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/kernel/linux/linux-5.10/drivers/clk/analogbits/
Dwrpll-cln28hpc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018-2019 SiFive, Inc.
16 * pre-determined set of performance points.
19 * - Analog Bits "Wide Range PLL Datasheet", version 2015.10.01
20 * - SiFive FU540-C000 Manual v1p0, Chapter 7 "Clocking and Reset"
21 * https://static.dev.sifive.com/FU540-C000-v1.0.pdf
28 #include <linux/clk/analogbits-wrpll-cln28hpc.h>
30 /* MIN_INPUT_FREQ: minimum input clock frequency, in Hz (Fref_min) */
33 /* MAX_INPUT_FREQ: maximum input clock frequency, in Hz (Fref_max) */
36 /* MIN_POST_DIVIDE_REF_FREQ: minimum post-divider reference frequency, in Hz */
[all …]
/kernel/linux/linux-5.10/Documentation/ABI/testing/
Dsysfs-bus-iio-frequency-adf43713 Contact: linux-iio@vger.kernel.org
5 Stores the PLL frequency in Hz for channel Y.
6 Reading returns the actual frequency in Hz.
7 The ADF4371 has an integrated VCO with fundamendal output
8 frequency ranging from 4000000000 Hz 8000000000 Hz.
12 frequencies from 62500000 Hz to 8000000000 Hz.
17 8000000000 Hz to 16000000000 Hz.
20 16000000000 Hz to 32000000000 Hz.
23 all the other channels, since it involves changing the VCO
28 Contact: linux-iio@vger.kernel.org
[all …]
/kernel/linux/linux-5.10/drivers/video/fbdev/kyro/
DSTG4000InitDevice.c69 #define STG4K3_PLL_MIN_VCO_SC (100000000 >> STG4K3_PLL_SCALER) /* Min VCO rate */
70 #define STG4K3_PLL_MAX_VCO_SC (500000000 >> STG4K3_PLL_SCALER) /* Max VCO rate */
71 #define STG4K3_PLL_MINR_VCO_SC (100000000 >> STG4K3_PLL_SCALER) /* Min VCO rate (restricted) */
72 #define STG4K3_PLL_MAXR_VCO_SC (500000000 >> STG4K3_PLL_SCALER) /* Max VCO rate (restricted) */
73 #define STG4K3_PLL_MINR_VCO 100000000 /* Min VCO rate (restricted) */
74 #define STG4K3_PLL_MAX_VCO 500000000 /* Max VCO rate */
75 #define STG4K3_PLL_MAXR_VCO 500000000 /* Max VCO rate (restricted) */
101 /* Program SD-RAM interface */ in InitSDRAMRegisters()
129 /* Translate clock in Hz */ in ProgramClock()
130 coreClock *= 100; /* in Hz */ in ProgramClock()
[all …]
/kernel/linux/linux-4.19/drivers/video/fbdev/kyro/
DSTG4000InitDevice.c69 #define STG4K3_PLL_MIN_VCO_SC (100000000 >> STG4K3_PLL_SCALER) /* Min VCO rate */
70 #define STG4K3_PLL_MAX_VCO_SC (500000000 >> STG4K3_PLL_SCALER) /* Max VCO rate */
71 #define STG4K3_PLL_MINR_VCO_SC (100000000 >> STG4K3_PLL_SCALER) /* Min VCO rate (restricted) */
72 #define STG4K3_PLL_MAXR_VCO_SC (500000000 >> STG4K3_PLL_SCALER) /* Max VCO rate (restricted) */
73 #define STG4K3_PLL_MINR_VCO 100000000 /* Min VCO rate (restricted) */
74 #define STG4K3_PLL_MAX_VCO 500000000 /* Max VCO rate */
75 #define STG4K3_PLL_MAXR_VCO 500000000 /* Max VCO rate (restricted) */
101 /* Program SD-RAM interface */ in InitSDRAMRegisters()
129 /* Translate clock in Hz */ in ProgramClock()
130 coreClock *= 100; /* in Hz */ in ProgramClock()
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dfsl,plldig.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wen He <wen.he_1@nxp.com>
19 const: fsl,ls1028a-plldig
27 '#clock-cells':
30 fsl,vco-hz:
31 description: Optional for VCO frequency of the PLL in Hertz. The VCO frequency
35 its own desired VCO frequency for the PLL.
41 - compatible
[all …]
/kernel/linux/linux-5.10/drivers/clk/
Dclk-si544.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
45 /* VCO range is 10.8 .. 12.1 GHz, max depends on speed grade */
74 * struct clk_si544_muldiv - Multiplier/divider settings
79 * If ls_div_bits is non-zero, hs_div must be even
80 * @delta_m: Frequency shift for small -950..+950 ppm changes, 24 bit
93 return regmap_update_bits(data->regmap, SI544_REG_OE_STATE, in si544_enable_output()
117 err = regmap_read(data->regmap, SI544_REG_OE_STATE, &val); in si544_is_prepared()
131 err = regmap_bulk_read(data->regmap, SI544_REG_HS_DIV, reg, 2); in si544_get_muldiv()
135 settings->ls_div_bits = (reg[1] >> 4) & 0x07; in si544_get_muldiv()
[all …]
Dclk-plldig.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
35 /* Range of the VCO frequencies, in Hz */
39 /* Range of the output frequencies, in Hz */
72 val = readl(data->regs + PLLDIG_REG_PLLFM); in plldig_enable()
78 writel(val, data->regs + PLLDIG_REG_PLLFM); in plldig_enable()
88 val = readl(data->regs + PLLDIG_REG_PLLFM); in plldig_disable()
93 writel(val, data->regs + PLLDIG_REG_PLLFM); in plldig_disable()
100 return readl(data->regs + PLLDIG_REG_PLLFM) & in plldig_is_enabled()
110 val = readl(data->regs + PLLDIG_REG_PLLDV); in plldig_recalc_rate()
[all …]
Dclk-gemini.c1 // SPDX-License-Identifier: GPL-2.0
7 #define pr_fmt(fmt) "clk-gemini: " fmt
15 #include <linux/clk-provider.h>
21 #include <linux/reset-controller.h>
22 #include <dt-bindings/reset/cortina,gemini-reset.h>
23 #include <dt-bindings/clock/cortina,gemini-clock.h>
53 * struct gemini_data_data - Gemini gated clocks
67 * struct clk_gemini_pci - Gemini PCI clock
79 * struct gemini_reset - gemini reset controller
92 { 1, "security-gate", "secdiv", 0 },
[all …]
/kernel/linux/linux-5.10/drivers/media/dvb-frontends/
Dstb6100.c1 // SPDX-License-Identifier: GPL-2.0-or-later
74 [STB6100_VCO] = "VCO",
125 .addr = state->config->tuner_address, in stb6100_read_regs()
131 rc = i2c_transfer(state->i2c, &msg, 1); in stb6100_read_regs()
134 state->config->tuner_address, rc); in stb6100_read_regs()
136 return -EREMOTEIO; in stb6100_read_regs()
141 dprintk(verbose, FE_DEBUG, 1, " Read from 0x%02x", state->config->tuner_address); in stb6100_read_regs()
153 .addr = state->config->tuner_address + reg, in stb6100_read_reg()
159 i2c_transfer(state->i2c, &msg, 1); in stb6100_read_reg()
163 return -EINVAL; in stb6100_read_reg()
[all …]
/kernel/linux/linux-4.19/drivers/media/dvb-frontends/
Dstb6100.c86 [STB6100_VCO] = "VCO",
137 .addr = state->config->tuner_address, in stb6100_read_regs()
143 rc = i2c_transfer(state->i2c, &msg, 1); in stb6100_read_regs()
146 state->config->tuner_address, rc); in stb6100_read_regs()
148 return -EREMOTEIO; in stb6100_read_regs()
153 dprintk(verbose, FE_DEBUG, 1, " Read from 0x%02x", state->config->tuner_address); in stb6100_read_regs()
165 .addr = state->config->tuner_address + reg, in stb6100_read_reg()
171 i2c_transfer(state->i2c, &msg, 1); in stb6100_read_reg()
175 return -EINVAL; in stb6100_read_reg()
178 dprintk(verbose, FE_DEBUG, 1, " Read from 0x%02x", state->config->tuner_address); in stb6100_read_reg()
[all …]
/kernel/linux/linux-4.19/arch/powerpc/boot/
Dredboot.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 // include/asm-ppc/redboot.h
26 unsigned int bi_intfreq; /* Internal Freq, in Hz */
27 unsigned int bi_busfreq; /* Bus Freq, in Hz */
28 unsigned int bi_cpmfreq; /* CPM Freq, in Hz */
29 unsigned int bi_brgfreq; /* BRG Freq, in Hz */
30 unsigned int bi_vco; /* VCO Out from PLL */
31 unsigned int bi_pci_freq; /* PCI Freq, in Hz */
Dppcboot.h2 * This interface is used for compatibility with old U-boots *ONLY*.
23 * MA 02111-1307 USA
32 * include/asm-ppc/ppcboot.h
62 unsigned long bi_vco; /* VCO Out from PLL, in MHz */
72 unsigned int bi_procfreq; /* CPU (Internal) Freq, in Hz */
73 unsigned int bi_plb_busfreq; /* PLB Bus speed, in Hz */
74 unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */
98 unsigned int bi_opbfreq; /* OB clock in Hz */
Dppcboot-hotfoot.h2 * This interface is used for compatibility with old U-boots *ONLY*.
10 * least-offensive solution. Please direct all flames to:
12 * Solomon Peachy <solomon@linux-wlan.com>
35 * MA 02111-1307 USA
44 * include/asm-ppc/ppcboot.h
79 unsigned long bi_vco; /* VCO Out from PLL, in MHz */
89 unsigned int bi_procfreq; /* CPU (Internal) Freq, in Hz */
90 unsigned int bi_plb_busfreq; /* PLB Bus speed, in Hz */
91 unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */
95 unsigned int bi_pllouta_freq; /* PLL OUTA speed, in Hz */
[all …]
/kernel/linux/linux-5.10/arch/powerpc/boot/
Dredboot.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 // include/asm-ppc/redboot.h
26 unsigned int bi_intfreq; /* Internal Freq, in Hz */
27 unsigned int bi_busfreq; /* Bus Freq, in Hz */
28 unsigned int bi_cpmfreq; /* CPM Freq, in Hz */
29 unsigned int bi_brgfreq; /* BRG Freq, in Hz */
30 unsigned int bi_vco; /* VCO Out from PLL */
31 unsigned int bi_pci_freq; /* PCI Freq, in Hz */
Dppcboot.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * This interface is used for compatibility with old U-boots *ONLY*.
18 * include/asm-ppc/ppcboot.h
48 unsigned long bi_vco; /* VCO Out from PLL, in MHz */
58 unsigned int bi_procfreq; /* CPU (Internal) Freq, in Hz */
59 unsigned int bi_plb_busfreq; /* PLB Bus speed, in Hz */
60 unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */
84 unsigned int bi_opbfreq; /* OB clock in Hz */
Dppcboot-hotfoot.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * This interface is used for compatibility with old U-boots *ONLY*.
11 * least-offensive solution. Please direct all flames to:
13 * Solomon Peachy <solomon@linux-wlan.com>
30 * include/asm-ppc/ppcboot.h
65 unsigned long bi_vco; /* VCO Out from PLL, in MHz */
75 unsigned int bi_procfreq; /* CPU (Internal) Freq, in Hz */
76 unsigned int bi_plb_busfreq; /* PLB Bus speed, in Hz */
77 unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */
81 unsigned int bi_pllouta_freq; /* PLL OUTA speed, in Hz */
[all …]
/kernel/linux/linux-5.10/drivers/media/tuners/
Dmax2165.c1 // SPDX-License-Identifier: GPL-2.0-or-later
20 #include "tuner-i2c.h"
38 msg.addr = priv->config->i2c_address; in max2165_write_reg()
43 ret = i2c_transfer(priv->i2c, &msg, 1); in max2165_write_reg()
49 return (ret != 1) ? -EIO : 0; in max2165_write_reg()
55 u8 dev_addr = priv->config->i2c_address; in max2165_read_reg()
64 ret = i2c_transfer(priv->i2c, msg, 2); in max2165_read_reg()
67 return -EIO; in max2165_read_reg()
104 priv->tf_ntch_low_cfg = dat[0] >> 4; in max2165_read_rom_table()
105 priv->tf_ntch_hi_cfg = dat[0] & 0x0F; in max2165_read_rom_table()
[all …]
/kernel/linux/linux-4.19/drivers/media/tuners/
Dmax2165.c30 #include "tuner-i2c.h"
48 msg.addr = priv->config->i2c_address; in max2165_write_reg()
53 ret = i2c_transfer(priv->i2c, &msg, 1); in max2165_write_reg()
59 return (ret != 1) ? -EIO : 0; in max2165_write_reg()
65 u8 dev_addr = priv->config->i2c_address; in max2165_read_reg()
74 ret = i2c_transfer(priv->i2c, msg, 2); in max2165_read_reg()
77 return -EIO; in max2165_read_reg()
114 priv->tf_ntch_low_cfg = dat[0] >> 4; in max2165_read_rom_table()
115 priv->tf_ntch_hi_cfg = dat[0] & 0x0F; in max2165_read_rom_table()
116 priv->tf_balun_low_ref = dat[1] & 0x0F; in max2165_read_rom_table()
[all …]
/kernel/linux/linux-5.10/drivers/iio/frequency/
Dadf4371.c1 // SPDX-License-Identifier: GPL-2.0
63 #define ADF4371_MAX_OUT_RF8_FREQ ADF4371_MAX_VCO_FREQ /* Hz */
64 #define ADF4371_MIN_OUT_RF8_FREQ (ADF4371_MIN_VCO_FREQ / 64) /* Hz */
65 #define ADF4371_MAX_OUT_RF16_FREQ (ADF4371_MAX_VCO_FREQ * 2) /* Hz */
66 #define ADF4371_MIN_OUT_RF16_FREQ (ADF4371_MIN_VCO_FREQ * 2) /* Hz */
67 #define ADF4371_MAX_OUT_RF32_FREQ (ADF4371_MAX_VCO_FREQ * 4) /* Hz */
68 #define ADF4371_MIN_OUT_RF32_FREQ (ADF4371_MIN_VCO_FREQ * 4) /* Hz */
70 #define ADF4371_MAX_FREQ_PFD 250000000UL /* Hz */
71 #define ADF4371_MAX_FREQ_REFIN 600000000UL /* Hz */
73 /* MOD1 is a 24-bit primary modulus with fixed value of 2^25 */
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/iio/frequency/
Dadf4350.txt4 - compatible: Should be one of
7 - reg: SPI chip select numbert for the device
8 - spi-max-frequency: Max SPI frequency to use (< 20000000)
9 - clocks: From common clock binding. Clock is phandle to clock for
13 - gpios: GPIO Lock detect - If set with a valid phandle and GPIO number,
15 - adi,channel-spacing: Channel spacing in Hz (influences MODULUS).
16 - adi,power-up-frequency: If set in Hz the PLL tunes to
18 - adi,reference-div-factor: If set the driver skips dynamic calculation
20 - adi,reference-doubler-enable: Enables reference doubler.
21 - adi,reference-div2-enable: Enables reference divider.
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/iio/frequency/
Dadf4350.txt4 - compatible: Should be one of
7 - reg: SPI chip select numbert for the device
8 - spi-max-frequency: Max SPI frequency to use (< 20000000)
9 - clocks: From common clock binding. Clock is phandle to clock for
13 - gpios: GPIO Lock detect - If set with a valid phandle and GPIO number,
15 - adi,channel-spacing: Channel spacing in Hz (influences MODULUS).
16 - adi,power-up-frequency: If set in Hz the PLL tunes to
18 - adi,reference-div-factor: If set the driver skips dynamic calculation
20 - adi,reference-doubler-enable: Enables reference doubler.
21 - adi,reference-div2-enable: Enables reference divider.
[all …]
/kernel/linux/linux-4.19/drivers/clk/
Dclk-gemini.c1 // SPDX-License-Identifier: GPL-2.0
7 #define pr_fmt(fmt) "clk-gemini: " fmt
15 #include <linux/clk-provider.h>
21 #include <linux/reset-controller.h>
22 #include <dt-bindings/reset/cortina,gemini-reset.h>
23 #include <dt-bindings/clock/cortina,gemini-clock.h>
53 * struct gemini_data_data - Gemini gated clocks
67 * struct clk_gemini_pci - Gemini PCI clock
79 * struct gemini_reset - gemini reset controller
92 { 1, "security-gate", "secdiv", 0 },
[all …]
/kernel/linux/linux-4.19/drivers/gpu/drm/i915/
Dintel_dpll_mgr.c2 * Copyright © 2006-2016 Intel Corporation
30 * per-pipe or per-encoder dedicated PLLs, others allow the use of any PLL
52 for (i = 0; i < dev_priv->num_shared_dpll; i++) { in intel_atomic_duplicate_dpll_state()
53 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; in intel_atomic_duplicate_dpll_state()
55 shared_dpll[i] = pll->state; in intel_atomic_duplicate_dpll_state()
64 WARN_ON(!drm_modeset_is_locked(&s->dev->mode_config.connection_mutex)); in intel_atomic_get_shared_dpll_state()
66 if (!state->dpll_set) { in intel_atomic_get_shared_dpll_state()
67 state->dpll_set = true; in intel_atomic_get_shared_dpll_state()
69 intel_atomic_duplicate_dpll_state(to_i915(s->dev), in intel_atomic_get_shared_dpll_state()
70 state->shared_dpll); in intel_atomic_get_shared_dpll_state()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/gma500/
Dgma_display.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2006-2011 Intel Corporation
28 struct drm_device *dev = crtc->dev; in gma_pipe_has_type()
29 struct drm_mode_config *mode_config = &dev->mode_config; in gma_pipe_has_type()
32 list_for_each_entry(l_entry, &mode_config->connector_list, head) { in gma_pipe_has_type()
33 if (l_entry->encoder && l_entry->encoder->crtc == crtc) { in gma_pipe_has_type()
36 if (gma_encoder->type == type) in gma_pipe_has_type()
46 /* Wait for 20ms, i.e. one cycle at 50hz. */ in gma_wait_for_vblank()
53 struct drm_device *dev = crtc->dev; in gma_pipe_set_base()
54 struct drm_psb_private *dev_priv = dev->dev_private; in gma_pipe_set_base()
[all …]
/kernel/linux/linux-4.19/drivers/gpu/drm/gma500/
Dgma_display.c2 * Copyright © 2006-2011 Intel Corporation
15 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
34 struct drm_device *dev = crtc->dev; in gma_pipe_has_type()
35 struct drm_mode_config *mode_config = &dev->mode_config; in gma_pipe_has_type()
38 list_for_each_entry(l_entry, &mode_config->connector_list, head) { in gma_pipe_has_type()
39 if (l_entry->encoder && l_entry->encoder->crtc == crtc) { in gma_pipe_has_type()
42 if (gma_encoder->type == type) in gma_pipe_has_type()
52 /* Wait for 20ms, i.e. one cycle at 50hz. */ in gma_wait_for_vblank()
59 struct drm_device *dev = crtc->dev; in gma_pipe_set_base()
60 struct drm_psb_private *dev_priv = dev->dev_private; in gma_pipe_set_base()
[all …]

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