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7 12 which was in the kernel from 2.6.13-2.6.19 (version 13 never saw a kernel38 1) # of times sched_yield() was called43 3) # of times schedule() was called47 5) # of times try_to_wake_up() was called48 6) # of times try_to_wake_up() was called to wake up the local cpu70 1) # of times in this domain load_balance() was called when the71 cpu was idle73 the load did not require balancing when the cpu was idle75 more tasks and failed, when the cpu was idle77 load_balance() in this domain when the cpu was idle[all …]
11 12 which was in the kernel from 2.6.13-2.6.19 (version 13 never saw a kernel43 1) # of times sched_yield() was called49 3) # of times schedule() was called54 5) # of times try_to_wake_up() was called55 6) # of times try_to_wake_up() was called to wake up the local cpu78 1) # of times in this domain load_balance() was called when the79 cpu was idle81 the load did not require balancing when the cpu was idle83 more tasks and failed, when the cpu was idle85 load_balance() in this domain when the cpu was idle[all …]
41 "BriefDescription": "Cycles when a demand ifetch was pending",71 …"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for an instru…72 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was chip pum…89 …"BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from an…90 …"PublicDescription": "The processor's Instruction cache was reloaded with Modified (M) data from a…95 …"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from anot…96 …"PublicDescription": "The processor's Instruction cache was reloaded with Shared (S) data from ano…101 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on a di…102 …"PublicDescription": "The processor's Instruction cache was reloaded from another chip's L4 on a d…107 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's memory on …[all …]
5 …"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for all data …6 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was chip pum…11 …"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for a demand …12 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was chip pum…17 …"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the sam…18 …"PublicDescription": "The processor's data cache was reloaded from another chip's memory on the sa…23 …"BriefDescription": "The processor's data cache was reloaded from the local chip's Memory due to a…24 …"PublicDescription": "The processor's data cache was reloaded from the local chip's Memory due to …29 …"BriefDescription": "The processor's data cache was reloaded from a memory location including L4 f…30 …"PublicDescription": "The processor's data cache was reloaded from a memory location including L4 …[all …]
5 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c…6 …"PublicDescription": "The processor's data cache was reloaded with Modified (M) data from another …11 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chi…12 …"PublicDescription": "The processor's data cache was reloaded with Shared (S) data from another ch…17 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different…18 …"PublicDescription": "The processor's data cache was reloaded from another chip's L4 on a differen…23 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a demand …24 …"PublicDescription": "The processor's data cache was reloaded from local core's L2 due to either o…35 …"BriefDescription": "The processor's data cache was reloaded from a location other than the local …36 …"PublicDescription": "The processor's data cache was reloaded from a location other than the local…[all …]
23 …"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for all data …24 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was chip pum…29 …"BriefDescription": "Initial and Final Pump Scope and data sourced across this scope was group pum…30 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was group pu…36 …data from source that was at smaller scope(Chip) Final pump was group pump and initial pump was ch…42 … ended up larger than Initial Pump Scope (Chip) Final pump was group pump and initial pump was chi…59 …"BriefDescription": "Initial and Final Pump Scope was system pump for all data types (demand load,…60 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was system p…65 … (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope…66 …e(system) got data from source that was at smaller scope(Chip/group) Final pump was system pump an…[all …]
29 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from anothe…35 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another …41 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 due to a data…47 …"BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the loc…53 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without d…59 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 without confl…65 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 due to a data…71 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch…77 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without dispa…83 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without confl…[all …]
5 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c…6 …"PublicDescription": "The processor's data cache was reloaded with Modified (M) data from another …11 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chi…12 …"PublicDescription": "The processor's data cache was reloaded with Shared (S) data from another ch…17 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different…18 …"PublicDescription": "The processor's data cache was reloaded from another chip's L4 on a differen…23 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a demand …24 …"PublicDescription": "The processor's data cache was reloaded from local core's L2 due to either o…35 …"BriefDescription": "The processor's data cache was reloaded from a localtion other than the local…36 …"PublicDescription": "The processor's data cache was reloaded from a localtion other than the loca…[all …]
10 …"BriefDescription": "A Page Directory Entry was reloaded to a level 1 page walk cache from beyond …15 …"BriefDescription": "An instruction was marked. Includes both Random Instruction Sampling (RIS) at…20 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another …25 …"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the sam…35 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 with disp…45 …A Page Table Entry was reloaded to a level 3 page walk cache from the core's L2 data cache. This i…50 …A Page Table Entry was reloaded to a level 3 page walk cache from the core's L3 data cache. This i…60 …"BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due…65 …"BriefDescription": "An instruction was marked at decode time. Random Instruction Sampling (RIS) o…70 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another …[all …]
5 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from anothe…15 …"BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the loc…25 …"BriefDescription": "Finish stall because the NTF instruction was a load or store that was held in…40 … (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope…50 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c…55 …"BriefDescription": "The processor's data cache was reloaded from local core's L3 without conflict…70 …"BriefDescription": "Finish stall because the NTF instruction was a store waiting for a slot in th…85 …"BriefDescription": "Finish stall because the NTF instruction was a stcx waiting for response from…95 …"BriefDescription": "The processor's data cache was reloaded from local core's L3 without dispatch…115 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another …[all …]
15 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another cor…25 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the …35 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another …60 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another …70 …"BriefDescription": "The processor's data cache was reloaded from a location other than the local …75 …"BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data fro…80 …"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from anot…95 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c…100 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on the same…115 …"BriefDescription": "Finish stall because the NTF instruction was a vector instruction issued to t…[all …]
10 Soon after the V4L API was added to the kernel it was criticised as too15 another four years and two stable kernel releases until the new API was23 1998-08-27: The :c:func:`select()` function was introduced.27 1998-09-18: The ``VIDIOC_NONCAP`` ioctl was replaced by the otherwise39 1998-10-02: The ``id`` field was removed from41 renamed. The :ref:`VIDIOC_QUERYSTD` ioctl was45 Codec API was released.50 1998-11-12: The read/write directon of some ioctls was misdefined.57 with ``V4L2_CID_AUDIO``. The ``V4L2_MAJOR`` define was removed from58 ``videodev.h`` since it was only used once in the ``videodev`` kernel[all …]
9 Soon after the V4L API was added to the kernel it was criticised as too14 another four years and two stable kernel releases until the new API was23 1998-08-27: The :ref:`select() <func-select>` function was introduced.27 1998-09-18: The ``VIDIOC_NONCAP`` ioctl was replaced by the otherwise39 1998-10-02: The ``id`` field was removed from struct41 renamed. The :ref:`VIDIOC_QUERYSTD` ioctl was45 Codec API was released.50 1998-11-12: The read/write directon of some ioctls was misdefined.57 with ``V4L2_CID_AUDIO``. The ``V4L2_MAJOR`` define was removed from58 ``videodev.h`` since it was only used once in the ``videodev`` kernel[all …]
21 # 7 was sys_waitpid31 # 17 was sys_break32 # 18 was sys_stat42 # 28 was sys_fstat45 # 31 was sys_stty46 # 32 was sys_gtty49 # 35 was sys_ftime58 # 44 was sys_prof62 # 48 was sys_signal67 # 53 was sys_lock[all …]
7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in…14 …een written into The Translation Lookaside Buffer 2 (TLB2) and the request was made by the data ca…28 …entry was written into the Combined Region and Segment Table Entry array in the Level-2 TLB for a …35 …"PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB"42 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from the Le…49 …een written into the Translation Lookaside Buffer 2 (TLB2) and the request was made by the instruc…63 …e to the Level-1 Instruction cache directory where the returned cache line was sourced from the Le…70 …"PublicDescription": "A translation entry was written into the Page Table Entry array in the Level…112 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from an On-…119 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chi…[all …]
7 …_RO_EXCL_WRITES A directory write to the Level-1 Data cache where the line was originally in a Rea…14 …een written into The Translation Lookaside Buffer 2 (TLB2) and the request was made by the data ca…28 …entry was written into the Combined Region and Segment Table Entry array in the Level-2 TLB for a …35 …"PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB"42 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from the Le…49 …een written into the Translation Lookaside Buffer 2 (TLB2) and the request was made by the instruc…63 …e to the Level-1 Instruction cache directory where the returned cache line was sourced from the Le…70 …"PublicDescription": "A translation entry was written into the Page Table Entry array in the Level…112 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from an On-…119 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chi…[all …]
7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in…42 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from the Le…63 …e to the Level-1 Instruction cache directory where the returned cache line was sourced from the Le…112 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from an On-…119 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from an On-…126 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from an On-…133 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from an On-…140 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from an On-…147 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from an On-…154 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from an On-…[all …]
7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in…14 …een written into The Translation Lookaside Buffer 2 (TLB2) and the request was made by the data ca…28 …"PublicDescription": "A translation entry was written into the Combined Region and Segment Table E…35 …"PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB"42 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from the Le…49 …een written into the Translation Lookaside Buffer 2 (TLB2) and the request was made by the instruc…63 …e to the Level-1 Instruction cache directory where the returned cache line was sourced from the Le…70 …"PublicDescription": "A translation entry was written into the Page Table Entry array in the Level…112 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from an On-…119 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chi…[all …]