| /kernel/linux/linux-4.19/arch/nios2/mm/ |
| D | tlb.c | 55 unsigned int way; in flush_tlb_one_pid() local
60 /* remember pid/way until we return. */ in flush_tlb_one_pid()
65 for (way = 0; way < cpuinfo.tlb_num_ways; way++) { in flush_tlb_one_pid()
70 tlbmisc = pid_misc | TLBMISC_RD | (way << TLBMISC_WAY_SHIFT); in flush_tlb_one_pid()
78 ((PAGE_SIZE * cpuinfo.tlb_num_lines) * way) + in flush_tlb_one_pid()
80 pr_debug("Flush entry by writing %#lx way=%dl pid=%ld\n", in flush_tlb_one_pid()
81 vaddr, way, (pid_misc >> TLBMISC_PID_SHIFT)); in flush_tlb_one_pid()
85 (way << TLBMISC_WAY_SHIFT); in flush_tlb_one_pid()
119 unsigned int way; in flush_tlb_one() local
124 /* remember pid/way until we return. */ in flush_tlb_one()
[all …]
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| /kernel/linux/linux-5.10/arch/nios2/mm/ |
| D | tlb.c | 47 unsigned int way; in replace_tlb_one_pid() local
50 /* remember pid/way until we return. */ in replace_tlb_one_pid()
55 for (way = 0; way < cpuinfo.tlb_num_ways; way++) { in replace_tlb_one_pid()
60 tlbmisc = TLBMISC_RD | (way << TLBMISC_WAY_SHIFT); in replace_tlb_one_pid()
73 (way << TLBMISC_WAY_SHIFT); in replace_tlb_one_pid()
126 unsigned int way; in flush_tlb_one() local
131 /* remember pid/way until we return. */ in flush_tlb_one()
136 for (way = 0; way < cpuinfo.tlb_num_ways; way++) { in flush_tlb_one()
140 tlbmisc = TLBMISC_RD | (way << TLBMISC_WAY_SHIFT); in flush_tlb_one()
147 pr_debug("Flush entry by writing way=%dl pid=%ld\n", in flush_tlb_one()
[all …]
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| /kernel/linux/linux-4.19/arch/x86/kernel/cpu/ |
| D | cacheinfo.c | 44 { 0x06, LVL_1_INST, 8 }, /* 4-way set assoc, 32 byte line size */
45 { 0x08, LVL_1_INST, 16 }, /* 4-way set assoc, 32 byte line size */
46 { 0x09, LVL_1_INST, 32 }, /* 4-way set assoc, 64 byte line size */
47 { 0x0a, LVL_1_DATA, 8 }, /* 2 way set assoc, 32 byte line size */
48 { 0x0c, LVL_1_DATA, 16 }, /* 4-way set assoc, 32 byte line size */
49 { 0x0d, LVL_1_DATA, 16 }, /* 4-way set assoc, 64 byte line size */
50 { 0x0e, LVL_1_DATA, 24 }, /* 6-way set assoc, 64 byte line size */
51 { 0x21, LVL_2, 256 }, /* 8-way set assoc, 64 byte line size */
52 { 0x22, LVL_3, 512 }, /* 4-way set assoc, sectored cache, 64 byte line size */
53 { 0x23, LVL_3, MB(1) }, /* 8-way set assoc, sectored cache, 64 byte line size */
[all …]
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| D | intel.c | 36 * allow a way to override the automatic disabling of MPX.
781 * One has 256kb of cache, the other 512. We have no way in intel_size_cache()
789 * Intel Quark SoC X1000 contains a 4-way set associative in intel_size_cache()
820 { 0x01, TLB_INST_4K, 32, " TLB_INST 4 KByte pages, 4-way set associative" },
822 { 0x03, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way set associative" },
823 { 0x04, TLB_DATA_4M, 8, " TLB_DATA 4 MByte pages, 4-way set associative" },
824 { 0x05, TLB_DATA_4M, 32, " TLB_DATA 4 MByte pages, 4-way set associative" },
825 { 0x0b, TLB_INST_4M, 4, " TLB_INST 4 MByte pages, 4-way set associative" },
831 { 0x56, TLB_DATA0_4M, 16, " TLB_DATA0 4 MByte pages, 4-way set associative" },
832 { 0x57, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, 4-way associative" },
[all …]
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| /kernel/linux/linux-5.10/arch/x86/kernel/cpu/ |
| D | cacheinfo.c | 45 { 0x06, LVL_1_INST, 8 }, /* 4-way set assoc, 32 byte line size */
46 { 0x08, LVL_1_INST, 16 }, /* 4-way set assoc, 32 byte line size */
47 { 0x09, LVL_1_INST, 32 }, /* 4-way set assoc, 64 byte line size */
48 { 0x0a, LVL_1_DATA, 8 }, /* 2 way set assoc, 32 byte line size */
49 { 0x0c, LVL_1_DATA, 16 }, /* 4-way set assoc, 32 byte line size */
50 { 0x0d, LVL_1_DATA, 16 }, /* 4-way set assoc, 64 byte line size */
51 { 0x0e, LVL_1_DATA, 24 }, /* 6-way set assoc, 64 byte line size */
52 { 0x21, LVL_2, 256 }, /* 8-way set assoc, 64 byte line size */
53 { 0x22, LVL_3, 512 }, /* 4-way set assoc, sectored cache, 64 byte line size */
54 { 0x23, LVL_3, MB(1) }, /* 8-way set assoc, sectored cache, 64 byte line size */
[all …]
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| /kernel/linux/linux-4.19/arch/sh/mm/ |
| D | cache-sh2a.c | 27 static void sh2a_flush_oc_line(unsigned long v, int way) in sh2a_flush_oc_line() argument
29 unsigned long addr = (v & 0x000007f0) | (way << 11); in sh2a_flush_oc_line()
77 int way; in sh2a__flush_wback_region() local
78 for (way = 0; way < nr_ways; way++) { in sh2a__flush_wback_region()
80 sh2a_flush_oc_line(v, way); in sh2a__flush_wback_region()
107 int way; in sh2a__flush_purge_region() local
109 for (way = 0; way < nr_ways; way++) in sh2a__flush_purge_region()
110 sh2a_flush_oc_line(v, way); in sh2a__flush_purge_region()
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| D | cache-sh2.c | 29 int way; in sh2__flush_wback_region() local
30 for (way = 0; way < 4; way++) { in sh2__flush_wback_region()
31 unsigned long data = __raw_readl(addr | (way << 12)); in sh2__flush_wback_region()
34 __raw_writel(data, addr | (way << 12)); in sh2__flush_wback_region()
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| D | cache-debugfs.c | 29 unsigned int waysize, way; in cache_seq_show() local
66 for (way = 0; way < cache->ways; way++) { in cache_seq_show()
71 seq_printf(file, "Way %d\n", way); in cache_seq_show()
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| /kernel/linux/linux-5.10/arch/sh/mm/ |
| D | cache-sh2a.c | 26 static void sh2a_flush_oc_line(unsigned long v, int way) in sh2a_flush_oc_line() argument
28 unsigned long addr = (v & 0x000007f0) | (way << 11); in sh2a_flush_oc_line()
76 int way; in sh2a__flush_wback_region() local
77 for (way = 0; way < nr_ways; way++) { in sh2a__flush_wback_region()
79 sh2a_flush_oc_line(v, way); in sh2a__flush_wback_region()
106 int way; in sh2a__flush_purge_region() local
108 for (way = 0; way < nr_ways; way++) in sh2a__flush_purge_region()
109 sh2a_flush_oc_line(v, way); in sh2a__flush_purge_region()
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| D | cache-sh2.c | 28 int way; in sh2__flush_wback_region() local
29 for (way = 0; way < 4; way++) { in sh2__flush_wback_region()
30 unsigned long data = __raw_readl(addr | (way << 12)); in sh2__flush_wback_region()
33 __raw_writel(data, addr | (way << 12)); in sh2__flush_wback_region()
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| D | cache-debugfs.c | 29 unsigned int waysize, way; in cache_seq_show() local
66 for (way = 0; way < cache->ways; way++) { in cache_seq_show()
71 seq_printf(file, "Way %d\n", way); in cache_seq_show()
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| /kernel/linux/linux-4.19/arch/xtensa/include/asm/ |
| D | tlbflush.h | 130 static inline void write_dtlb_entry (pte_t entry, int way) in write_dtlb_entry() argument
133 : : "r" (way), "r" (entry) ); in write_dtlb_entry()
136 static inline void write_itlb_entry (pte_t entry, int way) in write_itlb_entry() argument
139 : : "r" (way), "r" (entry) ); in write_itlb_entry()
179 static inline unsigned long read_dtlb_virtual (int way) in read_dtlb_virtual() argument
182 __asm__ __volatile__("rdtlb0 %0, %1\n\t" : "=a" (tmp), "+a" (way)); in read_dtlb_virtual()
186 static inline unsigned long read_dtlb_translation (int way) in read_dtlb_translation() argument
189 __asm__ __volatile__("rdtlb1 %0, %1\n\t" : "=a" (tmp), "+a" (way)); in read_dtlb_translation()
193 static inline unsigned long read_itlb_virtual (int way) in read_itlb_virtual() argument
196 __asm__ __volatile__("ritlb0 %0, %1\n\t" : "=a" (tmp), "+a" (way)); in read_itlb_virtual()
[all …]
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| /kernel/linux/linux-5.10/arch/xtensa/include/asm/ |
| D | tlbflush.h | 130 static inline void write_dtlb_entry (pte_t entry, int way) in write_dtlb_entry() argument
133 : : "r" (way), "r" (entry) ); in write_dtlb_entry()
136 static inline void write_itlb_entry (pte_t entry, int way) in write_itlb_entry() argument
139 : : "r" (way), "r" (entry) ); in write_itlb_entry()
176 static inline unsigned long read_dtlb_virtual (int way) in read_dtlb_virtual() argument
179 __asm__ __volatile__("rdtlb0 %0, %1\n\t" : "=a" (tmp), "+a" (way)); in read_dtlb_virtual()
183 static inline unsigned long read_dtlb_translation (int way) in read_dtlb_translation() argument
186 __asm__ __volatile__("rdtlb1 %0, %1\n\t" : "=a" (tmp), "+a" (way)); in read_dtlb_translation()
190 static inline unsigned long read_itlb_virtual (int way) in read_itlb_virtual() argument
193 __asm__ __volatile__("ritlb0 %0, %1\n\t" : "=a" (tmp), "+a" (way)); in read_itlb_virtual()
[all …]
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| /kernel/linux/linux-5.10/arch/arm/mm/ |
| D | cache-xsc3l2.c | 44 int set, way; in xsc3_l2_inv_all() local
49 for (way = 0; way < CACHE_WAY_PER_SET; way++) { in xsc3_l2_inv_all()
50 set_way = (way << 29) | (set << 5); in xsc3_l2_inv_all()
149 * optimize L2 flush all operation by set/way format
154 int set, way; in xsc3_l2_flush_all() local
159 for (way = 0; way < CACHE_WAY_PER_SET; way++) { in xsc3_l2_flush_all()
160 set_way = (way << 29) | (set << 5); in xsc3_l2_flush_all()
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| /kernel/linux/linux-4.19/arch/arm/mm/ |
| D | cache-xsc3l2.c | 56 int set, way; in xsc3_l2_inv_all() local
61 for (way = 0; way < CACHE_WAY_PER_SET; way++) { in xsc3_l2_inv_all()
62 set_way = (way << 29) | (set << 5); in xsc3_l2_inv_all()
161 * optimize L2 flush all operation by set/way format
166 int set, way; in xsc3_l2_flush_all() local
171 for (way = 0; way < CACHE_WAY_PER_SET; way++) { in xsc3_l2_flush_all()
172 set_way = (way << 29) | (set << 5); in xsc3_l2_flush_all()
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| /kernel/linux/linux-4.19/arch/openrisc/include/asm/ |
| D | spr_defs.h | 76 #define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100) argument
77 #define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100) argument
78 #define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100) argument
79 #define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100) argument
84 #define SPR_ITLBMR_BASE(WAY) (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100) argument
85 #define SPR_ITLBMR_LAST(WAY) (SPRGROUP_IMMU + 0x27f + (WAY) * 0x100) argument
86 #define SPR_ITLBTR_BASE(WAY) (SPRGROUP_IMMU + 0x280 + (WAY) * 0x100) argument
87 #define SPR_ITLBTR_LAST(WAY) (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x100) argument
96 #define SPR_DCR_BASE(WAY) (SPRGROUP_DC + 0x200 + (WAY) * 0x200) argument
97 #define SPR_DCR_LAST(WAY) (SPRGROUP_DC + 0x3ff + (WAY) * 0x200) argument
[all …]
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| /kernel/linux/linux-5.10/arch/openrisc/include/asm/ |
| D | spr_defs.h | 72 #define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100) argument
73 #define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100) argument
74 #define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100) argument
75 #define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100) argument
80 #define SPR_ITLBMR_BASE(WAY) (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100) argument
81 #define SPR_ITLBMR_LAST(WAY) (SPRGROUP_IMMU + 0x27f + (WAY) * 0x100) argument
82 #define SPR_ITLBTR_BASE(WAY) (SPRGROUP_IMMU + 0x280 + (WAY) * 0x100) argument
83 #define SPR_ITLBTR_LAST(WAY) (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x100) argument
92 #define SPR_DCR_BASE(WAY) (SPRGROUP_DC + 0x200 + (WAY) * 0x200) argument
93 #define SPR_DCR_LAST(WAY) (SPRGROUP_DC + 0x3ff + (WAY) * 0x200) argument
[all …]
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| /kernel/linux/linux-5.10/arch/x86/crypto/ |
| D | twofish_glue_3way.c | 3 * Glue Code for 3-way parallel assembler optimized version of Twofish
175 .base.cra_driver_name = "ecb-twofish-3way",
187 .base.cra_driver_name = "cbc-twofish-3way",
200 .base.cra_driver_name = "ctr-twofish-3way",
225 * On Atom, twofish-3way is slower than original assembler in is_blacklisted_cpu()
226 * implementation. Twofish-3way trades off some performance in in is_blacklisted_cpu()
238 * On Pentium 4, twofish-3way is slower than original assembler in is_blacklisted_cpu()
257 "twofish-x86_64-3way: performance on this CPU " in init()
259 "twofish-x86_64-3way.\n"); in init()
276 MODULE_DESCRIPTION("Twofish Cipher Algorithm, 3-way parallel asm optimized");
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| /kernel/linux/linux-4.19/Documentation/x86/ |
| D | entry_64.txt | 22 either way.
30 magically-generated functions that make their way to do_IRQ with
58 Now, there's a secondary complication: there's a cheap way to test
59 which mode the CPU is in and an expensive way.
61 The cheap way is to pick this info off the entry frame on the kernel
69 The expensive (paranoid) way is to read back the MSR_GS_BASE value
90 stack but before we executed SWAPGS, then the only safe way to check
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| /kernel/linux/linux-5.10/Documentation/x86/ |
| D | entry_64.rst | 28 either way.
36 magically-generated functions that make their way to do_IRQ with
64 Now, there's a secondary complication: there's a cheap way to test
65 which mode the CPU is in and an expensive way.
67 The cheap way is to pick this info off the entry frame on the kernel
75 The expensive (paranoid) way is to read back the MSR_GS_BASE value
96 stack but before we executed SWAPGS, then the only safe way to check
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| /kernel/linux/linux-4.19/arch/x86/crypto/ |
| D | twofish_glue_3way.c | 2 * Glue Code for 3-way parallel assembler optimized version of Twofish
187 .base.cra_driver_name = "ecb-twofish-3way",
199 .base.cra_driver_name = "cbc-twofish-3way",
212 .base.cra_driver_name = "ctr-twofish-3way",
237 * On Atom, twofish-3way is slower than original assembler in is_blacklisted_cpu()
238 * implementation. Twofish-3way trades off some performance in in is_blacklisted_cpu()
250 * On Pentium 4, twofish-3way is slower than original assembler in is_blacklisted_cpu()
269 "twofish-x86_64-3way: performance on this CPU " in init()
271 "twofish-x86_64-3way.\n"); in init()
288 MODULE_DESCRIPTION("Twofish Cipher Algorithm, 3-way parallel asm optimized");
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| /kernel/linux/linux-5.10/arch/mips/include/asm/octeon/ |
| D | cvmx-l2c.h | 183 * Return the L2 Cache way partitioning for a given core.
199 * a way, while a 1 bit blocks the core from evicting any
200 * lines from that way. There must be at least one allowed
201 * way (0 bit) in the mask.
212 * Return the L2 Cache way partitioning for the hw blocks.
214 * Returns The mask specifying the reserved way. 0 bits in mask indicates
225 * a way, while a 1 bit blocks the core from evicting any
226 * lines from that way. There must be at least one allowed
227 * way (0 bit) in the mask.
295 * @index: Which way to read from.
[all …]
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| /kernel/linux/linux-4.19/arch/mips/include/asm/octeon/ |
| D | cvmx-l2c.h | 183 * Return the L2 Cache way partitioning for a given core.
199 * a way, while a 1 bit blocks the core from evicting any
200 * lines from that way. There must be at least one allowed
201 * way (0 bit) in the mask.
212 * Return the L2 Cache way partitioning for the hw blocks.
214 * Returns The mask specifying the reserved way. 0 bits in mask indicates
225 * a way, while a 1 bit blocks the core from evicting any
226 * lines from that way. There must be at least one allowed
227 * way (0 bit) in the mask.
295 * @index: Which way to read from.
[all …]
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| /kernel/linux/linux-5.10/arch/mips/kernel/ |
| D | bmips_5xxx_init.S | 126 * Determine sets per way: IS
128 * This field contains the number of sets (i.e., indices) per way of
137 /* sets per way = (64<<IS) */
164 /* v0 now have sets per way, multiply it by line size now
174 * i) 0x0: Direct mapped, ii) 0x1: 2-way, iii) 0x2: 3-way, iv) 0x3:
175 * 4-way, v) 0x4 - 0x7: Reserved.
219 * Determine sets per way: IS
221 * This field contains the number of sets (i.e., indices) per way of
230 /* sets per way = (64<<IS) */
256 /* v0 now have sets per way, multiply it by line size now
[all …]
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| /kernel/linux/linux-4.19/arch/mips/kernel/ |
| D | bmips_5xxx_init.S | 126 * Determine sets per way: IS
128 * This field contains the number of sets (i.e., indices) per way of
137 /* sets per way = (64<<IS) */
164 /* v0 now have sets per way, multiply it by line size now
174 * i) 0x0: Direct mapped, ii) 0x1: 2-way, iii) 0x2: 3-way, iv) 0x3:
175 * 4-way, v) 0x4 - 0x7: Reserved.
219 * Determine sets per way: IS
221 * This field contains the number of sets (i.e., indices) per way of
230 /* sets per way = (64<<IS) */
256 /* v0 now have sets per way, multiply it by line size now
[all …]
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