| /kernel/linux/linux-5.10/Documentation/driver-api/md/ |
| D | raid5-cache.rst | 7 caches data to the RAID disks. The cache can be in write-through (supported
8 since 4.4) or write-back mode (supported since 4.10). mdadm (supported since
9 3.4) has a new option '--write-journal' to create array with cache. Please
11 in write-through mode. A user can switch it to write-back mode by::
13 echo "write-back" > /sys/block/md0/md/journal_mode
15 And switch it back to write-through mode by::
17 echo "write-through" > /sys/block/md0/md/journal_mode
22 write-through mode
25 This mode mainly fixes the 'write hole' issue. For RAID 4/5/6 array, an unclean
27 and parity don't match. The reason is that a stripe write involves several RAID
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| /kernel/linux/linux-4.19/Documentation/md/ |
| D | raid5-cache.txt | 5 caches data to the RAID disks. The cache can be in write-through (supported
6 since 4.4) or write-back mode (supported since 4.10). mdadm (supported since
7 3.4) has a new option '--write-journal' to create array with cache. Please
9 in write-through mode. A user can switch it to write-back mode by:
11 echo "write-back" > /sys/block/md0/md/journal_mode
13 And switch it back to write-through mode by:
15 echo "write-through" > /sys/block/md0/md/journal_mode
21 write-through mode:
23 This mode mainly fixes the 'write hole' issue. For RAID 4/5/6 array, an unclean
25 and parity don't match. The reason is that a stripe write involves several RAID
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| /kernel/linux/linux-5.10/include/dt-bindings/memory/ |
| D | tegra194-mc.h | 149 /* MSS internal memqual MIU7 write clients */
161 /* High-definition audio (HDA) write clients */
165 /* SATA write clients */
171 /* ISP Write client for Crossbar A */
173 /* ISP Write client Crossbar B */
177 /* XUSB_HOST write clients */
181 /* XUSB_DEV write clients */
189 /* sdmmca memory write client */
191 /* sdmmc memory write client */
193 /* sdmmcd memory write client */
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| D | tegra186-mc.h | 139 /* ISP Write client for Crossbar A */
141 /* ISP Write client Crossbar B */
153 /* TSEC Memory Write Client Description */
167 /* sdmmca memory write client */
169 /* sdmmcb memory write client */
171 /* sdmmc memory write client */
173 /* sdmmcd memory write client */
177 /* VI Write client */
189 /* SE Memory Write Client Description */
197 /* TSECB Memory Write Client Description */
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| /kernel/linux/linux-4.19/tools/perf/pmu-events/arch/arm64/ |
| D | armv8-recommended.json | 9 "PublicDescription": "Attributable Level 1 data cache access, write",
12 "BriefDescription": "L1D cache access, write"
21 "PublicDescription": "Attributable Level 1 data cache refill, write",
24 "BriefDescription": "L1D cache refill, write"
39 "PublicDescription": "Attributable Level 1 data cache Write-Back, victim",
42 "BriefDescription": "L1D cache Write-Back, victim"
45 "PublicDescription": "Level 1 data cache Write-Back, cleaning and coherency",
48 "BriefDescription": "L1D cache Write-Back, cleaning and coherency"
63 "PublicDescription": "Attributable Level 1 data TLB refill, write",
66 "BriefDescription": "L1D tlb refill, write"
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| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/arm64/ |
| D | armv8-recommended.json | 9 "PublicDescription": "Attributable Level 1 data cache access, write",
12 "BriefDescription": "L1D cache access, write"
21 "PublicDescription": "Attributable Level 1 data cache refill, write",
24 "BriefDescription": "L1D cache refill, write"
39 "PublicDescription": "Attributable Level 1 data cache Write-Back, victim",
42 "BriefDescription": "L1D cache Write-Back, victim"
45 "PublicDescription": "Level 1 data cache Write-Back, cleaning and coherency",
48 "BriefDescription": "L1D cache Write-Back, cleaning and coherency"
63 "PublicDescription": "Attributable Level 1 data TLB refill, write",
66 "BriefDescription": "L1D tlb refill, write"
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|
| /kernel/linux/linux-4.19/arch/arm/mach-pxa/include/mach/ |
| D | regs-uart.h | 12 #define FFTHR __REG(0x40100000) /* Transmit Holding Register (write only) */
13 #define FFIER __REG(0x40100004) /* Interrupt Enable Register (read/write) */
15 #define FFFCR __REG(0x40100008) /* FIFO Control Register (write only) */
16 #define FFLCR __REG(0x4010000C) /* Line Control Register (read/write) */
17 #define FFMCR __REG(0x40100010) /* Modem Control Register (read/write) */
20 #define FFSPR __REG(0x4010001C) /* Scratch Pad Register (read/write) */
21 #define FFISR __REG(0x40100020) /* Infrared Selection Register (read/write) */
22 #define FFDLL __REG(0x40100000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
23 #define FFDLH __REG(0x40100004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
28 #define BTTHR __REG(0x40200000) /* Transmit Holding Register (write only) */
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| /kernel/linux/linux-5.10/arch/arm/mach-pxa/include/mach/ |
| D | regs-uart.h | 12 #define FFTHR __REG(0x40100000) /* Transmit Holding Register (write only) */
13 #define FFIER __REG(0x40100004) /* Interrupt Enable Register (read/write) */
15 #define FFFCR __REG(0x40100008) /* FIFO Control Register (write only) */
16 #define FFLCR __REG(0x4010000C) /* Line Control Register (read/write) */
17 #define FFMCR __REG(0x40100010) /* Modem Control Register (read/write) */
20 #define FFSPR __REG(0x4010001C) /* Scratch Pad Register (read/write) */
21 #define FFISR __REG(0x40100020) /* Infrared Selection Register (read/write) */
22 #define FFDLL __REG(0x40100000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
23 #define FFDLH __REG(0x40100004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
28 #define BTTHR __REG(0x40200000) /* Transmit Holding Register (write only) */
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| /kernel/linux/linux-5.10/drivers/net/ethernet/aquantia/atlantic/macsec/ |
| D | macsec_api.h | 57 /*! Pack the fields of rec, and write the packed data into the
59 * rec - [IN] The bitfield values to write to the table row.
60 * table_index - The table row to write(max 23).
75 /*! Pack the fields of rec, and write the packed data into the
77 * rec - [IN] The bitfield values to write to the table row.
78 * table_index - The table row to write (max 47).
93 /*! Pack the fields of rec, and write the packed data into the
95 * rec - [IN] The bitfield values to write to the table row.
96 * table_index - The table row to write (max 31).
111 /*! Pack the fields of rec, and write the packed data into the
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| /kernel/linux/linux-4.19/Documentation/media/uapi/v4l/ |
| D | func-write.rst | 3 .. _func-write:
6 V4L2 write()
12 v4l2-write - Write to a V4L2 device
23 .. c:function:: ssize_t write( int fd, void *buf, size_t count )
24 :name: v4l2-write
41 :ref:`write() <func-write>` writes up to ``count`` bytes to the device
44 enables them. When ``count`` is zero, :ref:`write() <func-write>` returns 0
58 variable is set appropriately. In this case the next write will start at
64 available to write the data immediately.
70 The driver does not support multiple write streams and the device is
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| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/cascadelakex/ |
| D | uncore-memory.json | 13 "BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr",
77 …"BriefDescription": "Write requests allocated in the PMM Write Pending Queue for Intel Optane DC p…
85 …"BriefDescription": "Write requests allocated in the PMM Write Pending Queue for Intel Optane DC p…
102 …"BriefDescription": "Intel Optane DC persistent memory bandwidth write (MB). Derived from unc_m_pm…
105 "EventName": "UNC_M_PMM_BANDWIDTH.WRITE",
143 "BriefDescription": "DRAM Page Activate commands sent due to a write request",
148 …ption": "Counts DRAM Page Activate commands sent on this channel due to a write request to the iMC…
158 …write on DRAM, so this event increments for every read and write. This event counts whether AutoPr…
168 …write on DRAM, and this event increments for every regular read. This event only counts regular r…
178 …write, on a per channel basis. CAS commands are issued to specify the address to read or write on…
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| /kernel/linux/linux-5.10/Documentation/filesystems/ |
| D | zonefs.rst | 12 device support (e.g. f2fs), zonefs does not hide the sequential write
14 write zones of the device must be written sequentially starting from the end
38 conventional zones. Any read or write access can be executed, similarly to a
41 sequentially. Each sequential zone has a write pointer maintained by the
42 device that keeps track of the mandatory start LBA position of the next write
43 to the device. As a result of this write constraint, LBAs in a sequential zone
53 to, for instance, reduce internal write amplification due to garbage collection.
73 information. File sizes come from the device zone type and write pointer
80 state to make it read-only, preventing any data write.
94 For sequential write zones, the sub-directory "seq" is used.
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| /kernel/linux/linux-5.10/arch/mips/kernel/ |
| D | cps-vec-ns16550.S | 32 * _mips_cps_putc() - write a character to the UART
33 * @a0: ASCII character to write
45 * _mips_cps_puts() - write a string to the UART
49 * Write a null-terminated ASCII string to the UART.
65 * _mips_cps_putx4 - write a 4b hex value to the UART
66 * @a0: the 4b value to write to the UART
69 * Write a single hexadecimal character to the UART.
82 * _mips_cps_putx8 - write an 8b hex value to the UART
83 * @a0: the 8b value to write to the UART
86 * Write an 8 bit value (ie. 2 hexadecimal characters) to the UART.
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| /kernel/linux/linux-4.19/arch/mips/kernel/ |
| D | cps-vec-ns16550.S | 22 * _mips_cps_putc() - write a character to the UART
23 * @a0: ASCII character to write
35 * _mips_cps_puts() - write a string to the UART
39 * Write a null-terminated ASCII string to the UART.
55 * _mips_cps_putx4 - write a 4b hex value to the UART
56 * @a0: the 4b value to write to the UART
59 * Write a single hexadecimal character to the UART.
72 * _mips_cps_putx8 - write an 8b hex value to the UART
73 * @a0: the 8b value to write to the UART
76 * Write an 8 bit value (ie. 2 hexadecimal characters) to the UART.
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| /kernel/linux/linux-4.19/drivers/staging/comedi/drivers/ |
| D | ni_660x.c | 98 [NITIO_G0_INT_ACK] = { 0x004, 2 }, /* write */
100 [NITIO_G1_INT_ACK] = { 0x006, 2 }, /* write */
103 [NITIO_G0_CMD] = { 0x00c, 2 }, /* write */
105 [NITIO_G1_CMD] = { 0x00e, 2 }, /* write */
108 [NI660X_STC_DIO_OUTPUT] = { 0x014, 2 }, /* write */
109 [NI660X_STC_DIO_CONTROL] = { 0x016, 2 }, /* write */
112 [NITIO_G0_MODE] = { 0x034, 2 }, /* write */
114 [NITIO_G1_MODE] = { 0x036, 2 }, /* write */
116 [NITIO_G0_LOADA] = { 0x038, 4 }, /* write */
118 [NITIO_G0_LOADB] = { 0x03c, 4 }, /* write */
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| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/skylakex/ |
| D | uncore-memory.json | 13 "BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr",
77 "BriefDescription": "DRAM Page Activate commands sent due to a write request",
82 …ption": "Counts DRAM Page Activate commands sent on this channel due to a write request to the iMC…
92 …write on DRAM, so this event increments for every read and write. This event counts whether AutoPr…
102 …write on DRAM, and this event increments for every regular read. This event only counts regular r…
112 …write, on a per channel basis. CAS commands are issued to specify the address to read or write on…
117 …AM CAS (Column Address Strobe) Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode",
122 …cDescription": "Counts the total number or DRAM Write CAS commands issued on this channel while in…
145 "BriefDescription": "Write Pending Queue Allocations",
150 …Write Pending Queue (WPQ). The WPQ is used to schedule writes out to the memory controller and to…
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| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/s390/cf_z13/ |
| D | extended.json | 7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in…
42 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac…
63 …"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the retur…
112 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac…
119 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac…
126 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac…
133 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac…
140 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac…
147 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac…
154 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac…
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| /kernel/linux/linux-4.19/tools/perf/pmu-events/arch/s390/cf_z13/ |
| D | extended.json | 7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in…
42 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac…
63 …"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the retur…
112 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac…
119 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac…
126 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac…
133 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac…
140 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac…
147 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac…
154 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac…
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| /kernel/linux/linux-4.19/arch/parisc/kernel/ |
| D | perf_asm.S | 18 * along with this program; if not, write to the Free Software
569 ;* arg1 = 64-bit value to write
599 ; RDR 0 write sequence
601 sync ; RDR 0 write sequence
611 ; RDR 1 write sequence
623 ; RDR 2 write sequence
635 ; RDR 3 write sequence
647 ; RDR 4 write sequence
659 ; RDR 5 write sequence
671 ; RDR 6 write sequence
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| /kernel/linux/linux-4.19/drivers/media/i2c/adv748x/ |
| D | adv748x-core.c | 131 /* adv748x_write_block(): Write raw data with a maximum of I2C_SMBUS_BLOCK_MAX
198 * struct adv748x_reg_value - Register write instruction
201 * @value: value to write to @page at @reg
242 {ADV748X_PAGE_TXA, 0x31, 0x82}, /* ADI Required Write */
243 {ADV748X_PAGE_TXA, 0x1e, 0x40}, /* ADI Required Write */
248 {ADV748X_PAGE_TXA, 0xc1, 0x2b}, /* ADI Required Write */
250 {ADV748X_PAGE_TXA, 0x31, 0x80}, /* ADI Required Write */
257 {ADV748X_PAGE_TXA, 0x31, 0x82}, /* ADI Required Write */
258 {ADV748X_PAGE_TXA, 0x1e, 0x00}, /* ADI Required Write */
261 {ADV748X_PAGE_TXA, 0xc1, 0x3b}, /* ADI Required Write */
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| /kernel/linux/linux-5.10/arch/parisc/kernel/ |
| D | perf_asm.S | 556 ;* arg1 = 64-bit value to write
586 ; RDR 0 write sequence
588 sync ; RDR 0 write sequence
598 ; RDR 1 write sequence
610 ; RDR 2 write sequence
622 ; RDR 3 write sequence
634 ; RDR 4 write sequence
646 ; RDR 5 write sequence
658 ; RDR 6 write sequence
670 ; RDR 7 write sequence
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| /kernel/linux/linux-5.10/fs/ubifs/ |
| D | io.c | 16 * write-buffering support. Write buffers help to save space which otherwise
18 * Instead, data first goes to the write-buffer and is flushed when the
22 * UBIFS distinguishes between minimum write size (@c->min_io_size) and maximum
23 * write size (@c->max_write_size). The latter is the maximum amount of bytes
26 * @c->min_io_size <= @c->max_write_size. Write-buffers are of
28 * write-buffer is flushed, only the portion of it (aligned to @c->min_io_size
29 * boundary) which contains data is written, not the whole write-buffer,
33 * hand, we want to write in optimal @c->max_write_size bytes chunks, which
35 * other hand, we do not want to waste space when synchronizing the write
37 * the next write offset to be not aligned to @c->max_write_size bytes. So the
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| /kernel/linux/linux-4.19/fs/ubifs/ |
| D | io.c | 17 * this program; if not, write to the Free Software Foundation, Inc., 51
28 * write-buffering support. Write buffers help to save space which otherwise
30 * Instead, data first goes to the write-buffer and is flushed when the
34 * UBIFS distinguishes between minimum write size (@c->min_io_size) and maximum
35 * write size (@c->max_write_size). The latter is the maximum amount of bytes
38 * @c->min_io_size <= @c->max_write_size. Write-buffers are of
40 * write-buffer is flushed, only the portion of it (aligned to @c->min_io_size
41 * boundary) which contains data is written, not the whole write-buffer,
45 * hand, we want to write in optimal @c->max_write_size bytes chunks, which
47 * other hand, we do not want to waste space when synchronizing the write
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| /kernel/linux/linux-5.10/arch/sh/include/asm/ |
| D | watchdog.h | 72 * sh_wdt_write_cnt - Write to Counter
73 * @val: Value to write
76 * The upper byte is set manually on each write.
84 * sh_wdt_write_bst - Write to Counter
85 * @val: Value to write
88 * The upper byte is set manually on each write.
105 * sh_wdt_write_csr - Write to Control/Status Register
106 * @val: Value to write
109 * register. The upper byte is set manually on each write.
126 * sh_wdt_write_cnt - Write to Counter
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| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/s390/cf_z14/ |
| D | extended.json | 7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in…
42 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac…
63 …"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the retur…
112 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac…
119 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac…
126 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac…
133 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac…
140 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac…
147 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac…
154 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac…
[all …]
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