1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|* "Fast" Instruction Selector for the ARM target *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9 10// FastEmit Immediate Predicate functions. 11static bool Predicate_mod_imm(int64_t Imm) { 12 13 return ARM_AM::getSOImmVal(Imm) != -1; 14 15} 16static bool Predicate_imm0_65535(int64_t Imm) { 17 18 return Imm >= 0 && Imm < 65536; 19 20} 21static bool Predicate_imm0_7(int64_t Imm) { 22 23 return Imm >= 0 && Imm < 8; 24 25} 26static bool Predicate_imm8_255(int64_t Imm) { 27 28 return Imm >= 8 && Imm < 256; 29 30} 31static bool Predicate_imm0_255(int64_t Imm) { 32 return Imm >= 0 && Imm < 256; 33} 34static bool Predicate_t2_so_imm(int64_t Imm) { 35 36 return ARM_AM::getT2SOImmVal(Imm) != -1; 37 38} 39static bool Predicate_imm0_4095(int64_t Imm) { 40 41 return Imm >= 0 && Imm < 4096; 42 43} 44static bool Predicate_imm1_31(int64_t Imm) { 45 return Imm > 0 && Imm < 32; 46} 47static bool Predicate_imm0_31(int64_t Imm) { 48 49 return Imm >= 0 && Imm < 32; 50 51} 52static bool Predicate_shr_imm8(int64_t Imm) { 53 return Imm > 0 && Imm <= 8; 54} 55static bool Predicate_shr_imm16(int64_t Imm) { 56 return Imm > 0 && Imm <= 16; 57} 58static bool Predicate_shr_imm32(int64_t Imm) { 59 return Imm > 0 && Imm <= 32; 60} 61static bool Predicate_VectorIndex32(int64_t Imm) { 62 63 return ((uint64_t)Imm) < 2; 64 65} 66static bool Predicate_t2_so_imm_neg(int64_t Imm) { 67 68 return Imm && ARM_AM::getT2SOImmVal(-(uint32_t)Imm) != -1; 69 70} 71static bool Predicate_imm0_15(int64_t Imm) { 72 73 return Imm >= 0 && Imm < 16; 74 75} 76 77 78// FastEmit functions for ARMISD::CALL. 79 80unsigned fastEmit_ARMISD_CALL_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 81 if (RetVT.SimpleTy != MVT::isVoid) 82 return 0; 83 if ((Subtarget->hasV5TOps()) && (!Subtarget->isThumb())) { 84 return fastEmitInst_r(ARM::BLX, &ARM::GPRRegClass, Op0, Op0IsKill); 85 } 86 return 0; 87} 88 89unsigned fastEmit_ARMISD_CALL_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 90 switch (VT.SimpleTy) { 91 case MVT::i32: return fastEmit_ARMISD_CALL_MVT_i32_r(RetVT, Op0, Op0IsKill); 92 default: return 0; 93 } 94} 95 96// FastEmit functions for ARMISD::CALL_NOLINK. 97 98unsigned fastEmit_ARMISD_CALL_NOLINK_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 99 if (RetVT.SimpleTy != MVT::isVoid) 100 return 0; 101 if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) { 102 return fastEmitInst_r(ARM::tBX_CALL, &ARM::tGPRRegClass, Op0, Op0IsKill); 103 } 104 if ((!Subtarget->isThumb()) && (!Subtarget->hasV4TOps())) { 105 return fastEmitInst_r(ARM::BMOVPCRX_CALL, &ARM::tGPRRegClass, Op0, Op0IsKill); 106 } 107 if ((Subtarget->hasV4TOps()) && (!Subtarget->isThumb())) { 108 return fastEmitInst_r(ARM::BX_CALL, &ARM::tGPRRegClass, Op0, Op0IsKill); 109 } 110 return 0; 111} 112 113unsigned fastEmit_ARMISD_CALL_NOLINK_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 114 switch (VT.SimpleTy) { 115 case MVT::i32: return fastEmit_ARMISD_CALL_NOLINK_MVT_i32_r(RetVT, Op0, Op0IsKill); 116 default: return 0; 117 } 118} 119 120// FastEmit functions for ARMISD::CALL_PRED. 121 122unsigned fastEmit_ARMISD_CALL_PRED_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 123 if (RetVT.SimpleTy != MVT::isVoid) 124 return 0; 125 if ((Subtarget->hasV5TOps()) && (!Subtarget->isThumb())) { 126 return fastEmitInst_r(ARM::BLX_pred, &ARM::GPRRegClass, Op0, Op0IsKill); 127 } 128 return 0; 129} 130 131unsigned fastEmit_ARMISD_CALL_PRED_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 132 switch (VT.SimpleTy) { 133 case MVT::i32: return fastEmit_ARMISD_CALL_PRED_MVT_i32_r(RetVT, Op0, Op0IsKill); 134 default: return 0; 135 } 136} 137 138// FastEmit functions for ARMISD::CMPFPEw0. 139 140unsigned fastEmit_ARMISD_CMPFPEw0_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 141 if (RetVT.SimpleTy != MVT::isVoid) 142 return 0; 143 if ((Subtarget->hasFullFP16())) { 144 return fastEmitInst_r(ARM::VCMPEZH, &ARM::HPRRegClass, Op0, Op0IsKill); 145 } 146 return 0; 147} 148 149unsigned fastEmit_ARMISD_CMPFPEw0_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 150 if (RetVT.SimpleTy != MVT::isVoid) 151 return 0; 152 if ((Subtarget->hasVFP2Base())) { 153 return fastEmitInst_r(ARM::VCMPEZS, &ARM::SPRRegClass, Op0, Op0IsKill); 154 } 155 return 0; 156} 157 158unsigned fastEmit_ARMISD_CMPFPEw0_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 159 if (RetVT.SimpleTy != MVT::isVoid) 160 return 0; 161 if ((Subtarget->hasFP64()) && (Subtarget->hasVFP2Base())) { 162 return fastEmitInst_r(ARM::VCMPEZD, &ARM::DPRRegClass, Op0, Op0IsKill); 163 } 164 return 0; 165} 166 167unsigned fastEmit_ARMISD_CMPFPEw0_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 168 switch (VT.SimpleTy) { 169 case MVT::f16: return fastEmit_ARMISD_CMPFPEw0_MVT_f16_r(RetVT, Op0, Op0IsKill); 170 case MVT::f32: return fastEmit_ARMISD_CMPFPEw0_MVT_f32_r(RetVT, Op0, Op0IsKill); 171 case MVT::f64: return fastEmit_ARMISD_CMPFPEw0_MVT_f64_r(RetVT, Op0, Op0IsKill); 172 default: return 0; 173 } 174} 175 176// FastEmit functions for ARMISD::CMPFPw0. 177 178unsigned fastEmit_ARMISD_CMPFPw0_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 179 if (RetVT.SimpleTy != MVT::isVoid) 180 return 0; 181 if ((Subtarget->hasFullFP16())) { 182 return fastEmitInst_r(ARM::VCMPZH, &ARM::HPRRegClass, Op0, Op0IsKill); 183 } 184 return 0; 185} 186 187unsigned fastEmit_ARMISD_CMPFPw0_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 188 if (RetVT.SimpleTy != MVT::isVoid) 189 return 0; 190 if ((Subtarget->hasVFP2Base())) { 191 return fastEmitInst_r(ARM::VCMPZS, &ARM::SPRRegClass, Op0, Op0IsKill); 192 } 193 return 0; 194} 195 196unsigned fastEmit_ARMISD_CMPFPw0_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 197 if (RetVT.SimpleTy != MVT::isVoid) 198 return 0; 199 if ((Subtarget->hasFP64()) && (Subtarget->hasVFP2Base())) { 200 return fastEmitInst_r(ARM::VCMPZD, &ARM::DPRRegClass, Op0, Op0IsKill); 201 } 202 return 0; 203} 204 205unsigned fastEmit_ARMISD_CMPFPw0_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 206 switch (VT.SimpleTy) { 207 case MVT::f16: return fastEmit_ARMISD_CMPFPw0_MVT_f16_r(RetVT, Op0, Op0IsKill); 208 case MVT::f32: return fastEmit_ARMISD_CMPFPw0_MVT_f32_r(RetVT, Op0, Op0IsKill); 209 case MVT::f64: return fastEmit_ARMISD_CMPFPw0_MVT_f64_r(RetVT, Op0, Op0IsKill); 210 default: return 0; 211 } 212} 213 214// FastEmit functions for ARMISD::RRX. 215 216unsigned fastEmit_ARMISD_RRX_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 217 if (RetVT.SimpleTy != MVT::i32) 218 return 0; 219 if ((Subtarget->isThumb2())) { 220 return fastEmitInst_r(ARM::t2RRX, &ARM::rGPRRegClass, Op0, Op0IsKill); 221 } 222 if ((!Subtarget->isThumb())) { 223 return fastEmitInst_r(ARM::RRX, &ARM::GPRRegClass, Op0, Op0IsKill); 224 } 225 return 0; 226} 227 228unsigned fastEmit_ARMISD_RRX_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 229 switch (VT.SimpleTy) { 230 case MVT::i32: return fastEmit_ARMISD_RRX_MVT_i32_r(RetVT, Op0, Op0IsKill); 231 default: return 0; 232 } 233} 234 235// FastEmit functions for ARMISD::SRA_FLAG. 236 237unsigned fastEmit_ARMISD_SRA_FLAG_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 238 if (RetVT.SimpleTy != MVT::i32) 239 return 0; 240 if ((Subtarget->isThumb2())) { 241 return fastEmitInst_r(ARM::t2MOVsra_flag, &ARM::rGPRRegClass, Op0, Op0IsKill); 242 } 243 if ((!Subtarget->isThumb())) { 244 return fastEmitInst_r(ARM::MOVsra_flag, &ARM::GPRRegClass, Op0, Op0IsKill); 245 } 246 return 0; 247} 248 249unsigned fastEmit_ARMISD_SRA_FLAG_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 250 switch (VT.SimpleTy) { 251 case MVT::i32: return fastEmit_ARMISD_SRA_FLAG_MVT_i32_r(RetVT, Op0, Op0IsKill); 252 default: return 0; 253 } 254} 255 256// FastEmit functions for ARMISD::SRL_FLAG. 257 258unsigned fastEmit_ARMISD_SRL_FLAG_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 259 if (RetVT.SimpleTy != MVT::i32) 260 return 0; 261 if ((Subtarget->isThumb2())) { 262 return fastEmitInst_r(ARM::t2MOVsrl_flag, &ARM::rGPRRegClass, Op0, Op0IsKill); 263 } 264 if ((!Subtarget->isThumb())) { 265 return fastEmitInst_r(ARM::MOVsrl_flag, &ARM::GPRRegClass, Op0, Op0IsKill); 266 } 267 return 0; 268} 269 270unsigned fastEmit_ARMISD_SRL_FLAG_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 271 switch (VT.SimpleTy) { 272 case MVT::i32: return fastEmit_ARMISD_SRL_FLAG_MVT_i32_r(RetVT, Op0, Op0IsKill); 273 default: return 0; 274 } 275} 276 277// FastEmit functions for ARMISD::TC_RETURN. 278 279unsigned fastEmit_ARMISD_TC_RETURN_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 280 if (RetVT.SimpleTy != MVT::isVoid) 281 return 0; 282 return fastEmitInst_r(ARM::TCRETURNri, &ARM::tcGPRRegClass, Op0, Op0IsKill); 283} 284 285unsigned fastEmit_ARMISD_TC_RETURN_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 286 switch (VT.SimpleTy) { 287 case MVT::i32: return fastEmit_ARMISD_TC_RETURN_MVT_i32_r(RetVT, Op0, Op0IsKill); 288 default: return 0; 289 } 290} 291 292// FastEmit functions for ARMISD::VDUP. 293 294unsigned fastEmit_ARMISD_VDUP_MVT_i32_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) { 295 if ((Subtarget->hasNEON())) { 296 return fastEmitInst_r(ARM::VDUP8d, &ARM::DPRRegClass, Op0, Op0IsKill); 297 } 298 return 0; 299} 300 301unsigned fastEmit_ARMISD_VDUP_MVT_i32_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) { 302 if ((Subtarget->hasMVEIntegerOps())) { 303 return fastEmitInst_r(ARM::MVE_VDUP8, &ARM::MQPRRegClass, Op0, Op0IsKill); 304 } 305 if ((Subtarget->hasNEON())) { 306 return fastEmitInst_r(ARM::VDUP8q, &ARM::QPRRegClass, Op0, Op0IsKill); 307 } 308 return 0; 309} 310 311unsigned fastEmit_ARMISD_VDUP_MVT_i32_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) { 312 if ((Subtarget->hasNEON())) { 313 return fastEmitInst_r(ARM::VDUP16d, &ARM::DPRRegClass, Op0, Op0IsKill); 314 } 315 return 0; 316} 317 318unsigned fastEmit_ARMISD_VDUP_MVT_i32_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) { 319 if ((Subtarget->hasMVEIntegerOps())) { 320 return fastEmitInst_r(ARM::MVE_VDUP16, &ARM::MQPRRegClass, Op0, Op0IsKill); 321 } 322 if ((Subtarget->hasNEON())) { 323 return fastEmitInst_r(ARM::VDUP16q, &ARM::QPRRegClass, Op0, Op0IsKill); 324 } 325 return 0; 326} 327 328unsigned fastEmit_ARMISD_VDUP_MVT_i32_MVT_v2i32_r(unsigned Op0, bool Op0IsKill) { 329 if ((!Subtarget->hasSlowVDUP32()) && (Subtarget->hasNEON())) { 330 return fastEmitInst_r(ARM::VDUP32d, &ARM::DPRRegClass, Op0, Op0IsKill); 331 } 332 return 0; 333} 334 335unsigned fastEmit_ARMISD_VDUP_MVT_i32_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) { 336 if ((Subtarget->hasMVEIntegerOps())) { 337 return fastEmitInst_r(ARM::MVE_VDUP32, &ARM::MQPRRegClass, Op0, Op0IsKill); 338 } 339 if ((Subtarget->hasNEON())) { 340 return fastEmitInst_r(ARM::VDUP32q, &ARM::QPRRegClass, Op0, Op0IsKill); 341 } 342 return 0; 343} 344 345unsigned fastEmit_ARMISD_VDUP_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 346switch (RetVT.SimpleTy) { 347 case MVT::v8i8: return fastEmit_ARMISD_VDUP_MVT_i32_MVT_v8i8_r(Op0, Op0IsKill); 348 case MVT::v16i8: return fastEmit_ARMISD_VDUP_MVT_i32_MVT_v16i8_r(Op0, Op0IsKill); 349 case MVT::v4i16: return fastEmit_ARMISD_VDUP_MVT_i32_MVT_v4i16_r(Op0, Op0IsKill); 350 case MVT::v8i16: return fastEmit_ARMISD_VDUP_MVT_i32_MVT_v8i16_r(Op0, Op0IsKill); 351 case MVT::v2i32: return fastEmit_ARMISD_VDUP_MVT_i32_MVT_v2i32_r(Op0, Op0IsKill); 352 case MVT::v4i32: return fastEmit_ARMISD_VDUP_MVT_i32_MVT_v4i32_r(Op0, Op0IsKill); 353 default: return 0; 354} 355} 356 357unsigned fastEmit_ARMISD_VDUP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 358 switch (VT.SimpleTy) { 359 case MVT::i32: return fastEmit_ARMISD_VDUP_MVT_i32_r(RetVT, Op0, Op0IsKill); 360 default: return 0; 361 } 362} 363 364// FastEmit functions for ARMISD::VMOVSR. 365 366unsigned fastEmit_ARMISD_VMOVSR_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 367 if (RetVT.SimpleTy != MVT::f32) 368 return 0; 369 if ((Subtarget->hasVFP2Base()) && (Subtarget->preferVMOVSR() ||!Subtarget->useNEONForSinglePrecisionFP())) { 370 return fastEmitInst_r(ARM::VMOVSR, &ARM::SPRRegClass, Op0, Op0IsKill); 371 } 372 return 0; 373} 374 375unsigned fastEmit_ARMISD_VMOVSR_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 376 switch (VT.SimpleTy) { 377 case MVT::i32: return fastEmit_ARMISD_VMOVSR_MVT_i32_r(RetVT, Op0, Op0IsKill); 378 default: return 0; 379 } 380} 381 382// FastEmit functions for ARMISD::VMOVhr. 383 384unsigned fastEmit_ARMISD_VMOVhr_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 385 if (RetVT.SimpleTy != MVT::f16) 386 return 0; 387 if ((Subtarget->hasFPRegs16())) { 388 return fastEmitInst_r(ARM::VMOVHR, &ARM::HPRRegClass, Op0, Op0IsKill); 389 } 390 return 0; 391} 392 393unsigned fastEmit_ARMISD_VMOVhr_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 394 switch (VT.SimpleTy) { 395 case MVT::i32: return fastEmit_ARMISD_VMOVhr_MVT_i32_r(RetVT, Op0, Op0IsKill); 396 default: return 0; 397 } 398} 399 400// FastEmit functions for ARMISD::VMOVrh. 401 402unsigned fastEmit_ARMISD_VMOVrh_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 403 if (RetVT.SimpleTy != MVT::i32) 404 return 0; 405 if ((Subtarget->hasFPRegs16())) { 406 return fastEmitInst_r(ARM::VMOVRH, &ARM::rGPRRegClass, Op0, Op0IsKill); 407 } 408 return 0; 409} 410 411unsigned fastEmit_ARMISD_VMOVrh_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 412 switch (VT.SimpleTy) { 413 case MVT::f16: return fastEmit_ARMISD_VMOVrh_MVT_f16_r(RetVT, Op0, Op0IsKill); 414 default: return 0; 415 } 416} 417 418// FastEmit functions for ARMISD::VREV16. 419 420unsigned fastEmit_ARMISD_VREV16_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 421 if (RetVT.SimpleTy != MVT::v8i8) 422 return 0; 423 if ((Subtarget->hasNEON())) { 424 return fastEmitInst_r(ARM::VREV16d8, &ARM::DPRRegClass, Op0, Op0IsKill); 425 } 426 return 0; 427} 428 429unsigned fastEmit_ARMISD_VREV16_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 430 if (RetVT.SimpleTy != MVT::v16i8) 431 return 0; 432 if ((Subtarget->hasMVEIntegerOps())) { 433 return fastEmitInst_r(ARM::MVE_VREV16_8, &ARM::MQPRRegClass, Op0, Op0IsKill); 434 } 435 if ((Subtarget->hasNEON())) { 436 return fastEmitInst_r(ARM::VREV16q8, &ARM::QPRRegClass, Op0, Op0IsKill); 437 } 438 return 0; 439} 440 441unsigned fastEmit_ARMISD_VREV16_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 442 switch (VT.SimpleTy) { 443 case MVT::v8i8: return fastEmit_ARMISD_VREV16_MVT_v8i8_r(RetVT, Op0, Op0IsKill); 444 case MVT::v16i8: return fastEmit_ARMISD_VREV16_MVT_v16i8_r(RetVT, Op0, Op0IsKill); 445 default: return 0; 446 } 447} 448 449// FastEmit functions for ARMISD::VREV32. 450 451unsigned fastEmit_ARMISD_VREV32_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 452 if (RetVT.SimpleTy != MVT::v8i8) 453 return 0; 454 if ((Subtarget->hasNEON())) { 455 return fastEmitInst_r(ARM::VREV32d8, &ARM::DPRRegClass, Op0, Op0IsKill); 456 } 457 return 0; 458} 459 460unsigned fastEmit_ARMISD_VREV32_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 461 if (RetVT.SimpleTy != MVT::v16i8) 462 return 0; 463 if ((Subtarget->hasMVEIntegerOps())) { 464 return fastEmitInst_r(ARM::MVE_VREV32_8, &ARM::MQPRRegClass, Op0, Op0IsKill); 465 } 466 if ((Subtarget->hasNEON())) { 467 return fastEmitInst_r(ARM::VREV32q8, &ARM::QPRRegClass, Op0, Op0IsKill); 468 } 469 return 0; 470} 471 472unsigned fastEmit_ARMISD_VREV32_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 473 if (RetVT.SimpleTy != MVT::v4i16) 474 return 0; 475 if ((Subtarget->hasNEON())) { 476 return fastEmitInst_r(ARM::VREV32d16, &ARM::DPRRegClass, Op0, Op0IsKill); 477 } 478 return 0; 479} 480 481unsigned fastEmit_ARMISD_VREV32_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 482 if (RetVT.SimpleTy != MVT::v8i16) 483 return 0; 484 if ((Subtarget->hasMVEIntegerOps())) { 485 return fastEmitInst_r(ARM::MVE_VREV32_16, &ARM::MQPRRegClass, Op0, Op0IsKill); 486 } 487 if ((Subtarget->hasNEON())) { 488 return fastEmitInst_r(ARM::VREV32q16, &ARM::QPRRegClass, Op0, Op0IsKill); 489 } 490 return 0; 491} 492 493unsigned fastEmit_ARMISD_VREV32_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 494 if (RetVT.SimpleTy != MVT::v4f16) 495 return 0; 496 if ((Subtarget->hasNEON())) { 497 return fastEmitInst_r(ARM::VREV32d16, &ARM::DPRRegClass, Op0, Op0IsKill); 498 } 499 return 0; 500} 501 502unsigned fastEmit_ARMISD_VREV32_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 503 if (RetVT.SimpleTy != MVT::v8f16) 504 return 0; 505 if ((Subtarget->hasMVEIntegerOps())) { 506 return fastEmitInst_r(ARM::MVE_VREV32_16, &ARM::MQPRRegClass, Op0, Op0IsKill); 507 } 508 if ((Subtarget->hasNEON())) { 509 return fastEmitInst_r(ARM::VREV32q16, &ARM::QPRRegClass, Op0, Op0IsKill); 510 } 511 return 0; 512} 513 514unsigned fastEmit_ARMISD_VREV32_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 515 switch (VT.SimpleTy) { 516 case MVT::v8i8: return fastEmit_ARMISD_VREV32_MVT_v8i8_r(RetVT, Op0, Op0IsKill); 517 case MVT::v16i8: return fastEmit_ARMISD_VREV32_MVT_v16i8_r(RetVT, Op0, Op0IsKill); 518 case MVT::v4i16: return fastEmit_ARMISD_VREV32_MVT_v4i16_r(RetVT, Op0, Op0IsKill); 519 case MVT::v8i16: return fastEmit_ARMISD_VREV32_MVT_v8i16_r(RetVT, Op0, Op0IsKill); 520 case MVT::v4f16: return fastEmit_ARMISD_VREV32_MVT_v4f16_r(RetVT, Op0, Op0IsKill); 521 case MVT::v8f16: return fastEmit_ARMISD_VREV32_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 522 default: return 0; 523 } 524} 525 526// FastEmit functions for ARMISD::VREV64. 527 528unsigned fastEmit_ARMISD_VREV64_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 529 if (RetVT.SimpleTy != MVT::v8i8) 530 return 0; 531 if ((Subtarget->hasNEON())) { 532 return fastEmitInst_r(ARM::VREV64d8, &ARM::DPRRegClass, Op0, Op0IsKill); 533 } 534 return 0; 535} 536 537unsigned fastEmit_ARMISD_VREV64_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 538 if (RetVT.SimpleTy != MVT::v16i8) 539 return 0; 540 if ((Subtarget->hasMVEIntegerOps())) { 541 return fastEmitInst_r(ARM::MVE_VREV64_8, &ARM::MQPRRegClass, Op0, Op0IsKill); 542 } 543 if ((Subtarget->hasNEON())) { 544 return fastEmitInst_r(ARM::VREV64q8, &ARM::QPRRegClass, Op0, Op0IsKill); 545 } 546 return 0; 547} 548 549unsigned fastEmit_ARMISD_VREV64_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 550 if (RetVT.SimpleTy != MVT::v4i16) 551 return 0; 552 if ((Subtarget->hasNEON())) { 553 return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill); 554 } 555 return 0; 556} 557 558unsigned fastEmit_ARMISD_VREV64_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 559 if (RetVT.SimpleTy != MVT::v8i16) 560 return 0; 561 if ((Subtarget->hasMVEIntegerOps())) { 562 return fastEmitInst_r(ARM::MVE_VREV64_16, &ARM::MQPRRegClass, Op0, Op0IsKill); 563 } 564 if ((Subtarget->hasNEON())) { 565 return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill); 566 } 567 return 0; 568} 569 570unsigned fastEmit_ARMISD_VREV64_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 571 if (RetVT.SimpleTy != MVT::v2i32) 572 return 0; 573 if ((Subtarget->hasNEON())) { 574 return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill); 575 } 576 return 0; 577} 578 579unsigned fastEmit_ARMISD_VREV64_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 580 if (RetVT.SimpleTy != MVT::v4i32) 581 return 0; 582 if ((Subtarget->hasMVEIntegerOps())) { 583 return fastEmitInst_r(ARM::MVE_VREV64_32, &ARM::MQPRRegClass, Op0, Op0IsKill); 584 } 585 if ((Subtarget->hasNEON())) { 586 return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill); 587 } 588 return 0; 589} 590 591unsigned fastEmit_ARMISD_VREV64_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 592 if (RetVT.SimpleTy != MVT::v4f16) 593 return 0; 594 if ((Subtarget->hasNEON())) { 595 return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill); 596 } 597 return 0; 598} 599 600unsigned fastEmit_ARMISD_VREV64_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 601 if (RetVT.SimpleTy != MVT::v8f16) 602 return 0; 603 if ((Subtarget->hasMVEIntegerOps())) { 604 return fastEmitInst_r(ARM::MVE_VREV64_16, &ARM::MQPRRegClass, Op0, Op0IsKill); 605 } 606 if ((Subtarget->hasNEON())) { 607 return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill); 608 } 609 return 0; 610} 611 612unsigned fastEmit_ARMISD_VREV64_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 613 if (RetVT.SimpleTy != MVT::v2f32) 614 return 0; 615 if ((Subtarget->hasNEON())) { 616 return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill); 617 } 618 return 0; 619} 620 621unsigned fastEmit_ARMISD_VREV64_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 622 if (RetVT.SimpleTy != MVT::v4f32) 623 return 0; 624 if ((Subtarget->hasMVEIntegerOps())) { 625 return fastEmitInst_r(ARM::MVE_VREV64_32, &ARM::MQPRRegClass, Op0, Op0IsKill); 626 } 627 if ((Subtarget->hasNEON())) { 628 return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill); 629 } 630 return 0; 631} 632 633unsigned fastEmit_ARMISD_VREV64_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 634 switch (VT.SimpleTy) { 635 case MVT::v8i8: return fastEmit_ARMISD_VREV64_MVT_v8i8_r(RetVT, Op0, Op0IsKill); 636 case MVT::v16i8: return fastEmit_ARMISD_VREV64_MVT_v16i8_r(RetVT, Op0, Op0IsKill); 637 case MVT::v4i16: return fastEmit_ARMISD_VREV64_MVT_v4i16_r(RetVT, Op0, Op0IsKill); 638 case MVT::v8i16: return fastEmit_ARMISD_VREV64_MVT_v8i16_r(RetVT, Op0, Op0IsKill); 639 case MVT::v2i32: return fastEmit_ARMISD_VREV64_MVT_v2i32_r(RetVT, Op0, Op0IsKill); 640 case MVT::v4i32: return fastEmit_ARMISD_VREV64_MVT_v4i32_r(RetVT, Op0, Op0IsKill); 641 case MVT::v4f16: return fastEmit_ARMISD_VREV64_MVT_v4f16_r(RetVT, Op0, Op0IsKill); 642 case MVT::v8f16: return fastEmit_ARMISD_VREV64_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 643 case MVT::v2f32: return fastEmit_ARMISD_VREV64_MVT_v2f32_r(RetVT, Op0, Op0IsKill); 644 case MVT::v4f32: return fastEmit_ARMISD_VREV64_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 645 default: return 0; 646 } 647} 648 649// FastEmit functions for ARMISD::WIN__DBZCHK. 650 651unsigned fastEmit_ARMISD_WIN__DBZCHK_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 652 if (RetVT.SimpleTy != MVT::isVoid) 653 return 0; 654 return fastEmitInst_r(ARM::WIN__DBZCHK, &ARM::tGPRRegClass, Op0, Op0IsKill); 655} 656 657unsigned fastEmit_ARMISD_WIN__DBZCHK_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 658 switch (VT.SimpleTy) { 659 case MVT::i32: return fastEmit_ARMISD_WIN__DBZCHK_MVT_i32_r(RetVT, Op0, Op0IsKill); 660 default: return 0; 661 } 662} 663 664// FastEmit functions for ISD::ABS. 665 666unsigned fastEmit_ISD_ABS_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 667 if (RetVT.SimpleTy != MVT::v8i8) 668 return 0; 669 if ((Subtarget->hasNEON())) { 670 return fastEmitInst_r(ARM::VABSv8i8, &ARM::DPRRegClass, Op0, Op0IsKill); 671 } 672 return 0; 673} 674 675unsigned fastEmit_ISD_ABS_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 676 if (RetVT.SimpleTy != MVT::v16i8) 677 return 0; 678 if ((Subtarget->hasMVEIntegerOps())) { 679 return fastEmitInst_r(ARM::MVE_VABSs8, &ARM::MQPRRegClass, Op0, Op0IsKill); 680 } 681 if ((Subtarget->hasNEON())) { 682 return fastEmitInst_r(ARM::VABSv16i8, &ARM::QPRRegClass, Op0, Op0IsKill); 683 } 684 return 0; 685} 686 687unsigned fastEmit_ISD_ABS_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 688 if (RetVT.SimpleTy != MVT::v4i16) 689 return 0; 690 if ((Subtarget->hasNEON())) { 691 return fastEmitInst_r(ARM::VABSv4i16, &ARM::DPRRegClass, Op0, Op0IsKill); 692 } 693 return 0; 694} 695 696unsigned fastEmit_ISD_ABS_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 697 if (RetVT.SimpleTy != MVT::v8i16) 698 return 0; 699 if ((Subtarget->hasMVEIntegerOps())) { 700 return fastEmitInst_r(ARM::MVE_VABSs16, &ARM::MQPRRegClass, Op0, Op0IsKill); 701 } 702 if ((Subtarget->hasNEON())) { 703 return fastEmitInst_r(ARM::VABSv8i16, &ARM::QPRRegClass, Op0, Op0IsKill); 704 } 705 return 0; 706} 707 708unsigned fastEmit_ISD_ABS_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 709 if (RetVT.SimpleTy != MVT::v2i32) 710 return 0; 711 if ((Subtarget->hasNEON())) { 712 return fastEmitInst_r(ARM::VABSv2i32, &ARM::DPRRegClass, Op0, Op0IsKill); 713 } 714 return 0; 715} 716 717unsigned fastEmit_ISD_ABS_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 718 if (RetVT.SimpleTy != MVT::v4i32) 719 return 0; 720 if ((Subtarget->hasMVEIntegerOps())) { 721 return fastEmitInst_r(ARM::MVE_VABSs32, &ARM::MQPRRegClass, Op0, Op0IsKill); 722 } 723 if ((Subtarget->hasNEON())) { 724 return fastEmitInst_r(ARM::VABSv4i32, &ARM::QPRRegClass, Op0, Op0IsKill); 725 } 726 return 0; 727} 728 729unsigned fastEmit_ISD_ABS_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 730 switch (VT.SimpleTy) { 731 case MVT::v8i8: return fastEmit_ISD_ABS_MVT_v8i8_r(RetVT, Op0, Op0IsKill); 732 case MVT::v16i8: return fastEmit_ISD_ABS_MVT_v16i8_r(RetVT, Op0, Op0IsKill); 733 case MVT::v4i16: return fastEmit_ISD_ABS_MVT_v4i16_r(RetVT, Op0, Op0IsKill); 734 case MVT::v8i16: return fastEmit_ISD_ABS_MVT_v8i16_r(RetVT, Op0, Op0IsKill); 735 case MVT::v2i32: return fastEmit_ISD_ABS_MVT_v2i32_r(RetVT, Op0, Op0IsKill); 736 case MVT::v4i32: return fastEmit_ISD_ABS_MVT_v4i32_r(RetVT, Op0, Op0IsKill); 737 default: return 0; 738 } 739} 740 741// FastEmit functions for ISD::ANY_EXTEND. 742 743unsigned fastEmit_ISD_ANY_EXTEND_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 744 if (RetVT.SimpleTy != MVT::v8i16) 745 return 0; 746 if ((Subtarget->hasNEON())) { 747 return fastEmitInst_r(ARM::VMOVLuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill); 748 } 749 return 0; 750} 751 752unsigned fastEmit_ISD_ANY_EXTEND_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 753 if (RetVT.SimpleTy != MVT::v4i32) 754 return 0; 755 if ((Subtarget->hasNEON())) { 756 return fastEmitInst_r(ARM::VMOVLuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill); 757 } 758 return 0; 759} 760 761unsigned fastEmit_ISD_ANY_EXTEND_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 762 if (RetVT.SimpleTy != MVT::v2i64) 763 return 0; 764 if ((Subtarget->hasNEON())) { 765 return fastEmitInst_r(ARM::VMOVLuv2i64, &ARM::QPRRegClass, Op0, Op0IsKill); 766 } 767 return 0; 768} 769 770unsigned fastEmit_ISD_ANY_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 771 switch (VT.SimpleTy) { 772 case MVT::v8i8: return fastEmit_ISD_ANY_EXTEND_MVT_v8i8_r(RetVT, Op0, Op0IsKill); 773 case MVT::v4i16: return fastEmit_ISD_ANY_EXTEND_MVT_v4i16_r(RetVT, Op0, Op0IsKill); 774 case MVT::v2i32: return fastEmit_ISD_ANY_EXTEND_MVT_v2i32_r(RetVT, Op0, Op0IsKill); 775 default: return 0; 776 } 777} 778 779// FastEmit functions for ISD::BITCAST. 780 781unsigned fastEmit_ISD_BITCAST_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 782 if (RetVT.SimpleTy != MVT::f32) 783 return 0; 784 if ((Subtarget->hasFPRegs()) && (Subtarget->preferVMOVSR() ||!Subtarget->useNEONForSinglePrecisionFP())) { 785 return fastEmitInst_r(ARM::VMOVSR, &ARM::SPRRegClass, Op0, Op0IsKill); 786 } 787 return 0; 788} 789 790unsigned fastEmit_ISD_BITCAST_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 791 if (RetVT.SimpleTy != MVT::i32) 792 return 0; 793 if ((Subtarget->hasFPRegs())) { 794 return fastEmitInst_r(ARM::VMOVRS, &ARM::GPRRegClass, Op0, Op0IsKill); 795 } 796 return 0; 797} 798 799unsigned fastEmit_ISD_BITCAST_MVT_f64_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) { 800 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 801 return fastEmitInst_r(ARM::VREV64d8, &ARM::DPRRegClass, Op0, Op0IsKill); 802 } 803 return 0; 804} 805 806unsigned fastEmit_ISD_BITCAST_MVT_f64_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) { 807 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 808 return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill); 809 } 810 return 0; 811} 812 813unsigned fastEmit_ISD_BITCAST_MVT_f64_MVT_v2i32_r(unsigned Op0, bool Op0IsKill) { 814 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 815 return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill); 816 } 817 return 0; 818} 819 820unsigned fastEmit_ISD_BITCAST_MVT_f64_MVT_v4f16_r(unsigned Op0, bool Op0IsKill) { 821 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 822 return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill); 823 } 824 return 0; 825} 826 827unsigned fastEmit_ISD_BITCAST_MVT_f64_MVT_v2f32_r(unsigned Op0, bool Op0IsKill) { 828 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 829 return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill); 830 } 831 return 0; 832} 833 834unsigned fastEmit_ISD_BITCAST_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 835switch (RetVT.SimpleTy) { 836 case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_f64_MVT_v8i8_r(Op0, Op0IsKill); 837 case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_f64_MVT_v4i16_r(Op0, Op0IsKill); 838 case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_f64_MVT_v2i32_r(Op0, Op0IsKill); 839 case MVT::v4f16: return fastEmit_ISD_BITCAST_MVT_f64_MVT_v4f16_r(Op0, Op0IsKill); 840 case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_f64_MVT_v2f32_r(Op0, Op0IsKill); 841 default: return 0; 842} 843} 844 845unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_f64_r(unsigned Op0, bool Op0IsKill) { 846 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 847 return fastEmitInst_r(ARM::VREV64d8, &ARM::DPRRegClass, Op0, Op0IsKill); 848 } 849 return 0; 850} 851 852unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) { 853 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 854 return fastEmitInst_r(ARM::VREV16d8, &ARM::DPRRegClass, Op0, Op0IsKill); 855 } 856 return 0; 857} 858 859unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v2i32_r(unsigned Op0, bool Op0IsKill) { 860 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 861 return fastEmitInst_r(ARM::VREV32d8, &ARM::DPRRegClass, Op0, Op0IsKill); 862 } 863 return 0; 864} 865 866unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v1i64_r(unsigned Op0, bool Op0IsKill) { 867 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 868 return fastEmitInst_r(ARM::VREV64d8, &ARM::DPRRegClass, Op0, Op0IsKill); 869 } 870 return 0; 871} 872 873unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v4f16_r(unsigned Op0, bool Op0IsKill) { 874 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 875 return fastEmitInst_r(ARM::VREV16d8, &ARM::DPRRegClass, Op0, Op0IsKill); 876 } 877 return 0; 878} 879 880unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v2f32_r(unsigned Op0, bool Op0IsKill) { 881 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 882 return fastEmitInst_r(ARM::VREV32d8, &ARM::DPRRegClass, Op0, Op0IsKill); 883 } 884 return 0; 885} 886 887unsigned fastEmit_ISD_BITCAST_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 888switch (RetVT.SimpleTy) { 889 case MVT::f64: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_f64_r(Op0, Op0IsKill); 890 case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v4i16_r(Op0, Op0IsKill); 891 case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v2i32_r(Op0, Op0IsKill); 892 case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v1i64_r(Op0, Op0IsKill); 893 case MVT::v4f16: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v4f16_r(Op0, Op0IsKill); 894 case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v2f32_r(Op0, Op0IsKill); 895 default: return 0; 896} 897} 898 899unsigned fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) { 900 if ((Subtarget->hasMVEIntegerOps()) && (MF->getDataLayout().isBigEndian())) { 901 return fastEmitInst_r(ARM::MVE_VREV16_8, &ARM::MQPRRegClass, Op0, Op0IsKill); 902 } 903 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 904 return fastEmitInst_r(ARM::VREV16q8, &ARM::QPRRegClass, Op0, Op0IsKill); 905 } 906 return 0; 907} 908 909unsigned fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) { 910 if ((Subtarget->hasMVEIntegerOps()) && (MF->getDataLayout().isBigEndian())) { 911 return fastEmitInst_r(ARM::MVE_VREV32_8, &ARM::MQPRRegClass, Op0, Op0IsKill); 912 } 913 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 914 return fastEmitInst_r(ARM::VREV32q8, &ARM::QPRRegClass, Op0, Op0IsKill); 915 } 916 return 0; 917} 918 919unsigned fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) { 920 if ((Subtarget->hasMVEIntegerOps()) && (MF->getDataLayout().isBigEndian())) { 921 return fastEmitInst_r(ARM::MVE_VREV64_8, &ARM::MQPRRegClass, Op0, Op0IsKill); 922 } 923 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 924 return fastEmitInst_r(ARM::VREV64q8, &ARM::QPRRegClass, Op0, Op0IsKill); 925 } 926 return 0; 927} 928 929unsigned fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v8f16_r(unsigned Op0, bool Op0IsKill) { 930 if ((Subtarget->hasMVEIntegerOps()) && (MF->getDataLayout().isBigEndian())) { 931 return fastEmitInst_r(ARM::MVE_VREV16_8, &ARM::MQPRRegClass, Op0, Op0IsKill); 932 } 933 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 934 return fastEmitInst_r(ARM::VREV16q8, &ARM::QPRRegClass, Op0, Op0IsKill); 935 } 936 return 0; 937} 938 939unsigned fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v4f32_r(unsigned Op0, bool Op0IsKill) { 940 if ((Subtarget->hasMVEIntegerOps()) && (MF->getDataLayout().isBigEndian())) { 941 return fastEmitInst_r(ARM::MVE_VREV32_8, &ARM::MQPRRegClass, Op0, Op0IsKill); 942 } 943 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 944 return fastEmitInst_r(ARM::VREV32q8, &ARM::QPRRegClass, Op0, Op0IsKill); 945 } 946 return 0; 947} 948 949unsigned fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v2f64_r(unsigned Op0, bool Op0IsKill) { 950 if ((Subtarget->hasMVEIntegerOps()) && (MF->getDataLayout().isBigEndian())) { 951 return fastEmitInst_r(ARM::MVE_VREV64_8, &ARM::MQPRRegClass, Op0, Op0IsKill); 952 } 953 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 954 return fastEmitInst_r(ARM::VREV64q8, &ARM::QPRRegClass, Op0, Op0IsKill); 955 } 956 return 0; 957} 958 959unsigned fastEmit_ISD_BITCAST_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 960switch (RetVT.SimpleTy) { 961 case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v8i16_r(Op0, Op0IsKill); 962 case MVT::v4i32: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v4i32_r(Op0, Op0IsKill); 963 case MVT::v2i64: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v2i64_r(Op0, Op0IsKill); 964 case MVT::v8f16: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v8f16_r(Op0, Op0IsKill); 965 case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v4f32_r(Op0, Op0IsKill); 966 case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v2f64_r(Op0, Op0IsKill); 967 default: return 0; 968} 969} 970 971unsigned fastEmit_ISD_BITCAST_MVT_v4i16_MVT_f64_r(unsigned Op0, bool Op0IsKill) { 972 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 973 return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill); 974 } 975 return 0; 976} 977 978unsigned fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) { 979 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 980 return fastEmitInst_r(ARM::VREV16d8, &ARM::DPRRegClass, Op0, Op0IsKill); 981 } 982 return 0; 983} 984 985unsigned fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v2i32_r(unsigned Op0, bool Op0IsKill) { 986 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 987 return fastEmitInst_r(ARM::VREV32d16, &ARM::DPRRegClass, Op0, Op0IsKill); 988 } 989 return 0; 990} 991 992unsigned fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v1i64_r(unsigned Op0, bool Op0IsKill) { 993 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 994 return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill); 995 } 996 return 0; 997} 998 999unsigned fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v2f32_r(unsigned Op0, bool Op0IsKill) { 1000 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 1001 return fastEmitInst_r(ARM::VREV32d16, &ARM::DPRRegClass, Op0, Op0IsKill); 1002 } 1003 return 0; 1004} 1005 1006unsigned fastEmit_ISD_BITCAST_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1007switch (RetVT.SimpleTy) { 1008 case MVT::f64: return fastEmit_ISD_BITCAST_MVT_v4i16_MVT_f64_r(Op0, Op0IsKill); 1009 case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v8i8_r(Op0, Op0IsKill); 1010 case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v2i32_r(Op0, Op0IsKill); 1011 case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v1i64_r(Op0, Op0IsKill); 1012 case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v2f32_r(Op0, Op0IsKill); 1013 default: return 0; 1014} 1015} 1016 1017unsigned fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) { 1018 if ((Subtarget->hasMVEIntegerOps()) && (MF->getDataLayout().isBigEndian())) { 1019 return fastEmitInst_r(ARM::MVE_VREV16_8, &ARM::MQPRRegClass, Op0, Op0IsKill); 1020 } 1021 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 1022 return fastEmitInst_r(ARM::VREV16q8, &ARM::QPRRegClass, Op0, Op0IsKill); 1023 } 1024 return 0; 1025} 1026 1027unsigned fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) { 1028 if ((Subtarget->hasMVEIntegerOps()) && (MF->getDataLayout().isBigEndian())) { 1029 return fastEmitInst_r(ARM::MVE_VREV32_16, &ARM::MQPRRegClass, Op0, Op0IsKill); 1030 } 1031 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 1032 return fastEmitInst_r(ARM::VREV32q16, &ARM::QPRRegClass, Op0, Op0IsKill); 1033 } 1034 return 0; 1035} 1036 1037unsigned fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) { 1038 if ((Subtarget->hasMVEIntegerOps()) && (MF->getDataLayout().isBigEndian())) { 1039 return fastEmitInst_r(ARM::MVE_VREV64_16, &ARM::MQPRRegClass, Op0, Op0IsKill); 1040 } 1041 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 1042 return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill); 1043 } 1044 return 0; 1045} 1046 1047unsigned fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v4f32_r(unsigned Op0, bool Op0IsKill) { 1048 if ((Subtarget->hasMVEIntegerOps()) && (MF->getDataLayout().isBigEndian())) { 1049 return fastEmitInst_r(ARM::MVE_VREV32_16, &ARM::MQPRRegClass, Op0, Op0IsKill); 1050 } 1051 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 1052 return fastEmitInst_r(ARM::VREV32q16, &ARM::QPRRegClass, Op0, Op0IsKill); 1053 } 1054 return 0; 1055} 1056 1057unsigned fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v2f64_r(unsigned Op0, bool Op0IsKill) { 1058 if ((Subtarget->hasMVEIntegerOps()) && (MF->getDataLayout().isBigEndian())) { 1059 return fastEmitInst_r(ARM::MVE_VREV64_16, &ARM::MQPRRegClass, Op0, Op0IsKill); 1060 } 1061 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 1062 return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill); 1063 } 1064 return 0; 1065} 1066 1067unsigned fastEmit_ISD_BITCAST_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1068switch (RetVT.SimpleTy) { 1069 case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v16i8_r(Op0, Op0IsKill); 1070 case MVT::v4i32: return fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v4i32_r(Op0, Op0IsKill); 1071 case MVT::v2i64: return fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v2i64_r(Op0, Op0IsKill); 1072 case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v4f32_r(Op0, Op0IsKill); 1073 case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v2f64_r(Op0, Op0IsKill); 1074 default: return 0; 1075} 1076} 1077 1078unsigned fastEmit_ISD_BITCAST_MVT_v2i32_MVT_f64_r(unsigned Op0, bool Op0IsKill) { 1079 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 1080 return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill); 1081 } 1082 return 0; 1083} 1084 1085unsigned fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) { 1086 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 1087 return fastEmitInst_r(ARM::VREV32d8, &ARM::DPRRegClass, Op0, Op0IsKill); 1088 } 1089 return 0; 1090} 1091 1092unsigned fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) { 1093 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 1094 return fastEmitInst_r(ARM::VREV32d16, &ARM::DPRRegClass, Op0, Op0IsKill); 1095 } 1096 return 0; 1097} 1098 1099unsigned fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v1i64_r(unsigned Op0, bool Op0IsKill) { 1100 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 1101 return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill); 1102 } 1103 return 0; 1104} 1105 1106unsigned fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v4f16_r(unsigned Op0, bool Op0IsKill) { 1107 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 1108 return fastEmitInst_r(ARM::VREV32d16, &ARM::DPRRegClass, Op0, Op0IsKill); 1109 } 1110 return 0; 1111} 1112 1113unsigned fastEmit_ISD_BITCAST_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1114switch (RetVT.SimpleTy) { 1115 case MVT::f64: return fastEmit_ISD_BITCAST_MVT_v2i32_MVT_f64_r(Op0, Op0IsKill); 1116 case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v8i8_r(Op0, Op0IsKill); 1117 case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v4i16_r(Op0, Op0IsKill); 1118 case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v1i64_r(Op0, Op0IsKill); 1119 case MVT::v4f16: return fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v4f16_r(Op0, Op0IsKill); 1120 default: return 0; 1121} 1122} 1123 1124unsigned fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) { 1125 if ((Subtarget->hasMVEIntegerOps()) && (MF->getDataLayout().isBigEndian())) { 1126 return fastEmitInst_r(ARM::MVE_VREV32_8, &ARM::MQPRRegClass, Op0, Op0IsKill); 1127 } 1128 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 1129 return fastEmitInst_r(ARM::VREV32q8, &ARM::QPRRegClass, Op0, Op0IsKill); 1130 } 1131 return 0; 1132} 1133 1134unsigned fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) { 1135 if ((Subtarget->hasMVEIntegerOps()) && (MF->getDataLayout().isBigEndian())) { 1136 return fastEmitInst_r(ARM::MVE_VREV32_16, &ARM::MQPRRegClass, Op0, Op0IsKill); 1137 } 1138 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 1139 return fastEmitInst_r(ARM::VREV32q16, &ARM::QPRRegClass, Op0, Op0IsKill); 1140 } 1141 return 0; 1142} 1143 1144unsigned fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) { 1145 if ((Subtarget->hasMVEIntegerOps()) && (MF->getDataLayout().isBigEndian())) { 1146 return fastEmitInst_r(ARM::MVE_VREV64_32, &ARM::MQPRRegClass, Op0, Op0IsKill); 1147 } 1148 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 1149 return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill); 1150 } 1151 return 0; 1152} 1153 1154unsigned fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v8f16_r(unsigned Op0, bool Op0IsKill) { 1155 if ((Subtarget->hasMVEIntegerOps()) && (MF->getDataLayout().isBigEndian())) { 1156 return fastEmitInst_r(ARM::MVE_VREV32_16, &ARM::MQPRRegClass, Op0, Op0IsKill); 1157 } 1158 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 1159 return fastEmitInst_r(ARM::VREV32q16, &ARM::QPRRegClass, Op0, Op0IsKill); 1160 } 1161 return 0; 1162} 1163 1164unsigned fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v2f64_r(unsigned Op0, bool Op0IsKill) { 1165 if ((Subtarget->hasMVEIntegerOps()) && (MF->getDataLayout().isBigEndian())) { 1166 return fastEmitInst_r(ARM::MVE_VREV64_32, &ARM::MQPRRegClass, Op0, Op0IsKill); 1167 } 1168 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 1169 return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill); 1170 } 1171 return 0; 1172} 1173 1174unsigned fastEmit_ISD_BITCAST_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1175switch (RetVT.SimpleTy) { 1176 case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v16i8_r(Op0, Op0IsKill); 1177 case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v8i16_r(Op0, Op0IsKill); 1178 case MVT::v2i64: return fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v2i64_r(Op0, Op0IsKill); 1179 case MVT::v8f16: return fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v8f16_r(Op0, Op0IsKill); 1180 case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v2f64_r(Op0, Op0IsKill); 1181 default: return 0; 1182} 1183} 1184 1185unsigned fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) { 1186 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 1187 return fastEmitInst_r(ARM::VREV64d8, &ARM::DPRRegClass, Op0, Op0IsKill); 1188 } 1189 return 0; 1190} 1191 1192unsigned fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) { 1193 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 1194 return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill); 1195 } 1196 return 0; 1197} 1198 1199unsigned fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v2i32_r(unsigned Op0, bool Op0IsKill) { 1200 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 1201 return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill); 1202 } 1203 return 0; 1204} 1205 1206unsigned fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v4f16_r(unsigned Op0, bool Op0IsKill) { 1207 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 1208 return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill); 1209 } 1210 return 0; 1211} 1212 1213unsigned fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v2f32_r(unsigned Op0, bool Op0IsKill) { 1214 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 1215 return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill); 1216 } 1217 return 0; 1218} 1219 1220unsigned fastEmit_ISD_BITCAST_MVT_v1i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1221switch (RetVT.SimpleTy) { 1222 case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v8i8_r(Op0, Op0IsKill); 1223 case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v4i16_r(Op0, Op0IsKill); 1224 case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v2i32_r(Op0, Op0IsKill); 1225 case MVT::v4f16: return fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v4f16_r(Op0, Op0IsKill); 1226 case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v2f32_r(Op0, Op0IsKill); 1227 default: return 0; 1228} 1229} 1230 1231unsigned fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) { 1232 if ((Subtarget->hasMVEIntegerOps()) && (MF->getDataLayout().isBigEndian())) { 1233 return fastEmitInst_r(ARM::MVE_VREV64_8, &ARM::MQPRRegClass, Op0, Op0IsKill); 1234 } 1235 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 1236 return fastEmitInst_r(ARM::VREV64q8, &ARM::QPRRegClass, Op0, Op0IsKill); 1237 } 1238 return 0; 1239} 1240 1241unsigned fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) { 1242 if ((Subtarget->hasMVEIntegerOps()) && (MF->getDataLayout().isBigEndian())) { 1243 return fastEmitInst_r(ARM::MVE_VREV64_16, &ARM::MQPRRegClass, Op0, Op0IsKill); 1244 } 1245 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 1246 return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill); 1247 } 1248 return 0; 1249} 1250 1251unsigned fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) { 1252 if ((Subtarget->hasMVEIntegerOps()) && (MF->getDataLayout().isBigEndian())) { 1253 return fastEmitInst_r(ARM::MVE_VREV64_32, &ARM::MQPRRegClass, Op0, Op0IsKill); 1254 } 1255 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 1256 return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill); 1257 } 1258 return 0; 1259} 1260 1261unsigned fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v8f16_r(unsigned Op0, bool Op0IsKill) { 1262 if ((Subtarget->hasMVEIntegerOps()) && (MF->getDataLayout().isBigEndian())) { 1263 return fastEmitInst_r(ARM::MVE_VREV64_16, &ARM::MQPRRegClass, Op0, Op0IsKill); 1264 } 1265 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 1266 return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill); 1267 } 1268 return 0; 1269} 1270 1271unsigned fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v4f32_r(unsigned Op0, bool Op0IsKill) { 1272 if ((Subtarget->hasMVEIntegerOps()) && (MF->getDataLayout().isBigEndian())) { 1273 return fastEmitInst_r(ARM::MVE_VREV64_32, &ARM::MQPRRegClass, Op0, Op0IsKill); 1274 } 1275 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 1276 return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill); 1277 } 1278 return 0; 1279} 1280 1281unsigned fastEmit_ISD_BITCAST_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1282switch (RetVT.SimpleTy) { 1283 case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v16i8_r(Op0, Op0IsKill); 1284 case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v8i16_r(Op0, Op0IsKill); 1285 case MVT::v4i32: return fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v4i32_r(Op0, Op0IsKill); 1286 case MVT::v8f16: return fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v8f16_r(Op0, Op0IsKill); 1287 case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v4f32_r(Op0, Op0IsKill); 1288 default: return 0; 1289} 1290} 1291 1292unsigned fastEmit_ISD_BITCAST_MVT_v4f16_MVT_f64_r(unsigned Op0, bool Op0IsKill) { 1293 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 1294 return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill); 1295 } 1296 return 0; 1297} 1298 1299unsigned fastEmit_ISD_BITCAST_MVT_v4f16_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) { 1300 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 1301 return fastEmitInst_r(ARM::VREV16d8, &ARM::DPRRegClass, Op0, Op0IsKill); 1302 } 1303 return 0; 1304} 1305 1306unsigned fastEmit_ISD_BITCAST_MVT_v4f16_MVT_v2i32_r(unsigned Op0, bool Op0IsKill) { 1307 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 1308 return fastEmitInst_r(ARM::VREV32d16, &ARM::DPRRegClass, Op0, Op0IsKill); 1309 } 1310 return 0; 1311} 1312 1313unsigned fastEmit_ISD_BITCAST_MVT_v4f16_MVT_v1i64_r(unsigned Op0, bool Op0IsKill) { 1314 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 1315 return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill); 1316 } 1317 return 0; 1318} 1319 1320unsigned fastEmit_ISD_BITCAST_MVT_v4f16_MVT_v2f32_r(unsigned Op0, bool Op0IsKill) { 1321 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 1322 return fastEmitInst_r(ARM::VREV32d16, &ARM::DPRRegClass, Op0, Op0IsKill); 1323 } 1324 return 0; 1325} 1326 1327unsigned fastEmit_ISD_BITCAST_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1328switch (RetVT.SimpleTy) { 1329 case MVT::f64: return fastEmit_ISD_BITCAST_MVT_v4f16_MVT_f64_r(Op0, Op0IsKill); 1330 case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v4f16_MVT_v8i8_r(Op0, Op0IsKill); 1331 case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_v4f16_MVT_v2i32_r(Op0, Op0IsKill); 1332 case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v4f16_MVT_v1i64_r(Op0, Op0IsKill); 1333 case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_v4f16_MVT_v2f32_r(Op0, Op0IsKill); 1334 default: return 0; 1335} 1336} 1337 1338unsigned fastEmit_ISD_BITCAST_MVT_v8f16_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) { 1339 if ((Subtarget->hasMVEIntegerOps()) && (MF->getDataLayout().isBigEndian())) { 1340 return fastEmitInst_r(ARM::MVE_VREV16_8, &ARM::MQPRRegClass, Op0, Op0IsKill); 1341 } 1342 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 1343 return fastEmitInst_r(ARM::VREV16q8, &ARM::QPRRegClass, Op0, Op0IsKill); 1344 } 1345 return 0; 1346} 1347 1348unsigned fastEmit_ISD_BITCAST_MVT_v8f16_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) { 1349 if ((Subtarget->hasMVEIntegerOps()) && (MF->getDataLayout().isBigEndian())) { 1350 return fastEmitInst_r(ARM::MVE_VREV32_16, &ARM::MQPRRegClass, Op0, Op0IsKill); 1351 } 1352 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 1353 return fastEmitInst_r(ARM::VREV32q16, &ARM::QPRRegClass, Op0, Op0IsKill); 1354 } 1355 return 0; 1356} 1357 1358unsigned fastEmit_ISD_BITCAST_MVT_v8f16_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) { 1359 if ((Subtarget->hasMVEIntegerOps()) && (MF->getDataLayout().isBigEndian())) { 1360 return fastEmitInst_r(ARM::MVE_VREV64_16, &ARM::MQPRRegClass, Op0, Op0IsKill); 1361 } 1362 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 1363 return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill); 1364 } 1365 return 0; 1366} 1367 1368unsigned fastEmit_ISD_BITCAST_MVT_v8f16_MVT_v4f32_r(unsigned Op0, bool Op0IsKill) { 1369 if ((Subtarget->hasMVEIntegerOps()) && (MF->getDataLayout().isBigEndian())) { 1370 return fastEmitInst_r(ARM::MVE_VREV32_16, &ARM::MQPRRegClass, Op0, Op0IsKill); 1371 } 1372 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 1373 return fastEmitInst_r(ARM::VREV32q16, &ARM::QPRRegClass, Op0, Op0IsKill); 1374 } 1375 return 0; 1376} 1377 1378unsigned fastEmit_ISD_BITCAST_MVT_v8f16_MVT_v2f64_r(unsigned Op0, bool Op0IsKill) { 1379 if ((Subtarget->hasMVEIntegerOps()) && (MF->getDataLayout().isBigEndian())) { 1380 return fastEmitInst_r(ARM::MVE_VREV64_16, &ARM::MQPRRegClass, Op0, Op0IsKill); 1381 } 1382 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 1383 return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill); 1384 } 1385 return 0; 1386} 1387 1388unsigned fastEmit_ISD_BITCAST_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1389switch (RetVT.SimpleTy) { 1390 case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v8f16_MVT_v16i8_r(Op0, Op0IsKill); 1391 case MVT::v4i32: return fastEmit_ISD_BITCAST_MVT_v8f16_MVT_v4i32_r(Op0, Op0IsKill); 1392 case MVT::v2i64: return fastEmit_ISD_BITCAST_MVT_v8f16_MVT_v2i64_r(Op0, Op0IsKill); 1393 case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v8f16_MVT_v4f32_r(Op0, Op0IsKill); 1394 case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v8f16_MVT_v2f64_r(Op0, Op0IsKill); 1395 default: return 0; 1396} 1397} 1398 1399unsigned fastEmit_ISD_BITCAST_MVT_v2f32_MVT_f64_r(unsigned Op0, bool Op0IsKill) { 1400 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 1401 return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill); 1402 } 1403 return 0; 1404} 1405 1406unsigned fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) { 1407 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 1408 return fastEmitInst_r(ARM::VREV32d8, &ARM::DPRRegClass, Op0, Op0IsKill); 1409 } 1410 return 0; 1411} 1412 1413unsigned fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) { 1414 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 1415 return fastEmitInst_r(ARM::VREV32d16, &ARM::DPRRegClass, Op0, Op0IsKill); 1416 } 1417 return 0; 1418} 1419 1420unsigned fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v1i64_r(unsigned Op0, bool Op0IsKill) { 1421 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 1422 return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill); 1423 } 1424 return 0; 1425} 1426 1427unsigned fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v4f16_r(unsigned Op0, bool Op0IsKill) { 1428 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 1429 return fastEmitInst_r(ARM::VREV32d16, &ARM::DPRRegClass, Op0, Op0IsKill); 1430 } 1431 return 0; 1432} 1433 1434unsigned fastEmit_ISD_BITCAST_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1435switch (RetVT.SimpleTy) { 1436 case MVT::f64: return fastEmit_ISD_BITCAST_MVT_v2f32_MVT_f64_r(Op0, Op0IsKill); 1437 case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v8i8_r(Op0, Op0IsKill); 1438 case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v4i16_r(Op0, Op0IsKill); 1439 case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v1i64_r(Op0, Op0IsKill); 1440 case MVT::v4f16: return fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v4f16_r(Op0, Op0IsKill); 1441 default: return 0; 1442} 1443} 1444 1445unsigned fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) { 1446 if ((Subtarget->hasMVEIntegerOps()) && (MF->getDataLayout().isBigEndian())) { 1447 return fastEmitInst_r(ARM::MVE_VREV32_8, &ARM::MQPRRegClass, Op0, Op0IsKill); 1448 } 1449 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 1450 return fastEmitInst_r(ARM::VREV32q8, &ARM::QPRRegClass, Op0, Op0IsKill); 1451 } 1452 return 0; 1453} 1454 1455unsigned fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) { 1456 if ((Subtarget->hasMVEIntegerOps()) && (MF->getDataLayout().isBigEndian())) { 1457 return fastEmitInst_r(ARM::MVE_VREV32_16, &ARM::MQPRRegClass, Op0, Op0IsKill); 1458 } 1459 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 1460 return fastEmitInst_r(ARM::VREV32q16, &ARM::QPRRegClass, Op0, Op0IsKill); 1461 } 1462 return 0; 1463} 1464 1465unsigned fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) { 1466 if ((Subtarget->hasMVEIntegerOps()) && (MF->getDataLayout().isBigEndian())) { 1467 return fastEmitInst_r(ARM::MVE_VREV64_32, &ARM::MQPRRegClass, Op0, Op0IsKill); 1468 } 1469 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 1470 return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill); 1471 } 1472 return 0; 1473} 1474 1475unsigned fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v8f16_r(unsigned Op0, bool Op0IsKill) { 1476 if ((Subtarget->hasMVEIntegerOps()) && (MF->getDataLayout().isBigEndian())) { 1477 return fastEmitInst_r(ARM::MVE_VREV32_16, &ARM::MQPRRegClass, Op0, Op0IsKill); 1478 } 1479 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 1480 return fastEmitInst_r(ARM::VREV32q16, &ARM::QPRRegClass, Op0, Op0IsKill); 1481 } 1482 return 0; 1483} 1484 1485unsigned fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v2f64_r(unsigned Op0, bool Op0IsKill) { 1486 if ((Subtarget->hasMVEIntegerOps()) && (MF->getDataLayout().isBigEndian())) { 1487 return fastEmitInst_r(ARM::MVE_VREV64_32, &ARM::MQPRRegClass, Op0, Op0IsKill); 1488 } 1489 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 1490 return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill); 1491 } 1492 return 0; 1493} 1494 1495unsigned fastEmit_ISD_BITCAST_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1496switch (RetVT.SimpleTy) { 1497 case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v16i8_r(Op0, Op0IsKill); 1498 case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v8i16_r(Op0, Op0IsKill); 1499 case MVT::v2i64: return fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v2i64_r(Op0, Op0IsKill); 1500 case MVT::v8f16: return fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v8f16_r(Op0, Op0IsKill); 1501 case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v2f64_r(Op0, Op0IsKill); 1502 default: return 0; 1503} 1504} 1505 1506unsigned fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) { 1507 if ((Subtarget->hasMVEIntegerOps()) && (MF->getDataLayout().isBigEndian())) { 1508 return fastEmitInst_r(ARM::MVE_VREV64_8, &ARM::MQPRRegClass, Op0, Op0IsKill); 1509 } 1510 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 1511 return fastEmitInst_r(ARM::VREV64q8, &ARM::QPRRegClass, Op0, Op0IsKill); 1512 } 1513 return 0; 1514} 1515 1516unsigned fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) { 1517 if ((Subtarget->hasMVEIntegerOps()) && (MF->getDataLayout().isBigEndian())) { 1518 return fastEmitInst_r(ARM::MVE_VREV64_16, &ARM::MQPRRegClass, Op0, Op0IsKill); 1519 } 1520 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 1521 return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill); 1522 } 1523 return 0; 1524} 1525 1526unsigned fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) { 1527 if ((Subtarget->hasMVEIntegerOps()) && (MF->getDataLayout().isBigEndian())) { 1528 return fastEmitInst_r(ARM::MVE_VREV64_32, &ARM::MQPRRegClass, Op0, Op0IsKill); 1529 } 1530 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 1531 return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill); 1532 } 1533 return 0; 1534} 1535 1536unsigned fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v8f16_r(unsigned Op0, bool Op0IsKill) { 1537 if ((Subtarget->hasMVEIntegerOps()) && (MF->getDataLayout().isBigEndian())) { 1538 return fastEmitInst_r(ARM::MVE_VREV64_16, &ARM::MQPRRegClass, Op0, Op0IsKill); 1539 } 1540 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 1541 return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill); 1542 } 1543 return 0; 1544} 1545 1546unsigned fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v4f32_r(unsigned Op0, bool Op0IsKill) { 1547 if ((Subtarget->hasMVEIntegerOps()) && (MF->getDataLayout().isBigEndian())) { 1548 return fastEmitInst_r(ARM::MVE_VREV64_32, &ARM::MQPRRegClass, Op0, Op0IsKill); 1549 } 1550 if ((Subtarget->hasNEON()) && (MF->getDataLayout().isBigEndian())) { 1551 return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill); 1552 } 1553 return 0; 1554} 1555 1556unsigned fastEmit_ISD_BITCAST_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1557switch (RetVT.SimpleTy) { 1558 case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v16i8_r(Op0, Op0IsKill); 1559 case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v8i16_r(Op0, Op0IsKill); 1560 case MVT::v4i32: return fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v4i32_r(Op0, Op0IsKill); 1561 case MVT::v8f16: return fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v8f16_r(Op0, Op0IsKill); 1562 case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v4f32_r(Op0, Op0IsKill); 1563 default: return 0; 1564} 1565} 1566 1567unsigned fastEmit_ISD_BITCAST_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 1568 switch (VT.SimpleTy) { 1569 case MVT::i32: return fastEmit_ISD_BITCAST_MVT_i32_r(RetVT, Op0, Op0IsKill); 1570 case MVT::f32: return fastEmit_ISD_BITCAST_MVT_f32_r(RetVT, Op0, Op0IsKill); 1571 case MVT::f64: return fastEmit_ISD_BITCAST_MVT_f64_r(RetVT, Op0, Op0IsKill); 1572 case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v8i8_r(RetVT, Op0, Op0IsKill); 1573 case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v16i8_r(RetVT, Op0, Op0IsKill); 1574 case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_v4i16_r(RetVT, Op0, Op0IsKill); 1575 case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v8i16_r(RetVT, Op0, Op0IsKill); 1576 case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_v2i32_r(RetVT, Op0, Op0IsKill); 1577 case MVT::v4i32: return fastEmit_ISD_BITCAST_MVT_v4i32_r(RetVT, Op0, Op0IsKill); 1578 case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v1i64_r(RetVT, Op0, Op0IsKill); 1579 case MVT::v2i64: return fastEmit_ISD_BITCAST_MVT_v2i64_r(RetVT, Op0, Op0IsKill); 1580 case MVT::v4f16: return fastEmit_ISD_BITCAST_MVT_v4f16_r(RetVT, Op0, Op0IsKill); 1581 case MVT::v8f16: return fastEmit_ISD_BITCAST_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 1582 case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_v2f32_r(RetVT, Op0, Op0IsKill); 1583 case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 1584 case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v2f64_r(RetVT, Op0, Op0IsKill); 1585 default: return 0; 1586 } 1587} 1588 1589// FastEmit functions for ISD::BITREVERSE. 1590 1591unsigned fastEmit_ISD_BITREVERSE_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1592 if (RetVT.SimpleTy != MVT::i32) 1593 return 0; 1594 if ((Subtarget->isThumb2())) { 1595 return fastEmitInst_r(ARM::t2RBIT, &ARM::rGPRRegClass, Op0, Op0IsKill); 1596 } 1597 if ((Subtarget->hasV6T2Ops()) && (!Subtarget->isThumb())) { 1598 return fastEmitInst_r(ARM::RBIT, &ARM::GPRRegClass, Op0, Op0IsKill); 1599 } 1600 return 0; 1601} 1602 1603unsigned fastEmit_ISD_BITREVERSE_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 1604 switch (VT.SimpleTy) { 1605 case MVT::i32: return fastEmit_ISD_BITREVERSE_MVT_i32_r(RetVT, Op0, Op0IsKill); 1606 default: return 0; 1607 } 1608} 1609 1610// FastEmit functions for ISD::BRIND. 1611 1612unsigned fastEmit_ISD_BRIND_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1613 if (RetVT.SimpleTy != MVT::isVoid) 1614 return 0; 1615 if ((Subtarget->isThumb())) { 1616 return fastEmitInst_r(ARM::tBRIND, &ARM::GPRRegClass, Op0, Op0IsKill); 1617 } 1618 if ((!Subtarget->isThumb()) && (!Subtarget->hasV4TOps())) { 1619 return fastEmitInst_r(ARM::MOVPCRX, &ARM::GPRRegClass, Op0, Op0IsKill); 1620 } 1621 if ((Subtarget->hasV4TOps()) && (!Subtarget->isThumb())) { 1622 return fastEmitInst_r(ARM::BX, &ARM::GPRRegClass, Op0, Op0IsKill); 1623 } 1624 return 0; 1625} 1626 1627unsigned fastEmit_ISD_BRIND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 1628 switch (VT.SimpleTy) { 1629 case MVT::i32: return fastEmit_ISD_BRIND_MVT_i32_r(RetVT, Op0, Op0IsKill); 1630 default: return 0; 1631 } 1632} 1633 1634// FastEmit functions for ISD::BSWAP. 1635 1636unsigned fastEmit_ISD_BSWAP_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1637 if (RetVT.SimpleTy != MVT::i32) 1638 return 0; 1639 if ((Subtarget->isThumb2())) { 1640 return fastEmitInst_r(ARM::t2REV, &ARM::rGPRRegClass, Op0, Op0IsKill); 1641 } 1642 if ((Subtarget->hasV6Ops()) && (Subtarget->isThumb()) && (Subtarget->isThumb1Only())) { 1643 return fastEmitInst_r(ARM::tREV, &ARM::tGPRRegClass, Op0, Op0IsKill); 1644 } 1645 if ((Subtarget->hasV6Ops()) && (!Subtarget->isThumb())) { 1646 return fastEmitInst_r(ARM::REV, &ARM::GPRRegClass, Op0, Op0IsKill); 1647 } 1648 return 0; 1649} 1650 1651unsigned fastEmit_ISD_BSWAP_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1652 if (RetVT.SimpleTy != MVT::v8i16) 1653 return 0; 1654 if ((Subtarget->hasMVEIntegerOps())) { 1655 return fastEmitInst_r(ARM::MVE_VREV16_8, &ARM::MQPRRegClass, Op0, Op0IsKill); 1656 } 1657 return 0; 1658} 1659 1660unsigned fastEmit_ISD_BSWAP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1661 if (RetVT.SimpleTy != MVT::v4i32) 1662 return 0; 1663 if ((Subtarget->hasMVEIntegerOps())) { 1664 return fastEmitInst_r(ARM::MVE_VREV32_8, &ARM::MQPRRegClass, Op0, Op0IsKill); 1665 } 1666 return 0; 1667} 1668 1669unsigned fastEmit_ISD_BSWAP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 1670 switch (VT.SimpleTy) { 1671 case MVT::i32: return fastEmit_ISD_BSWAP_MVT_i32_r(RetVT, Op0, Op0IsKill); 1672 case MVT::v8i16: return fastEmit_ISD_BSWAP_MVT_v8i16_r(RetVT, Op0, Op0IsKill); 1673 case MVT::v4i32: return fastEmit_ISD_BSWAP_MVT_v4i32_r(RetVT, Op0, Op0IsKill); 1674 default: return 0; 1675 } 1676} 1677 1678// FastEmit functions for ISD::CTLZ. 1679 1680unsigned fastEmit_ISD_CTLZ_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1681 if (RetVT.SimpleTy != MVT::i32) 1682 return 0; 1683 if ((Subtarget->isThumb2())) { 1684 return fastEmitInst_r(ARM::t2CLZ, &ARM::rGPRRegClass, Op0, Op0IsKill); 1685 } 1686 if ((Subtarget->hasV5TOps()) && (!Subtarget->isThumb())) { 1687 return fastEmitInst_r(ARM::CLZ, &ARM::GPRRegClass, Op0, Op0IsKill); 1688 } 1689 return 0; 1690} 1691 1692unsigned fastEmit_ISD_CTLZ_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1693 if (RetVT.SimpleTy != MVT::v8i8) 1694 return 0; 1695 if ((Subtarget->hasNEON())) { 1696 return fastEmitInst_r(ARM::VCLZv8i8, &ARM::DPRRegClass, Op0, Op0IsKill); 1697 } 1698 return 0; 1699} 1700 1701unsigned fastEmit_ISD_CTLZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1702 if (RetVT.SimpleTy != MVT::v16i8) 1703 return 0; 1704 if ((Subtarget->hasMVEIntegerOps())) { 1705 return fastEmitInst_r(ARM::MVE_VCLZs8, &ARM::MQPRRegClass, Op0, Op0IsKill); 1706 } 1707 if ((Subtarget->hasNEON())) { 1708 return fastEmitInst_r(ARM::VCLZv16i8, &ARM::QPRRegClass, Op0, Op0IsKill); 1709 } 1710 return 0; 1711} 1712 1713unsigned fastEmit_ISD_CTLZ_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1714 if (RetVT.SimpleTy != MVT::v4i16) 1715 return 0; 1716 if ((Subtarget->hasNEON())) { 1717 return fastEmitInst_r(ARM::VCLZv4i16, &ARM::DPRRegClass, Op0, Op0IsKill); 1718 } 1719 return 0; 1720} 1721 1722unsigned fastEmit_ISD_CTLZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1723 if (RetVT.SimpleTy != MVT::v8i16) 1724 return 0; 1725 if ((Subtarget->hasMVEIntegerOps())) { 1726 return fastEmitInst_r(ARM::MVE_VCLZs16, &ARM::MQPRRegClass, Op0, Op0IsKill); 1727 } 1728 if ((Subtarget->hasNEON())) { 1729 return fastEmitInst_r(ARM::VCLZv8i16, &ARM::QPRRegClass, Op0, Op0IsKill); 1730 } 1731 return 0; 1732} 1733 1734unsigned fastEmit_ISD_CTLZ_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1735 if (RetVT.SimpleTy != MVT::v2i32) 1736 return 0; 1737 if ((Subtarget->hasNEON())) { 1738 return fastEmitInst_r(ARM::VCLZv2i32, &ARM::DPRRegClass, Op0, Op0IsKill); 1739 } 1740 return 0; 1741} 1742 1743unsigned fastEmit_ISD_CTLZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1744 if (RetVT.SimpleTy != MVT::v4i32) 1745 return 0; 1746 if ((Subtarget->hasMVEIntegerOps())) { 1747 return fastEmitInst_r(ARM::MVE_VCLZs32, &ARM::MQPRRegClass, Op0, Op0IsKill); 1748 } 1749 if ((Subtarget->hasNEON())) { 1750 return fastEmitInst_r(ARM::VCLZv4i32, &ARM::QPRRegClass, Op0, Op0IsKill); 1751 } 1752 return 0; 1753} 1754 1755unsigned fastEmit_ISD_CTLZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 1756 switch (VT.SimpleTy) { 1757 case MVT::i32: return fastEmit_ISD_CTLZ_MVT_i32_r(RetVT, Op0, Op0IsKill); 1758 case MVT::v8i8: return fastEmit_ISD_CTLZ_MVT_v8i8_r(RetVT, Op0, Op0IsKill); 1759 case MVT::v16i8: return fastEmit_ISD_CTLZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill); 1760 case MVT::v4i16: return fastEmit_ISD_CTLZ_MVT_v4i16_r(RetVT, Op0, Op0IsKill); 1761 case MVT::v8i16: return fastEmit_ISD_CTLZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill); 1762 case MVT::v2i32: return fastEmit_ISD_CTLZ_MVT_v2i32_r(RetVT, Op0, Op0IsKill); 1763 case MVT::v4i32: return fastEmit_ISD_CTLZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill); 1764 default: return 0; 1765 } 1766} 1767 1768// FastEmit functions for ISD::CTPOP. 1769 1770unsigned fastEmit_ISD_CTPOP_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1771 if (RetVT.SimpleTy != MVT::v8i8) 1772 return 0; 1773 if ((Subtarget->hasNEON())) { 1774 return fastEmitInst_r(ARM::VCNTd, &ARM::DPRRegClass, Op0, Op0IsKill); 1775 } 1776 return 0; 1777} 1778 1779unsigned fastEmit_ISD_CTPOP_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1780 if (RetVT.SimpleTy != MVT::v16i8) 1781 return 0; 1782 if ((Subtarget->hasNEON())) { 1783 return fastEmitInst_r(ARM::VCNTq, &ARM::QPRRegClass, Op0, Op0IsKill); 1784 } 1785 return 0; 1786} 1787 1788unsigned fastEmit_ISD_CTPOP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 1789 switch (VT.SimpleTy) { 1790 case MVT::v8i8: return fastEmit_ISD_CTPOP_MVT_v8i8_r(RetVT, Op0, Op0IsKill); 1791 case MVT::v16i8: return fastEmit_ISD_CTPOP_MVT_v16i8_r(RetVT, Op0, Op0IsKill); 1792 default: return 0; 1793 } 1794} 1795 1796// FastEmit functions for ISD::FABS. 1797 1798unsigned fastEmit_ISD_FABS_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1799 if (RetVT.SimpleTy != MVT::f16) 1800 return 0; 1801 if ((Subtarget->hasFullFP16())) { 1802 return fastEmitInst_r(ARM::VABSH, &ARM::HPRRegClass, Op0, Op0IsKill); 1803 } 1804 return 0; 1805} 1806 1807unsigned fastEmit_ISD_FABS_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1808 if (RetVT.SimpleTy != MVT::f32) 1809 return 0; 1810 if ((!Subtarget->useNEONForSinglePrecisionFP()) && (Subtarget->hasVFP2Base())) { 1811 return fastEmitInst_r(ARM::VABSS, &ARM::SPRRegClass, Op0, Op0IsKill); 1812 } 1813 return 0; 1814} 1815 1816unsigned fastEmit_ISD_FABS_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1817 if (RetVT.SimpleTy != MVT::f64) 1818 return 0; 1819 if ((Subtarget->hasFP64()) && (Subtarget->hasVFP2Base())) { 1820 return fastEmitInst_r(ARM::VABSD, &ARM::DPRRegClass, Op0, Op0IsKill); 1821 } 1822 return 0; 1823} 1824 1825unsigned fastEmit_ISD_FABS_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1826 if (RetVT.SimpleTy != MVT::v4f16) 1827 return 0; 1828 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 1829 return fastEmitInst_r(ARM::VABShd, &ARM::DPRRegClass, Op0, Op0IsKill); 1830 } 1831 return 0; 1832} 1833 1834unsigned fastEmit_ISD_FABS_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1835 if (RetVT.SimpleTy != MVT::v8f16) 1836 return 0; 1837 if ((Subtarget->hasMVEFloatOps())) { 1838 return fastEmitInst_r(ARM::MVE_VABSf16, &ARM::MQPRRegClass, Op0, Op0IsKill); 1839 } 1840 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 1841 return fastEmitInst_r(ARM::VABShq, &ARM::QPRRegClass, Op0, Op0IsKill); 1842 } 1843 return 0; 1844} 1845 1846unsigned fastEmit_ISD_FABS_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1847 if (RetVT.SimpleTy != MVT::v2f32) 1848 return 0; 1849 if ((Subtarget->hasNEON())) { 1850 return fastEmitInst_r(ARM::VABSfd, &ARM::DPRRegClass, Op0, Op0IsKill); 1851 } 1852 return 0; 1853} 1854 1855unsigned fastEmit_ISD_FABS_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1856 if (RetVT.SimpleTy != MVT::v4f32) 1857 return 0; 1858 if ((Subtarget->hasMVEFloatOps())) { 1859 return fastEmitInst_r(ARM::MVE_VABSf32, &ARM::MQPRRegClass, Op0, Op0IsKill); 1860 } 1861 if ((Subtarget->hasNEON())) { 1862 return fastEmitInst_r(ARM::VABSfq, &ARM::QPRRegClass, Op0, Op0IsKill); 1863 } 1864 return 0; 1865} 1866 1867unsigned fastEmit_ISD_FABS_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 1868 switch (VT.SimpleTy) { 1869 case MVT::f16: return fastEmit_ISD_FABS_MVT_f16_r(RetVT, Op0, Op0IsKill); 1870 case MVT::f32: return fastEmit_ISD_FABS_MVT_f32_r(RetVT, Op0, Op0IsKill); 1871 case MVT::f64: return fastEmit_ISD_FABS_MVT_f64_r(RetVT, Op0, Op0IsKill); 1872 case MVT::v4f16: return fastEmit_ISD_FABS_MVT_v4f16_r(RetVT, Op0, Op0IsKill); 1873 case MVT::v8f16: return fastEmit_ISD_FABS_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 1874 case MVT::v2f32: return fastEmit_ISD_FABS_MVT_v2f32_r(RetVT, Op0, Op0IsKill); 1875 case MVT::v4f32: return fastEmit_ISD_FABS_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 1876 default: return 0; 1877 } 1878} 1879 1880// FastEmit functions for ISD::FCEIL. 1881 1882unsigned fastEmit_ISD_FCEIL_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1883 if (RetVT.SimpleTy != MVT::f16) 1884 return 0; 1885 if ((Subtarget->hasFullFP16())) { 1886 return fastEmitInst_r(ARM::VRINTPH, &ARM::HPRRegClass, Op0, Op0IsKill); 1887 } 1888 return 0; 1889} 1890 1891unsigned fastEmit_ISD_FCEIL_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1892 if (RetVT.SimpleTy != MVT::f32) 1893 return 0; 1894 if ((Subtarget->hasFPARMv8Base())) { 1895 return fastEmitInst_r(ARM::VRINTPS, &ARM::SPRRegClass, Op0, Op0IsKill); 1896 } 1897 return 0; 1898} 1899 1900unsigned fastEmit_ISD_FCEIL_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1901 if (RetVT.SimpleTy != MVT::f64) 1902 return 0; 1903 if ((Subtarget->hasFP64()) && (Subtarget->hasFPARMv8Base())) { 1904 return fastEmitInst_r(ARM::VRINTPD, &ARM::DPRRegClass, Op0, Op0IsKill); 1905 } 1906 return 0; 1907} 1908 1909unsigned fastEmit_ISD_FCEIL_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1910 if (RetVT.SimpleTy != MVT::v8f16) 1911 return 0; 1912 if ((Subtarget->hasMVEFloatOps())) { 1913 return fastEmitInst_r(ARM::MVE_VRINTf16P, &ARM::MQPRRegClass, Op0, Op0IsKill); 1914 } 1915 return 0; 1916} 1917 1918unsigned fastEmit_ISD_FCEIL_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1919 if (RetVT.SimpleTy != MVT::v4f32) 1920 return 0; 1921 if ((Subtarget->hasMVEFloatOps())) { 1922 return fastEmitInst_r(ARM::MVE_VRINTf32P, &ARM::MQPRRegClass, Op0, Op0IsKill); 1923 } 1924 return 0; 1925} 1926 1927unsigned fastEmit_ISD_FCEIL_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 1928 switch (VT.SimpleTy) { 1929 case MVT::f16: return fastEmit_ISD_FCEIL_MVT_f16_r(RetVT, Op0, Op0IsKill); 1930 case MVT::f32: return fastEmit_ISD_FCEIL_MVT_f32_r(RetVT, Op0, Op0IsKill); 1931 case MVT::f64: return fastEmit_ISD_FCEIL_MVT_f64_r(RetVT, Op0, Op0IsKill); 1932 case MVT::v8f16: return fastEmit_ISD_FCEIL_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 1933 case MVT::v4f32: return fastEmit_ISD_FCEIL_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 1934 default: return 0; 1935 } 1936} 1937 1938// FastEmit functions for ISD::FFLOOR. 1939 1940unsigned fastEmit_ISD_FFLOOR_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1941 if (RetVT.SimpleTy != MVT::f16) 1942 return 0; 1943 if ((Subtarget->hasFullFP16())) { 1944 return fastEmitInst_r(ARM::VRINTMH, &ARM::HPRRegClass, Op0, Op0IsKill); 1945 } 1946 return 0; 1947} 1948 1949unsigned fastEmit_ISD_FFLOOR_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1950 if (RetVT.SimpleTy != MVT::f32) 1951 return 0; 1952 if ((Subtarget->hasFPARMv8Base())) { 1953 return fastEmitInst_r(ARM::VRINTMS, &ARM::SPRRegClass, Op0, Op0IsKill); 1954 } 1955 return 0; 1956} 1957 1958unsigned fastEmit_ISD_FFLOOR_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1959 if (RetVT.SimpleTy != MVT::f64) 1960 return 0; 1961 if ((Subtarget->hasFP64()) && (Subtarget->hasFPARMv8Base())) { 1962 return fastEmitInst_r(ARM::VRINTMD, &ARM::DPRRegClass, Op0, Op0IsKill); 1963 } 1964 return 0; 1965} 1966 1967unsigned fastEmit_ISD_FFLOOR_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1968 if (RetVT.SimpleTy != MVT::v8f16) 1969 return 0; 1970 if ((Subtarget->hasMVEFloatOps())) { 1971 return fastEmitInst_r(ARM::MVE_VRINTf16M, &ARM::MQPRRegClass, Op0, Op0IsKill); 1972 } 1973 return 0; 1974} 1975 1976unsigned fastEmit_ISD_FFLOOR_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1977 if (RetVT.SimpleTy != MVT::v4f32) 1978 return 0; 1979 if ((Subtarget->hasMVEFloatOps())) { 1980 return fastEmitInst_r(ARM::MVE_VRINTf32M, &ARM::MQPRRegClass, Op0, Op0IsKill); 1981 } 1982 return 0; 1983} 1984 1985unsigned fastEmit_ISD_FFLOOR_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 1986 switch (VT.SimpleTy) { 1987 case MVT::f16: return fastEmit_ISD_FFLOOR_MVT_f16_r(RetVT, Op0, Op0IsKill); 1988 case MVT::f32: return fastEmit_ISD_FFLOOR_MVT_f32_r(RetVT, Op0, Op0IsKill); 1989 case MVT::f64: return fastEmit_ISD_FFLOOR_MVT_f64_r(RetVT, Op0, Op0IsKill); 1990 case MVT::v8f16: return fastEmit_ISD_FFLOOR_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 1991 case MVT::v4f32: return fastEmit_ISD_FFLOOR_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 1992 default: return 0; 1993 } 1994} 1995 1996// FastEmit functions for ISD::FNEARBYINT. 1997 1998unsigned fastEmit_ISD_FNEARBYINT_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1999 if (RetVT.SimpleTy != MVT::f16) 2000 return 0; 2001 if ((Subtarget->hasFullFP16())) { 2002 return fastEmitInst_r(ARM::VRINTRH, &ARM::HPRRegClass, Op0, Op0IsKill); 2003 } 2004 return 0; 2005} 2006 2007unsigned fastEmit_ISD_FNEARBYINT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2008 if (RetVT.SimpleTy != MVT::f32) 2009 return 0; 2010 if ((Subtarget->hasFPARMv8Base())) { 2011 return fastEmitInst_r(ARM::VRINTRS, &ARM::SPRRegClass, Op0, Op0IsKill); 2012 } 2013 return 0; 2014} 2015 2016unsigned fastEmit_ISD_FNEARBYINT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2017 if (RetVT.SimpleTy != MVT::f64) 2018 return 0; 2019 if ((Subtarget->hasFP64()) && (Subtarget->hasFPARMv8Base())) { 2020 return fastEmitInst_r(ARM::VRINTRD, &ARM::DPRRegClass, Op0, Op0IsKill); 2021 } 2022 return 0; 2023} 2024 2025unsigned fastEmit_ISD_FNEARBYINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 2026 switch (VT.SimpleTy) { 2027 case MVT::f16: return fastEmit_ISD_FNEARBYINT_MVT_f16_r(RetVT, Op0, Op0IsKill); 2028 case MVT::f32: return fastEmit_ISD_FNEARBYINT_MVT_f32_r(RetVT, Op0, Op0IsKill); 2029 case MVT::f64: return fastEmit_ISD_FNEARBYINT_MVT_f64_r(RetVT, Op0, Op0IsKill); 2030 default: return 0; 2031 } 2032} 2033 2034// FastEmit functions for ISD::FNEG. 2035 2036unsigned fastEmit_ISD_FNEG_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2037 if (RetVT.SimpleTy != MVT::f16) 2038 return 0; 2039 if ((Subtarget->hasFullFP16())) { 2040 return fastEmitInst_r(ARM::VNEGH, &ARM::HPRRegClass, Op0, Op0IsKill); 2041 } 2042 return 0; 2043} 2044 2045unsigned fastEmit_ISD_FNEG_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2046 if (RetVT.SimpleTy != MVT::f32) 2047 return 0; 2048 if ((!Subtarget->useNEONForSinglePrecisionFP()) && (Subtarget->hasVFP2Base())) { 2049 return fastEmitInst_r(ARM::VNEGS, &ARM::SPRRegClass, Op0, Op0IsKill); 2050 } 2051 return 0; 2052} 2053 2054unsigned fastEmit_ISD_FNEG_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2055 if (RetVT.SimpleTy != MVT::f64) 2056 return 0; 2057 if ((Subtarget->hasFP64()) && (Subtarget->hasVFP2Base())) { 2058 return fastEmitInst_r(ARM::VNEGD, &ARM::DPRRegClass, Op0, Op0IsKill); 2059 } 2060 return 0; 2061} 2062 2063unsigned fastEmit_ISD_FNEG_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2064 if (RetVT.SimpleTy != MVT::v4f16) 2065 return 0; 2066 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 2067 return fastEmitInst_r(ARM::VNEGhd, &ARM::DPRRegClass, Op0, Op0IsKill); 2068 } 2069 return 0; 2070} 2071 2072unsigned fastEmit_ISD_FNEG_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2073 if (RetVT.SimpleTy != MVT::v8f16) 2074 return 0; 2075 if ((Subtarget->hasMVEFloatOps())) { 2076 return fastEmitInst_r(ARM::MVE_VNEGf16, &ARM::MQPRRegClass, Op0, Op0IsKill); 2077 } 2078 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 2079 return fastEmitInst_r(ARM::VNEGhq, &ARM::QPRRegClass, Op0, Op0IsKill); 2080 } 2081 return 0; 2082} 2083 2084unsigned fastEmit_ISD_FNEG_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2085 if (RetVT.SimpleTy != MVT::v2f32) 2086 return 0; 2087 if ((Subtarget->hasNEON())) { 2088 return fastEmitInst_r(ARM::VNEGfd, &ARM::DPRRegClass, Op0, Op0IsKill); 2089 } 2090 return 0; 2091} 2092 2093unsigned fastEmit_ISD_FNEG_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2094 if (RetVT.SimpleTy != MVT::v4f32) 2095 return 0; 2096 if ((Subtarget->hasMVEFloatOps())) { 2097 return fastEmitInst_r(ARM::MVE_VNEGf32, &ARM::MQPRRegClass, Op0, Op0IsKill); 2098 } 2099 if ((Subtarget->hasNEON())) { 2100 return fastEmitInst_r(ARM::VNEGf32q, &ARM::QPRRegClass, Op0, Op0IsKill); 2101 } 2102 return 0; 2103} 2104 2105unsigned fastEmit_ISD_FNEG_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 2106 switch (VT.SimpleTy) { 2107 case MVT::f16: return fastEmit_ISD_FNEG_MVT_f16_r(RetVT, Op0, Op0IsKill); 2108 case MVT::f32: return fastEmit_ISD_FNEG_MVT_f32_r(RetVT, Op0, Op0IsKill); 2109 case MVT::f64: return fastEmit_ISD_FNEG_MVT_f64_r(RetVT, Op0, Op0IsKill); 2110 case MVT::v4f16: return fastEmit_ISD_FNEG_MVT_v4f16_r(RetVT, Op0, Op0IsKill); 2111 case MVT::v8f16: return fastEmit_ISD_FNEG_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 2112 case MVT::v2f32: return fastEmit_ISD_FNEG_MVT_v2f32_r(RetVT, Op0, Op0IsKill); 2113 case MVT::v4f32: return fastEmit_ISD_FNEG_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 2114 default: return 0; 2115 } 2116} 2117 2118// FastEmit functions for ISD::FP_EXTEND. 2119 2120unsigned fastEmit_ISD_FP_EXTEND_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2121 if (RetVT.SimpleTy != MVT::f64) 2122 return 0; 2123 if ((Subtarget->hasFP64()) && (Subtarget->hasVFP2Base())) { 2124 return fastEmitInst_r(ARM::VCVTDS, &ARM::DPRRegClass, Op0, Op0IsKill); 2125 } 2126 return 0; 2127} 2128 2129unsigned fastEmit_ISD_FP_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 2130 switch (VT.SimpleTy) { 2131 case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f32_r(RetVT, Op0, Op0IsKill); 2132 default: return 0; 2133 } 2134} 2135 2136// FastEmit functions for ISD::FP_ROUND. 2137 2138unsigned fastEmit_ISD_FP_ROUND_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2139 if (RetVT.SimpleTy != MVT::f32) 2140 return 0; 2141 if ((Subtarget->hasFP64()) && (Subtarget->hasVFP2Base())) { 2142 return fastEmitInst_r(ARM::VCVTSD, &ARM::SPRRegClass, Op0, Op0IsKill); 2143 } 2144 return 0; 2145} 2146 2147unsigned fastEmit_ISD_FP_ROUND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 2148 switch (VT.SimpleTy) { 2149 case MVT::f64: return fastEmit_ISD_FP_ROUND_MVT_f64_r(RetVT, Op0, Op0IsKill); 2150 default: return 0; 2151 } 2152} 2153 2154// FastEmit functions for ISD::FP_TO_SINT. 2155 2156unsigned fastEmit_ISD_FP_TO_SINT_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2157 if (RetVT.SimpleTy != MVT::v4i16) 2158 return 0; 2159 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 2160 return fastEmitInst_r(ARM::VCVTh2sd, &ARM::DPRRegClass, Op0, Op0IsKill); 2161 } 2162 return 0; 2163} 2164 2165unsigned fastEmit_ISD_FP_TO_SINT_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2166 if (RetVT.SimpleTy != MVT::v8i16) 2167 return 0; 2168 if ((Subtarget->hasMVEFloatOps())) { 2169 return fastEmitInst_r(ARM::MVE_VCVTs16f16z, &ARM::MQPRRegClass, Op0, Op0IsKill); 2170 } 2171 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 2172 return fastEmitInst_r(ARM::VCVTh2sq, &ARM::QPRRegClass, Op0, Op0IsKill); 2173 } 2174 return 0; 2175} 2176 2177unsigned fastEmit_ISD_FP_TO_SINT_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2178 if (RetVT.SimpleTy != MVT::v2i32) 2179 return 0; 2180 if ((Subtarget->hasNEON())) { 2181 return fastEmitInst_r(ARM::VCVTf2sd, &ARM::DPRRegClass, Op0, Op0IsKill); 2182 } 2183 return 0; 2184} 2185 2186unsigned fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2187 if (RetVT.SimpleTy != MVT::v4i32) 2188 return 0; 2189 if ((Subtarget->hasMVEFloatOps())) { 2190 return fastEmitInst_r(ARM::MVE_VCVTs32f32z, &ARM::MQPRRegClass, Op0, Op0IsKill); 2191 } 2192 if ((Subtarget->hasNEON())) { 2193 return fastEmitInst_r(ARM::VCVTf2sq, &ARM::QPRRegClass, Op0, Op0IsKill); 2194 } 2195 return 0; 2196} 2197 2198unsigned fastEmit_ISD_FP_TO_SINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 2199 switch (VT.SimpleTy) { 2200 case MVT::v4f16: return fastEmit_ISD_FP_TO_SINT_MVT_v4f16_r(RetVT, Op0, Op0IsKill); 2201 case MVT::v8f16: return fastEmit_ISD_FP_TO_SINT_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 2202 case MVT::v2f32: return fastEmit_ISD_FP_TO_SINT_MVT_v2f32_r(RetVT, Op0, Op0IsKill); 2203 case MVT::v4f32: return fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 2204 default: return 0; 2205 } 2206} 2207 2208// FastEmit functions for ISD::FP_TO_UINT. 2209 2210unsigned fastEmit_ISD_FP_TO_UINT_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2211 if (RetVT.SimpleTy != MVT::v4i16) 2212 return 0; 2213 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 2214 return fastEmitInst_r(ARM::VCVTh2ud, &ARM::DPRRegClass, Op0, Op0IsKill); 2215 } 2216 return 0; 2217} 2218 2219unsigned fastEmit_ISD_FP_TO_UINT_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2220 if (RetVT.SimpleTy != MVT::v8i16) 2221 return 0; 2222 if ((Subtarget->hasMVEFloatOps())) { 2223 return fastEmitInst_r(ARM::MVE_VCVTu16f16z, &ARM::MQPRRegClass, Op0, Op0IsKill); 2224 } 2225 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 2226 return fastEmitInst_r(ARM::VCVTh2uq, &ARM::QPRRegClass, Op0, Op0IsKill); 2227 } 2228 return 0; 2229} 2230 2231unsigned fastEmit_ISD_FP_TO_UINT_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2232 if (RetVT.SimpleTy != MVT::v2i32) 2233 return 0; 2234 if ((Subtarget->hasNEON())) { 2235 return fastEmitInst_r(ARM::VCVTf2ud, &ARM::DPRRegClass, Op0, Op0IsKill); 2236 } 2237 return 0; 2238} 2239 2240unsigned fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2241 if (RetVT.SimpleTy != MVT::v4i32) 2242 return 0; 2243 if ((Subtarget->hasMVEFloatOps())) { 2244 return fastEmitInst_r(ARM::MVE_VCVTu32f32z, &ARM::MQPRRegClass, Op0, Op0IsKill); 2245 } 2246 if ((Subtarget->hasNEON())) { 2247 return fastEmitInst_r(ARM::VCVTf2uq, &ARM::QPRRegClass, Op0, Op0IsKill); 2248 } 2249 return 0; 2250} 2251 2252unsigned fastEmit_ISD_FP_TO_UINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 2253 switch (VT.SimpleTy) { 2254 case MVT::v4f16: return fastEmit_ISD_FP_TO_UINT_MVT_v4f16_r(RetVT, Op0, Op0IsKill); 2255 case MVT::v8f16: return fastEmit_ISD_FP_TO_UINT_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 2256 case MVT::v2f32: return fastEmit_ISD_FP_TO_UINT_MVT_v2f32_r(RetVT, Op0, Op0IsKill); 2257 case MVT::v4f32: return fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 2258 default: return 0; 2259 } 2260} 2261 2262// FastEmit functions for ISD::FRINT. 2263 2264unsigned fastEmit_ISD_FRINT_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2265 if (RetVT.SimpleTy != MVT::f16) 2266 return 0; 2267 if ((Subtarget->hasFullFP16())) { 2268 return fastEmitInst_r(ARM::VRINTXH, &ARM::HPRRegClass, Op0, Op0IsKill); 2269 } 2270 return 0; 2271} 2272 2273unsigned fastEmit_ISD_FRINT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2274 if (RetVT.SimpleTy != MVT::f32) 2275 return 0; 2276 if ((Subtarget->hasFPARMv8Base())) { 2277 return fastEmitInst_r(ARM::VRINTXS, &ARM::SPRRegClass, Op0, Op0IsKill); 2278 } 2279 return 0; 2280} 2281 2282unsigned fastEmit_ISD_FRINT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2283 if (RetVT.SimpleTy != MVT::f64) 2284 return 0; 2285 if ((Subtarget->hasFP64()) && (Subtarget->hasFPARMv8Base())) { 2286 return fastEmitInst_r(ARM::VRINTXD, &ARM::DPRRegClass, Op0, Op0IsKill); 2287 } 2288 return 0; 2289} 2290 2291unsigned fastEmit_ISD_FRINT_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2292 if (RetVT.SimpleTy != MVT::v8f16) 2293 return 0; 2294 if ((Subtarget->hasMVEFloatOps())) { 2295 return fastEmitInst_r(ARM::MVE_VRINTf16X, &ARM::MQPRRegClass, Op0, Op0IsKill); 2296 } 2297 return 0; 2298} 2299 2300unsigned fastEmit_ISD_FRINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2301 if (RetVT.SimpleTy != MVT::v4f32) 2302 return 0; 2303 if ((Subtarget->hasMVEFloatOps())) { 2304 return fastEmitInst_r(ARM::MVE_VRINTf32X, &ARM::MQPRRegClass, Op0, Op0IsKill); 2305 } 2306 return 0; 2307} 2308 2309unsigned fastEmit_ISD_FRINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 2310 switch (VT.SimpleTy) { 2311 case MVT::f16: return fastEmit_ISD_FRINT_MVT_f16_r(RetVT, Op0, Op0IsKill); 2312 case MVT::f32: return fastEmit_ISD_FRINT_MVT_f32_r(RetVT, Op0, Op0IsKill); 2313 case MVT::f64: return fastEmit_ISD_FRINT_MVT_f64_r(RetVT, Op0, Op0IsKill); 2314 case MVT::v8f16: return fastEmit_ISD_FRINT_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 2315 case MVT::v4f32: return fastEmit_ISD_FRINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 2316 default: return 0; 2317 } 2318} 2319 2320// FastEmit functions for ISD::FROUND. 2321 2322unsigned fastEmit_ISD_FROUND_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2323 if (RetVT.SimpleTy != MVT::f16) 2324 return 0; 2325 if ((Subtarget->hasFullFP16())) { 2326 return fastEmitInst_r(ARM::VRINTAH, &ARM::HPRRegClass, Op0, Op0IsKill); 2327 } 2328 return 0; 2329} 2330 2331unsigned fastEmit_ISD_FROUND_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2332 if (RetVT.SimpleTy != MVT::f32) 2333 return 0; 2334 if ((Subtarget->hasFPARMv8Base())) { 2335 return fastEmitInst_r(ARM::VRINTAS, &ARM::SPRRegClass, Op0, Op0IsKill); 2336 } 2337 return 0; 2338} 2339 2340unsigned fastEmit_ISD_FROUND_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2341 if (RetVT.SimpleTy != MVT::f64) 2342 return 0; 2343 if ((Subtarget->hasFP64()) && (Subtarget->hasFPARMv8Base())) { 2344 return fastEmitInst_r(ARM::VRINTAD, &ARM::DPRRegClass, Op0, Op0IsKill); 2345 } 2346 return 0; 2347} 2348 2349unsigned fastEmit_ISD_FROUND_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2350 if (RetVT.SimpleTy != MVT::v8f16) 2351 return 0; 2352 if ((Subtarget->hasMVEFloatOps())) { 2353 return fastEmitInst_r(ARM::MVE_VRINTf16A, &ARM::MQPRRegClass, Op0, Op0IsKill); 2354 } 2355 return 0; 2356} 2357 2358unsigned fastEmit_ISD_FROUND_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2359 if (RetVT.SimpleTy != MVT::v4f32) 2360 return 0; 2361 if ((Subtarget->hasMVEFloatOps())) { 2362 return fastEmitInst_r(ARM::MVE_VRINTf32A, &ARM::MQPRRegClass, Op0, Op0IsKill); 2363 } 2364 return 0; 2365} 2366 2367unsigned fastEmit_ISD_FROUND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 2368 switch (VT.SimpleTy) { 2369 case MVT::f16: return fastEmit_ISD_FROUND_MVT_f16_r(RetVT, Op0, Op0IsKill); 2370 case MVT::f32: return fastEmit_ISD_FROUND_MVT_f32_r(RetVT, Op0, Op0IsKill); 2371 case MVT::f64: return fastEmit_ISD_FROUND_MVT_f64_r(RetVT, Op0, Op0IsKill); 2372 case MVT::v8f16: return fastEmit_ISD_FROUND_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 2373 case MVT::v4f32: return fastEmit_ISD_FROUND_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 2374 default: return 0; 2375 } 2376} 2377 2378// FastEmit functions for ISD::FSQRT. 2379 2380unsigned fastEmit_ISD_FSQRT_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2381 if (RetVT.SimpleTy != MVT::f16) 2382 return 0; 2383 if ((Subtarget->hasFullFP16())) { 2384 return fastEmitInst_r(ARM::VSQRTH, &ARM::HPRRegClass, Op0, Op0IsKill); 2385 } 2386 return 0; 2387} 2388 2389unsigned fastEmit_ISD_FSQRT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2390 if (RetVT.SimpleTy != MVT::f32) 2391 return 0; 2392 if ((Subtarget->hasVFP2Base())) { 2393 return fastEmitInst_r(ARM::VSQRTS, &ARM::SPRRegClass, Op0, Op0IsKill); 2394 } 2395 return 0; 2396} 2397 2398unsigned fastEmit_ISD_FSQRT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2399 if (RetVT.SimpleTy != MVT::f64) 2400 return 0; 2401 if ((Subtarget->hasFP64()) && (Subtarget->hasVFP2Base())) { 2402 return fastEmitInst_r(ARM::VSQRTD, &ARM::DPRRegClass, Op0, Op0IsKill); 2403 } 2404 return 0; 2405} 2406 2407unsigned fastEmit_ISD_FSQRT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 2408 switch (VT.SimpleTy) { 2409 case MVT::f16: return fastEmit_ISD_FSQRT_MVT_f16_r(RetVT, Op0, Op0IsKill); 2410 case MVT::f32: return fastEmit_ISD_FSQRT_MVT_f32_r(RetVT, Op0, Op0IsKill); 2411 case MVT::f64: return fastEmit_ISD_FSQRT_MVT_f64_r(RetVT, Op0, Op0IsKill); 2412 default: return 0; 2413 } 2414} 2415 2416// FastEmit functions for ISD::FTRUNC. 2417 2418unsigned fastEmit_ISD_FTRUNC_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2419 if (RetVT.SimpleTy != MVT::f16) 2420 return 0; 2421 if ((Subtarget->hasFullFP16())) { 2422 return fastEmitInst_r(ARM::VRINTZH, &ARM::HPRRegClass, Op0, Op0IsKill); 2423 } 2424 return 0; 2425} 2426 2427unsigned fastEmit_ISD_FTRUNC_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2428 if (RetVT.SimpleTy != MVT::f32) 2429 return 0; 2430 if ((Subtarget->hasFPARMv8Base())) { 2431 return fastEmitInst_r(ARM::VRINTZS, &ARM::SPRRegClass, Op0, Op0IsKill); 2432 } 2433 return 0; 2434} 2435 2436unsigned fastEmit_ISD_FTRUNC_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2437 if (RetVT.SimpleTy != MVT::f64) 2438 return 0; 2439 if ((Subtarget->hasFP64()) && (Subtarget->hasFPARMv8Base())) { 2440 return fastEmitInst_r(ARM::VRINTZD, &ARM::DPRRegClass, Op0, Op0IsKill); 2441 } 2442 return 0; 2443} 2444 2445unsigned fastEmit_ISD_FTRUNC_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2446 if (RetVT.SimpleTy != MVT::v8f16) 2447 return 0; 2448 if ((Subtarget->hasMVEFloatOps())) { 2449 return fastEmitInst_r(ARM::MVE_VRINTf16Z, &ARM::MQPRRegClass, Op0, Op0IsKill); 2450 } 2451 return 0; 2452} 2453 2454unsigned fastEmit_ISD_FTRUNC_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2455 if (RetVT.SimpleTy != MVT::v4f32) 2456 return 0; 2457 if ((Subtarget->hasMVEFloatOps())) { 2458 return fastEmitInst_r(ARM::MVE_VRINTf32Z, &ARM::MQPRRegClass, Op0, Op0IsKill); 2459 } 2460 return 0; 2461} 2462 2463unsigned fastEmit_ISD_FTRUNC_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 2464 switch (VT.SimpleTy) { 2465 case MVT::f16: return fastEmit_ISD_FTRUNC_MVT_f16_r(RetVT, Op0, Op0IsKill); 2466 case MVT::f32: return fastEmit_ISD_FTRUNC_MVT_f32_r(RetVT, Op0, Op0IsKill); 2467 case MVT::f64: return fastEmit_ISD_FTRUNC_MVT_f64_r(RetVT, Op0, Op0IsKill); 2468 case MVT::v8f16: return fastEmit_ISD_FTRUNC_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 2469 case MVT::v4f32: return fastEmit_ISD_FTRUNC_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 2470 default: return 0; 2471 } 2472} 2473 2474// FastEmit functions for ISD::SIGN_EXTEND. 2475 2476unsigned fastEmit_ISD_SIGN_EXTEND_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2477 if (RetVT.SimpleTy != MVT::v8i16) 2478 return 0; 2479 if ((Subtarget->hasNEON())) { 2480 return fastEmitInst_r(ARM::VMOVLsv8i16, &ARM::QPRRegClass, Op0, Op0IsKill); 2481 } 2482 return 0; 2483} 2484 2485unsigned fastEmit_ISD_SIGN_EXTEND_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2486 if (RetVT.SimpleTy != MVT::v4i32) 2487 return 0; 2488 if ((Subtarget->hasNEON())) { 2489 return fastEmitInst_r(ARM::VMOVLsv4i32, &ARM::QPRRegClass, Op0, Op0IsKill); 2490 } 2491 return 0; 2492} 2493 2494unsigned fastEmit_ISD_SIGN_EXTEND_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2495 if (RetVT.SimpleTy != MVT::v2i64) 2496 return 0; 2497 if ((Subtarget->hasNEON())) { 2498 return fastEmitInst_r(ARM::VMOVLsv2i64, &ARM::QPRRegClass, Op0, Op0IsKill); 2499 } 2500 return 0; 2501} 2502 2503unsigned fastEmit_ISD_SIGN_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 2504 switch (VT.SimpleTy) { 2505 case MVT::v8i8: return fastEmit_ISD_SIGN_EXTEND_MVT_v8i8_r(RetVT, Op0, Op0IsKill); 2506 case MVT::v4i16: return fastEmit_ISD_SIGN_EXTEND_MVT_v4i16_r(RetVT, Op0, Op0IsKill); 2507 case MVT::v2i32: return fastEmit_ISD_SIGN_EXTEND_MVT_v2i32_r(RetVT, Op0, Op0IsKill); 2508 default: return 0; 2509 } 2510} 2511 2512// FastEmit functions for ISD::SINT_TO_FP. 2513 2514unsigned fastEmit_ISD_SINT_TO_FP_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2515 if (RetVT.SimpleTy != MVT::v4f16) 2516 return 0; 2517 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 2518 return fastEmitInst_r(ARM::VCVTs2hd, &ARM::DPRRegClass, Op0, Op0IsKill); 2519 } 2520 return 0; 2521} 2522 2523unsigned fastEmit_ISD_SINT_TO_FP_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2524 if (RetVT.SimpleTy != MVT::v8f16) 2525 return 0; 2526 if ((Subtarget->hasMVEFloatOps())) { 2527 return fastEmitInst_r(ARM::MVE_VCVTf16s16n, &ARM::MQPRRegClass, Op0, Op0IsKill); 2528 } 2529 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 2530 return fastEmitInst_r(ARM::VCVTs2hq, &ARM::QPRRegClass, Op0, Op0IsKill); 2531 } 2532 return 0; 2533} 2534 2535unsigned fastEmit_ISD_SINT_TO_FP_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2536 if (RetVT.SimpleTy != MVT::v2f32) 2537 return 0; 2538 if ((Subtarget->hasNEON())) { 2539 return fastEmitInst_r(ARM::VCVTs2fd, &ARM::DPRRegClass, Op0, Op0IsKill); 2540 } 2541 return 0; 2542} 2543 2544unsigned fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2545 if (RetVT.SimpleTy != MVT::v4f32) 2546 return 0; 2547 if ((Subtarget->hasMVEFloatOps())) { 2548 return fastEmitInst_r(ARM::MVE_VCVTf32s32n, &ARM::MQPRRegClass, Op0, Op0IsKill); 2549 } 2550 if ((Subtarget->hasNEON())) { 2551 return fastEmitInst_r(ARM::VCVTs2fq, &ARM::QPRRegClass, Op0, Op0IsKill); 2552 } 2553 return 0; 2554} 2555 2556unsigned fastEmit_ISD_SINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 2557 switch (VT.SimpleTy) { 2558 case MVT::v4i16: return fastEmit_ISD_SINT_TO_FP_MVT_v4i16_r(RetVT, Op0, Op0IsKill); 2559 case MVT::v8i16: return fastEmit_ISD_SINT_TO_FP_MVT_v8i16_r(RetVT, Op0, Op0IsKill); 2560 case MVT::v2i32: return fastEmit_ISD_SINT_TO_FP_MVT_v2i32_r(RetVT, Op0, Op0IsKill); 2561 case MVT::v4i32: return fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(RetVT, Op0, Op0IsKill); 2562 default: return 0; 2563 } 2564} 2565 2566// FastEmit functions for ISD::TRUNCATE. 2567 2568unsigned fastEmit_ISD_TRUNCATE_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2569 if (RetVT.SimpleTy != MVT::v8i8) 2570 return 0; 2571 if ((Subtarget->hasNEON())) { 2572 return fastEmitInst_r(ARM::VMOVNv8i8, &ARM::DPRRegClass, Op0, Op0IsKill); 2573 } 2574 return 0; 2575} 2576 2577unsigned fastEmit_ISD_TRUNCATE_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2578 if (RetVT.SimpleTy != MVT::v4i16) 2579 return 0; 2580 if ((Subtarget->hasNEON())) { 2581 return fastEmitInst_r(ARM::VMOVNv4i16, &ARM::DPRRegClass, Op0, Op0IsKill); 2582 } 2583 return 0; 2584} 2585 2586unsigned fastEmit_ISD_TRUNCATE_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2587 if (RetVT.SimpleTy != MVT::v2i32) 2588 return 0; 2589 if ((Subtarget->hasNEON())) { 2590 return fastEmitInst_r(ARM::VMOVNv2i32, &ARM::DPRRegClass, Op0, Op0IsKill); 2591 } 2592 return 0; 2593} 2594 2595unsigned fastEmit_ISD_TRUNCATE_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 2596 switch (VT.SimpleTy) { 2597 case MVT::v8i16: return fastEmit_ISD_TRUNCATE_MVT_v8i16_r(RetVT, Op0, Op0IsKill); 2598 case MVT::v4i32: return fastEmit_ISD_TRUNCATE_MVT_v4i32_r(RetVT, Op0, Op0IsKill); 2599 case MVT::v2i64: return fastEmit_ISD_TRUNCATE_MVT_v2i64_r(RetVT, Op0, Op0IsKill); 2600 default: return 0; 2601 } 2602} 2603 2604// FastEmit functions for ISD::UINT_TO_FP. 2605 2606unsigned fastEmit_ISD_UINT_TO_FP_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2607 if (RetVT.SimpleTy != MVT::v4f16) 2608 return 0; 2609 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 2610 return fastEmitInst_r(ARM::VCVTu2hd, &ARM::DPRRegClass, Op0, Op0IsKill); 2611 } 2612 return 0; 2613} 2614 2615unsigned fastEmit_ISD_UINT_TO_FP_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2616 if (RetVT.SimpleTy != MVT::v8f16) 2617 return 0; 2618 if ((Subtarget->hasMVEFloatOps())) { 2619 return fastEmitInst_r(ARM::MVE_VCVTf16u16n, &ARM::MQPRRegClass, Op0, Op0IsKill); 2620 } 2621 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 2622 return fastEmitInst_r(ARM::VCVTu2hq, &ARM::QPRRegClass, Op0, Op0IsKill); 2623 } 2624 return 0; 2625} 2626 2627unsigned fastEmit_ISD_UINT_TO_FP_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2628 if (RetVT.SimpleTy != MVT::v2f32) 2629 return 0; 2630 if ((Subtarget->hasNEON())) { 2631 return fastEmitInst_r(ARM::VCVTu2fd, &ARM::DPRRegClass, Op0, Op0IsKill); 2632 } 2633 return 0; 2634} 2635 2636unsigned fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2637 if (RetVT.SimpleTy != MVT::v4f32) 2638 return 0; 2639 if ((Subtarget->hasMVEFloatOps())) { 2640 return fastEmitInst_r(ARM::MVE_VCVTf32u32n, &ARM::MQPRRegClass, Op0, Op0IsKill); 2641 } 2642 if ((Subtarget->hasNEON())) { 2643 return fastEmitInst_r(ARM::VCVTu2fq, &ARM::QPRRegClass, Op0, Op0IsKill); 2644 } 2645 return 0; 2646} 2647 2648unsigned fastEmit_ISD_UINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 2649 switch (VT.SimpleTy) { 2650 case MVT::v4i16: return fastEmit_ISD_UINT_TO_FP_MVT_v4i16_r(RetVT, Op0, Op0IsKill); 2651 case MVT::v8i16: return fastEmit_ISD_UINT_TO_FP_MVT_v8i16_r(RetVT, Op0, Op0IsKill); 2652 case MVT::v2i32: return fastEmit_ISD_UINT_TO_FP_MVT_v2i32_r(RetVT, Op0, Op0IsKill); 2653 case MVT::v4i32: return fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(RetVT, Op0, Op0IsKill); 2654 default: return 0; 2655 } 2656} 2657 2658// FastEmit functions for ISD::VECREDUCE_ADD. 2659 2660unsigned fastEmit_ISD_VECREDUCE_ADD_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2661 if (RetVT.SimpleTy != MVT::i32) 2662 return 0; 2663 if ((Subtarget->hasMVEIntegerOps())) { 2664 return fastEmitInst_r(ARM::MVE_VADDVu8no_acc, &ARM::tGPREvenRegClass, Op0, Op0IsKill); 2665 } 2666 return 0; 2667} 2668 2669unsigned fastEmit_ISD_VECREDUCE_ADD_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2670 if (RetVT.SimpleTy != MVT::i32) 2671 return 0; 2672 if ((Subtarget->hasMVEIntegerOps())) { 2673 return fastEmitInst_r(ARM::MVE_VADDVu16no_acc, &ARM::tGPREvenRegClass, Op0, Op0IsKill); 2674 } 2675 return 0; 2676} 2677 2678unsigned fastEmit_ISD_VECREDUCE_ADD_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2679 if (RetVT.SimpleTy != MVT::i32) 2680 return 0; 2681 if ((Subtarget->hasMVEIntegerOps())) { 2682 return fastEmitInst_r(ARM::MVE_VADDVu32no_acc, &ARM::tGPREvenRegClass, Op0, Op0IsKill); 2683 } 2684 return 0; 2685} 2686 2687unsigned fastEmit_ISD_VECREDUCE_ADD_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 2688 switch (VT.SimpleTy) { 2689 case MVT::v16i8: return fastEmit_ISD_VECREDUCE_ADD_MVT_v16i8_r(RetVT, Op0, Op0IsKill); 2690 case MVT::v8i16: return fastEmit_ISD_VECREDUCE_ADD_MVT_v8i16_r(RetVT, Op0, Op0IsKill); 2691 case MVT::v4i32: return fastEmit_ISD_VECREDUCE_ADD_MVT_v4i32_r(RetVT, Op0, Op0IsKill); 2692 default: return 0; 2693 } 2694} 2695 2696// FastEmit functions for ISD::ZERO_EXTEND. 2697 2698unsigned fastEmit_ISD_ZERO_EXTEND_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2699 if (RetVT.SimpleTy != MVT::v8i16) 2700 return 0; 2701 if ((Subtarget->hasNEON())) { 2702 return fastEmitInst_r(ARM::VMOVLuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill); 2703 } 2704 return 0; 2705} 2706 2707unsigned fastEmit_ISD_ZERO_EXTEND_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2708 if (RetVT.SimpleTy != MVT::v4i32) 2709 return 0; 2710 if ((Subtarget->hasNEON())) { 2711 return fastEmitInst_r(ARM::VMOVLuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill); 2712 } 2713 return 0; 2714} 2715 2716unsigned fastEmit_ISD_ZERO_EXTEND_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 2717 if (RetVT.SimpleTy != MVT::v2i64) 2718 return 0; 2719 if ((Subtarget->hasNEON())) { 2720 return fastEmitInst_r(ARM::VMOVLuv2i64, &ARM::QPRRegClass, Op0, Op0IsKill); 2721 } 2722 return 0; 2723} 2724 2725unsigned fastEmit_ISD_ZERO_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 2726 switch (VT.SimpleTy) { 2727 case MVT::v8i8: return fastEmit_ISD_ZERO_EXTEND_MVT_v8i8_r(RetVT, Op0, Op0IsKill); 2728 case MVT::v4i16: return fastEmit_ISD_ZERO_EXTEND_MVT_v4i16_r(RetVT, Op0, Op0IsKill); 2729 case MVT::v2i32: return fastEmit_ISD_ZERO_EXTEND_MVT_v2i32_r(RetVT, Op0, Op0IsKill); 2730 default: return 0; 2731 } 2732} 2733 2734// Top-level FastEmit function. 2735 2736unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill) override { 2737 switch (Opcode) { 2738 case ARMISD::CALL: return fastEmit_ARMISD_CALL_r(VT, RetVT, Op0, Op0IsKill); 2739 case ARMISD::CALL_NOLINK: return fastEmit_ARMISD_CALL_NOLINK_r(VT, RetVT, Op0, Op0IsKill); 2740 case ARMISD::CALL_PRED: return fastEmit_ARMISD_CALL_PRED_r(VT, RetVT, Op0, Op0IsKill); 2741 case ARMISD::CMPFPEw0: return fastEmit_ARMISD_CMPFPEw0_r(VT, RetVT, Op0, Op0IsKill); 2742 case ARMISD::CMPFPw0: return fastEmit_ARMISD_CMPFPw0_r(VT, RetVT, Op0, Op0IsKill); 2743 case ARMISD::RRX: return fastEmit_ARMISD_RRX_r(VT, RetVT, Op0, Op0IsKill); 2744 case ARMISD::SRA_FLAG: return fastEmit_ARMISD_SRA_FLAG_r(VT, RetVT, Op0, Op0IsKill); 2745 case ARMISD::SRL_FLAG: return fastEmit_ARMISD_SRL_FLAG_r(VT, RetVT, Op0, Op0IsKill); 2746 case ARMISD::TC_RETURN: return fastEmit_ARMISD_TC_RETURN_r(VT, RetVT, Op0, Op0IsKill); 2747 case ARMISD::VDUP: return fastEmit_ARMISD_VDUP_r(VT, RetVT, Op0, Op0IsKill); 2748 case ARMISD::VMOVSR: return fastEmit_ARMISD_VMOVSR_r(VT, RetVT, Op0, Op0IsKill); 2749 case ARMISD::VMOVhr: return fastEmit_ARMISD_VMOVhr_r(VT, RetVT, Op0, Op0IsKill); 2750 case ARMISD::VMOVrh: return fastEmit_ARMISD_VMOVrh_r(VT, RetVT, Op0, Op0IsKill); 2751 case ARMISD::VREV16: return fastEmit_ARMISD_VREV16_r(VT, RetVT, Op0, Op0IsKill); 2752 case ARMISD::VREV32: return fastEmit_ARMISD_VREV32_r(VT, RetVT, Op0, Op0IsKill); 2753 case ARMISD::VREV64: return fastEmit_ARMISD_VREV64_r(VT, RetVT, Op0, Op0IsKill); 2754 case ARMISD::WIN__DBZCHK: return fastEmit_ARMISD_WIN__DBZCHK_r(VT, RetVT, Op0, Op0IsKill); 2755 case ISD::ABS: return fastEmit_ISD_ABS_r(VT, RetVT, Op0, Op0IsKill); 2756 case ISD::ANY_EXTEND: return fastEmit_ISD_ANY_EXTEND_r(VT, RetVT, Op0, Op0IsKill); 2757 case ISD::BITCAST: return fastEmit_ISD_BITCAST_r(VT, RetVT, Op0, Op0IsKill); 2758 case ISD::BITREVERSE: return fastEmit_ISD_BITREVERSE_r(VT, RetVT, Op0, Op0IsKill); 2759 case ISD::BRIND: return fastEmit_ISD_BRIND_r(VT, RetVT, Op0, Op0IsKill); 2760 case ISD::BSWAP: return fastEmit_ISD_BSWAP_r(VT, RetVT, Op0, Op0IsKill); 2761 case ISD::CTLZ: return fastEmit_ISD_CTLZ_r(VT, RetVT, Op0, Op0IsKill); 2762 case ISD::CTPOP: return fastEmit_ISD_CTPOP_r(VT, RetVT, Op0, Op0IsKill); 2763 case ISD::FABS: return fastEmit_ISD_FABS_r(VT, RetVT, Op0, Op0IsKill); 2764 case ISD::FCEIL: return fastEmit_ISD_FCEIL_r(VT, RetVT, Op0, Op0IsKill); 2765 case ISD::FFLOOR: return fastEmit_ISD_FFLOOR_r(VT, RetVT, Op0, Op0IsKill); 2766 case ISD::FNEARBYINT: return fastEmit_ISD_FNEARBYINT_r(VT, RetVT, Op0, Op0IsKill); 2767 case ISD::FNEG: return fastEmit_ISD_FNEG_r(VT, RetVT, Op0, Op0IsKill); 2768 case ISD::FP_EXTEND: return fastEmit_ISD_FP_EXTEND_r(VT, RetVT, Op0, Op0IsKill); 2769 case ISD::FP_ROUND: return fastEmit_ISD_FP_ROUND_r(VT, RetVT, Op0, Op0IsKill); 2770 case ISD::FP_TO_SINT: return fastEmit_ISD_FP_TO_SINT_r(VT, RetVT, Op0, Op0IsKill); 2771 case ISD::FP_TO_UINT: return fastEmit_ISD_FP_TO_UINT_r(VT, RetVT, Op0, Op0IsKill); 2772 case ISD::FRINT: return fastEmit_ISD_FRINT_r(VT, RetVT, Op0, Op0IsKill); 2773 case ISD::FROUND: return fastEmit_ISD_FROUND_r(VT, RetVT, Op0, Op0IsKill); 2774 case ISD::FSQRT: return fastEmit_ISD_FSQRT_r(VT, RetVT, Op0, Op0IsKill); 2775 case ISD::FTRUNC: return fastEmit_ISD_FTRUNC_r(VT, RetVT, Op0, Op0IsKill); 2776 case ISD::SIGN_EXTEND: return fastEmit_ISD_SIGN_EXTEND_r(VT, RetVT, Op0, Op0IsKill); 2777 case ISD::SINT_TO_FP: return fastEmit_ISD_SINT_TO_FP_r(VT, RetVT, Op0, Op0IsKill); 2778 case ISD::TRUNCATE: return fastEmit_ISD_TRUNCATE_r(VT, RetVT, Op0, Op0IsKill); 2779 case ISD::UINT_TO_FP: return fastEmit_ISD_UINT_TO_FP_r(VT, RetVT, Op0, Op0IsKill); 2780 case ISD::VECREDUCE_ADD: return fastEmit_ISD_VECREDUCE_ADD_r(VT, RetVT, Op0, Op0IsKill); 2781 case ISD::ZERO_EXTEND: return fastEmit_ISD_ZERO_EXTEND_r(VT, RetVT, Op0, Op0IsKill); 2782 default: return 0; 2783 } 2784} 2785 2786// FastEmit functions for ARMISD::CMP. 2787 2788unsigned fastEmit_ARMISD_CMP_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2789 if (RetVT.SimpleTy != MVT::isVoid) 2790 return 0; 2791 if ((Subtarget->isThumb2())) { 2792 return fastEmitInst_rr(ARM::t2CMPrr, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2793 } 2794 if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) { 2795 return fastEmitInst_rr(ARM::tCMPr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2796 } 2797 if ((!Subtarget->isThumb())) { 2798 return fastEmitInst_rr(ARM::CMPrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2799 } 2800 return 0; 2801} 2802 2803unsigned fastEmit_ARMISD_CMP_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2804 switch (VT.SimpleTy) { 2805 case MVT::i32: return fastEmit_ARMISD_CMP_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2806 default: return 0; 2807 } 2808} 2809 2810// FastEmit functions for ARMISD::CMPFP. 2811 2812unsigned fastEmit_ARMISD_CMPFP_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2813 if (RetVT.SimpleTy != MVT::isVoid) 2814 return 0; 2815 if ((Subtarget->hasFullFP16())) { 2816 return fastEmitInst_rr(ARM::VCMPH, &ARM::HPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2817 } 2818 return 0; 2819} 2820 2821unsigned fastEmit_ARMISD_CMPFP_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2822 if (RetVT.SimpleTy != MVT::isVoid) 2823 return 0; 2824 if ((Subtarget->hasVFP2Base())) { 2825 return fastEmitInst_rr(ARM::VCMPS, &ARM::SPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2826 } 2827 return 0; 2828} 2829 2830unsigned fastEmit_ARMISD_CMPFP_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2831 if (RetVT.SimpleTy != MVT::isVoid) 2832 return 0; 2833 if ((Subtarget->hasFP64()) && (Subtarget->hasVFP2Base())) { 2834 return fastEmitInst_rr(ARM::VCMPD, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2835 } 2836 return 0; 2837} 2838 2839unsigned fastEmit_ARMISD_CMPFP_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2840 switch (VT.SimpleTy) { 2841 case MVT::f16: return fastEmit_ARMISD_CMPFP_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2842 case MVT::f32: return fastEmit_ARMISD_CMPFP_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2843 case MVT::f64: return fastEmit_ARMISD_CMPFP_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2844 default: return 0; 2845 } 2846} 2847 2848// FastEmit functions for ARMISD::CMPFPE. 2849 2850unsigned fastEmit_ARMISD_CMPFPE_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2851 if (RetVT.SimpleTy != MVT::isVoid) 2852 return 0; 2853 if ((Subtarget->hasFullFP16())) { 2854 return fastEmitInst_rr(ARM::VCMPEH, &ARM::HPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2855 } 2856 return 0; 2857} 2858 2859unsigned fastEmit_ARMISD_CMPFPE_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2860 if (RetVT.SimpleTy != MVT::isVoid) 2861 return 0; 2862 if ((Subtarget->hasVFP2Base())) { 2863 return fastEmitInst_rr(ARM::VCMPES, &ARM::SPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2864 } 2865 return 0; 2866} 2867 2868unsigned fastEmit_ARMISD_CMPFPE_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2869 if (RetVT.SimpleTy != MVT::isVoid) 2870 return 0; 2871 if ((Subtarget->hasFP64()) && (Subtarget->hasVFP2Base())) { 2872 return fastEmitInst_rr(ARM::VCMPED, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2873 } 2874 return 0; 2875} 2876 2877unsigned fastEmit_ARMISD_CMPFPE_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2878 switch (VT.SimpleTy) { 2879 case MVT::f16: return fastEmit_ARMISD_CMPFPE_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2880 case MVT::f32: return fastEmit_ARMISD_CMPFPE_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2881 case MVT::f64: return fastEmit_ARMISD_CMPFPE_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2882 default: return 0; 2883 } 2884} 2885 2886// FastEmit functions for ARMISD::CMPZ. 2887 2888unsigned fastEmit_ARMISD_CMPZ_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2889 if (RetVT.SimpleTy != MVT::isVoid) 2890 return 0; 2891 if ((Subtarget->isThumb2())) { 2892 return fastEmitInst_rr(ARM::t2CMPrr, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2893 } 2894 if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) { 2895 return fastEmitInst_rr(ARM::tCMPr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2896 } 2897 if ((!Subtarget->isThumb())) { 2898 return fastEmitInst_rr(ARM::CMPrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2899 } 2900 return 0; 2901} 2902 2903unsigned fastEmit_ARMISD_CMPZ_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2904 switch (VT.SimpleTy) { 2905 case MVT::i32: return fastEmit_ARMISD_CMPZ_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2906 default: return 0; 2907 } 2908} 2909 2910// FastEmit functions for ARMISD::EH_SJLJ_LONGJMP. 2911 2912unsigned fastEmit_ARMISD_EH_SJLJ_LONGJMP_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2913 if (RetVT.SimpleTy != MVT::isVoid) 2914 return 0; 2915 if ((Subtarget->isThumb()) && (Subtarget->isTargetWindows())) { 2916 return fastEmitInst_rr(ARM::tInt_WIN_eh_sjlj_longjmp, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2917 } 2918 if ((!Subtarget->isTargetWindows()) && (Subtarget->isThumb())) { 2919 return fastEmitInst_rr(ARM::tInt_eh_sjlj_longjmp, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2920 } 2921 if ((!Subtarget->isThumb())) { 2922 return fastEmitInst_rr(ARM::Int_eh_sjlj_longjmp, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2923 } 2924 return 0; 2925} 2926 2927unsigned fastEmit_ARMISD_EH_SJLJ_LONGJMP_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2928 switch (VT.SimpleTy) { 2929 case MVT::i32: return fastEmit_ARMISD_EH_SJLJ_LONGJMP_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2930 default: return 0; 2931 } 2932} 2933 2934// FastEmit functions for ARMISD::EH_SJLJ_SETJMP. 2935 2936unsigned fastEmit_ARMISD_EH_SJLJ_SETJMP_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2937 if (RetVT.SimpleTy != MVT::i32) 2938 return 0; 2939 if ((Subtarget->isThumb2()) && (!Subtarget->hasVFP2Base())) { 2940 return fastEmitInst_rr(ARM::t2Int_eh_sjlj_setjmp_nofp, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2941 } 2942 if ((Subtarget->hasVFP2Base()) && (Subtarget->isThumb2())) { 2943 return fastEmitInst_rr(ARM::t2Int_eh_sjlj_setjmp, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2944 } 2945 if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) { 2946 return fastEmitInst_rr(ARM::tInt_eh_sjlj_setjmp, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2947 } 2948 if ((!Subtarget->isThumb()) && (!Subtarget->hasVFP2Base())) { 2949 return fastEmitInst_rr(ARM::Int_eh_sjlj_setjmp_nofp, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2950 } 2951 if ((Subtarget->hasVFP2Base()) && (!Subtarget->isThumb())) { 2952 return fastEmitInst_rr(ARM::Int_eh_sjlj_setjmp, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2953 } 2954 return 0; 2955} 2956 2957unsigned fastEmit_ARMISD_EH_SJLJ_SETJMP_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2958 switch (VT.SimpleTy) { 2959 case MVT::i32: return fastEmit_ARMISD_EH_SJLJ_SETJMP_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2960 default: return 0; 2961 } 2962} 2963 2964// FastEmit functions for ARMISD::QADD16b. 2965 2966unsigned fastEmit_ARMISD_QADD16b_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2967 if (RetVT.SimpleTy != MVT::i32) 2968 return 0; 2969 if ((Subtarget->hasDSP()) && (Subtarget->isThumb2())) { 2970 return fastEmitInst_rr(ARM::t2QADD16, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2971 } 2972 if ((Subtarget->hasV6Ops()) && (!Subtarget->isThumb())) { 2973 return fastEmitInst_rr(ARM::QADD16, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2974 } 2975 return 0; 2976} 2977 2978unsigned fastEmit_ARMISD_QADD16b_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2979 switch (VT.SimpleTy) { 2980 case MVT::i32: return fastEmit_ARMISD_QADD16b_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2981 default: return 0; 2982 } 2983} 2984 2985// FastEmit functions for ARMISD::QADD8b. 2986 2987unsigned fastEmit_ARMISD_QADD8b_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2988 if (RetVT.SimpleTy != MVT::i32) 2989 return 0; 2990 if ((Subtarget->hasDSP()) && (Subtarget->isThumb2())) { 2991 return fastEmitInst_rr(ARM::t2QADD8, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2992 } 2993 if ((Subtarget->hasV6Ops()) && (!Subtarget->isThumb())) { 2994 return fastEmitInst_rr(ARM::QADD8, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2995 } 2996 return 0; 2997} 2998 2999unsigned fastEmit_ARMISD_QADD8b_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3000 switch (VT.SimpleTy) { 3001 case MVT::i32: return fastEmit_ARMISD_QADD8b_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3002 default: return 0; 3003 } 3004} 3005 3006// FastEmit functions for ARMISD::QSUB16b. 3007 3008unsigned fastEmit_ARMISD_QSUB16b_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3009 if (RetVT.SimpleTy != MVT::i32) 3010 return 0; 3011 if ((Subtarget->hasDSP()) && (Subtarget->isThumb2())) { 3012 return fastEmitInst_rr(ARM::t2QSUB16, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3013 } 3014 if ((Subtarget->hasV6Ops()) && (!Subtarget->isThumb())) { 3015 return fastEmitInst_rr(ARM::QSUB16, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3016 } 3017 return 0; 3018} 3019 3020unsigned fastEmit_ARMISD_QSUB16b_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3021 switch (VT.SimpleTy) { 3022 case MVT::i32: return fastEmit_ARMISD_QSUB16b_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3023 default: return 0; 3024 } 3025} 3026 3027// FastEmit functions for ARMISD::QSUB8b. 3028 3029unsigned fastEmit_ARMISD_QSUB8b_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3030 if (RetVT.SimpleTy != MVT::i32) 3031 return 0; 3032 if ((Subtarget->hasDSP()) && (Subtarget->isThumb2())) { 3033 return fastEmitInst_rr(ARM::t2QSUB8, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3034 } 3035 if ((Subtarget->hasV6Ops()) && (!Subtarget->isThumb())) { 3036 return fastEmitInst_rr(ARM::QSUB8, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3037 } 3038 return 0; 3039} 3040 3041unsigned fastEmit_ARMISD_QSUB8b_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3042 switch (VT.SimpleTy) { 3043 case MVT::i32: return fastEmit_ARMISD_QSUB8b_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3044 default: return 0; 3045 } 3046} 3047 3048// FastEmit functions for ARMISD::SMULWB. 3049 3050unsigned fastEmit_ARMISD_SMULWB_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3051 if (RetVT.SimpleTy != MVT::i32) 3052 return 0; 3053 if ((Subtarget->hasDSP()) && (Subtarget->isThumb2())) { 3054 return fastEmitInst_rr(ARM::t2SMULWB, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3055 } 3056 if ((Subtarget->hasV5TEOps()) && (!Subtarget->isThumb())) { 3057 return fastEmitInst_rr(ARM::SMULWB, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3058 } 3059 return 0; 3060} 3061 3062unsigned fastEmit_ARMISD_SMULWB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3063 switch (VT.SimpleTy) { 3064 case MVT::i32: return fastEmit_ARMISD_SMULWB_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3065 default: return 0; 3066 } 3067} 3068 3069// FastEmit functions for ARMISD::SMULWT. 3070 3071unsigned fastEmit_ARMISD_SMULWT_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3072 if (RetVT.SimpleTy != MVT::i32) 3073 return 0; 3074 if ((Subtarget->hasDSP()) && (Subtarget->isThumb2())) { 3075 return fastEmitInst_rr(ARM::t2SMULWT, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3076 } 3077 if ((Subtarget->hasV5TEOps()) && (!Subtarget->isThumb())) { 3078 return fastEmitInst_rr(ARM::SMULWT, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3079 } 3080 return 0; 3081} 3082 3083unsigned fastEmit_ARMISD_SMULWT_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3084 switch (VT.SimpleTy) { 3085 case MVT::i32: return fastEmit_ARMISD_SMULWT_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3086 default: return 0; 3087 } 3088} 3089 3090// FastEmit functions for ARMISD::SUBS. 3091 3092unsigned fastEmit_ARMISD_SUBS_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3093 if (RetVT.SimpleTy != MVT::i32) 3094 return 0; 3095 if ((Subtarget->isThumb2())) { 3096 return fastEmitInst_rr(ARM::t2SUBSrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3097 } 3098 if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) { 3099 return fastEmitInst_rr(ARM::tSUBSrr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3100 } 3101 if ((!Subtarget->isThumb())) { 3102 return fastEmitInst_rr(ARM::SUBSrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3103 } 3104 return 0; 3105} 3106 3107unsigned fastEmit_ARMISD_SUBS_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3108 switch (VT.SimpleTy) { 3109 case MVT::i32: return fastEmit_ARMISD_SUBS_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3110 default: return 0; 3111 } 3112} 3113 3114// FastEmit functions for ARMISD::VMOVDRR. 3115 3116unsigned fastEmit_ARMISD_VMOVDRR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3117 if (RetVT.SimpleTy != MVT::f64) 3118 return 0; 3119 if ((Subtarget->hasFPRegs())) { 3120 return fastEmitInst_rr(ARM::VMOVDRR, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3121 } 3122 return 0; 3123} 3124 3125unsigned fastEmit_ARMISD_VMOVDRR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3126 switch (VT.SimpleTy) { 3127 case MVT::i32: return fastEmit_ARMISD_VMOVDRR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3128 default: return 0; 3129 } 3130} 3131 3132// FastEmit functions for ARMISD::VMULLs. 3133 3134unsigned fastEmit_ARMISD_VMULLs_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3135 if (RetVT.SimpleTy != MVT::v8i16) 3136 return 0; 3137 if ((Subtarget->hasNEON())) { 3138 return fastEmitInst_rr(ARM::VMULLsv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3139 } 3140 return 0; 3141} 3142 3143unsigned fastEmit_ARMISD_VMULLs_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3144 if (RetVT.SimpleTy != MVT::v4i32) 3145 return 0; 3146 if ((Subtarget->hasNEON())) { 3147 return fastEmitInst_rr(ARM::VMULLsv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3148 } 3149 return 0; 3150} 3151 3152unsigned fastEmit_ARMISD_VMULLs_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3153 if (RetVT.SimpleTy != MVT::v2i64) 3154 return 0; 3155 if ((Subtarget->hasNEON())) { 3156 return fastEmitInst_rr(ARM::VMULLsv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3157 } 3158 return 0; 3159} 3160 3161unsigned fastEmit_ARMISD_VMULLs_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3162 switch (VT.SimpleTy) { 3163 case MVT::v8i8: return fastEmit_ARMISD_VMULLs_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3164 case MVT::v4i16: return fastEmit_ARMISD_VMULLs_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3165 case MVT::v2i32: return fastEmit_ARMISD_VMULLs_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3166 default: return 0; 3167 } 3168} 3169 3170// FastEmit functions for ARMISD::VMULLu. 3171 3172unsigned fastEmit_ARMISD_VMULLu_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3173 if (RetVT.SimpleTy != MVT::v8i16) 3174 return 0; 3175 if ((Subtarget->hasNEON())) { 3176 return fastEmitInst_rr(ARM::VMULLuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3177 } 3178 return 0; 3179} 3180 3181unsigned fastEmit_ARMISD_VMULLu_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3182 if (RetVT.SimpleTy != MVT::v4i32) 3183 return 0; 3184 if ((Subtarget->hasNEON())) { 3185 return fastEmitInst_rr(ARM::VMULLuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3186 } 3187 return 0; 3188} 3189 3190unsigned fastEmit_ARMISD_VMULLu_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3191 if (RetVT.SimpleTy != MVT::v2i64) 3192 return 0; 3193 if ((Subtarget->hasNEON())) { 3194 return fastEmitInst_rr(ARM::VMULLuv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3195 } 3196 return 0; 3197} 3198 3199unsigned fastEmit_ARMISD_VMULLu_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3200 switch (VT.SimpleTy) { 3201 case MVT::v8i8: return fastEmit_ARMISD_VMULLu_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3202 case MVT::v4i16: return fastEmit_ARMISD_VMULLu_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3203 case MVT::v2i32: return fastEmit_ARMISD_VMULLu_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3204 default: return 0; 3205 } 3206} 3207 3208// FastEmit functions for ARMISD::VSHLs. 3209 3210unsigned fastEmit_ARMISD_VSHLs_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3211 if (RetVT.SimpleTy != MVT::v8i8) 3212 return 0; 3213 if ((Subtarget->hasNEON())) { 3214 return fastEmitInst_rr(ARM::VSHLsv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3215 } 3216 return 0; 3217} 3218 3219unsigned fastEmit_ARMISD_VSHLs_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3220 if (RetVT.SimpleTy != MVT::v16i8) 3221 return 0; 3222 if ((Subtarget->hasMVEIntegerOps())) { 3223 return fastEmitInst_rr(ARM::MVE_VSHL_by_vecs8, &ARM::MQPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3224 } 3225 if ((Subtarget->hasNEON())) { 3226 return fastEmitInst_rr(ARM::VSHLsv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3227 } 3228 return 0; 3229} 3230 3231unsigned fastEmit_ARMISD_VSHLs_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3232 if (RetVT.SimpleTy != MVT::v4i16) 3233 return 0; 3234 if ((Subtarget->hasNEON())) { 3235 return fastEmitInst_rr(ARM::VSHLsv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3236 } 3237 return 0; 3238} 3239 3240unsigned fastEmit_ARMISD_VSHLs_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3241 if (RetVT.SimpleTy != MVT::v8i16) 3242 return 0; 3243 if ((Subtarget->hasMVEIntegerOps())) { 3244 return fastEmitInst_rr(ARM::MVE_VSHL_by_vecs16, &ARM::MQPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3245 } 3246 if ((Subtarget->hasNEON())) { 3247 return fastEmitInst_rr(ARM::VSHLsv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3248 } 3249 return 0; 3250} 3251 3252unsigned fastEmit_ARMISD_VSHLs_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3253 if (RetVT.SimpleTy != MVT::v2i32) 3254 return 0; 3255 if ((Subtarget->hasNEON())) { 3256 return fastEmitInst_rr(ARM::VSHLsv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3257 } 3258 return 0; 3259} 3260 3261unsigned fastEmit_ARMISD_VSHLs_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3262 if (RetVT.SimpleTy != MVT::v4i32) 3263 return 0; 3264 if ((Subtarget->hasMVEIntegerOps())) { 3265 return fastEmitInst_rr(ARM::MVE_VSHL_by_vecs32, &ARM::MQPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3266 } 3267 if ((Subtarget->hasNEON())) { 3268 return fastEmitInst_rr(ARM::VSHLsv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3269 } 3270 return 0; 3271} 3272 3273unsigned fastEmit_ARMISD_VSHLs_MVT_v1i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3274 if (RetVT.SimpleTy != MVT::v1i64) 3275 return 0; 3276 if ((Subtarget->hasNEON())) { 3277 return fastEmitInst_rr(ARM::VSHLsv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3278 } 3279 return 0; 3280} 3281 3282unsigned fastEmit_ARMISD_VSHLs_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3283 if (RetVT.SimpleTy != MVT::v2i64) 3284 return 0; 3285 if ((Subtarget->hasNEON())) { 3286 return fastEmitInst_rr(ARM::VSHLsv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3287 } 3288 return 0; 3289} 3290 3291unsigned fastEmit_ARMISD_VSHLs_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3292 switch (VT.SimpleTy) { 3293 case MVT::v8i8: return fastEmit_ARMISD_VSHLs_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3294 case MVT::v16i8: return fastEmit_ARMISD_VSHLs_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3295 case MVT::v4i16: return fastEmit_ARMISD_VSHLs_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3296 case MVT::v8i16: return fastEmit_ARMISD_VSHLs_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3297 case MVT::v2i32: return fastEmit_ARMISD_VSHLs_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3298 case MVT::v4i32: return fastEmit_ARMISD_VSHLs_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3299 case MVT::v1i64: return fastEmit_ARMISD_VSHLs_MVT_v1i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3300 case MVT::v2i64: return fastEmit_ARMISD_VSHLs_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3301 default: return 0; 3302 } 3303} 3304 3305// FastEmit functions for ARMISD::VSHLu. 3306 3307unsigned fastEmit_ARMISD_VSHLu_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3308 if (RetVT.SimpleTy != MVT::v8i8) 3309 return 0; 3310 if ((Subtarget->hasNEON())) { 3311 return fastEmitInst_rr(ARM::VSHLuv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3312 } 3313 return 0; 3314} 3315 3316unsigned fastEmit_ARMISD_VSHLu_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3317 if (RetVT.SimpleTy != MVT::v16i8) 3318 return 0; 3319 if ((Subtarget->hasMVEIntegerOps())) { 3320 return fastEmitInst_rr(ARM::MVE_VSHL_by_vecu8, &ARM::MQPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3321 } 3322 if ((Subtarget->hasNEON())) { 3323 return fastEmitInst_rr(ARM::VSHLuv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3324 } 3325 return 0; 3326} 3327 3328unsigned fastEmit_ARMISD_VSHLu_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3329 if (RetVT.SimpleTy != MVT::v4i16) 3330 return 0; 3331 if ((Subtarget->hasNEON())) { 3332 return fastEmitInst_rr(ARM::VSHLuv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3333 } 3334 return 0; 3335} 3336 3337unsigned fastEmit_ARMISD_VSHLu_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3338 if (RetVT.SimpleTy != MVT::v8i16) 3339 return 0; 3340 if ((Subtarget->hasMVEIntegerOps())) { 3341 return fastEmitInst_rr(ARM::MVE_VSHL_by_vecu16, &ARM::MQPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3342 } 3343 if ((Subtarget->hasNEON())) { 3344 return fastEmitInst_rr(ARM::VSHLuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3345 } 3346 return 0; 3347} 3348 3349unsigned fastEmit_ARMISD_VSHLu_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3350 if (RetVT.SimpleTy != MVT::v2i32) 3351 return 0; 3352 if ((Subtarget->hasNEON())) { 3353 return fastEmitInst_rr(ARM::VSHLuv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3354 } 3355 return 0; 3356} 3357 3358unsigned fastEmit_ARMISD_VSHLu_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3359 if (RetVT.SimpleTy != MVT::v4i32) 3360 return 0; 3361 if ((Subtarget->hasMVEIntegerOps())) { 3362 return fastEmitInst_rr(ARM::MVE_VSHL_by_vecu32, &ARM::MQPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3363 } 3364 if ((Subtarget->hasNEON())) { 3365 return fastEmitInst_rr(ARM::VSHLuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3366 } 3367 return 0; 3368} 3369 3370unsigned fastEmit_ARMISD_VSHLu_MVT_v1i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3371 if (RetVT.SimpleTy != MVT::v1i64) 3372 return 0; 3373 if ((Subtarget->hasNEON())) { 3374 return fastEmitInst_rr(ARM::VSHLuv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3375 } 3376 return 0; 3377} 3378 3379unsigned fastEmit_ARMISD_VSHLu_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3380 if (RetVT.SimpleTy != MVT::v2i64) 3381 return 0; 3382 if ((Subtarget->hasNEON())) { 3383 return fastEmitInst_rr(ARM::VSHLuv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3384 } 3385 return 0; 3386} 3387 3388unsigned fastEmit_ARMISD_VSHLu_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3389 switch (VT.SimpleTy) { 3390 case MVT::v8i8: return fastEmit_ARMISD_VSHLu_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3391 case MVT::v16i8: return fastEmit_ARMISD_VSHLu_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3392 case MVT::v4i16: return fastEmit_ARMISD_VSHLu_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3393 case MVT::v8i16: return fastEmit_ARMISD_VSHLu_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3394 case MVT::v2i32: return fastEmit_ARMISD_VSHLu_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3395 case MVT::v4i32: return fastEmit_ARMISD_VSHLu_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3396 case MVT::v1i64: return fastEmit_ARMISD_VSHLu_MVT_v1i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3397 case MVT::v2i64: return fastEmit_ARMISD_VSHLu_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3398 default: return 0; 3399 } 3400} 3401 3402// FastEmit functions for ARMISD::VTBL1. 3403 3404unsigned fastEmit_ARMISD_VTBL1_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3405 if (RetVT.SimpleTy != MVT::v8i8) 3406 return 0; 3407 if ((Subtarget->hasNEON())) { 3408 return fastEmitInst_rr(ARM::VTBL1, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3409 } 3410 return 0; 3411} 3412 3413unsigned fastEmit_ARMISD_VTBL1_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3414 switch (VT.SimpleTy) { 3415 case MVT::v8i8: return fastEmit_ARMISD_VTBL1_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3416 default: return 0; 3417 } 3418} 3419 3420// FastEmit functions for ARMISD::VTST. 3421 3422unsigned fastEmit_ARMISD_VTST_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3423 if (RetVT.SimpleTy != MVT::v8i8) 3424 return 0; 3425 if ((Subtarget->hasNEON())) { 3426 return fastEmitInst_rr(ARM::VTSTv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3427 } 3428 return 0; 3429} 3430 3431unsigned fastEmit_ARMISD_VTST_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3432 if (RetVT.SimpleTy != MVT::v16i8) 3433 return 0; 3434 if ((Subtarget->hasNEON())) { 3435 return fastEmitInst_rr(ARM::VTSTv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3436 } 3437 return 0; 3438} 3439 3440unsigned fastEmit_ARMISD_VTST_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3441 if (RetVT.SimpleTy != MVT::v4i16) 3442 return 0; 3443 if ((Subtarget->hasNEON())) { 3444 return fastEmitInst_rr(ARM::VTSTv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3445 } 3446 return 0; 3447} 3448 3449unsigned fastEmit_ARMISD_VTST_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3450 if (RetVT.SimpleTy != MVT::v8i16) 3451 return 0; 3452 if ((Subtarget->hasNEON())) { 3453 return fastEmitInst_rr(ARM::VTSTv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3454 } 3455 return 0; 3456} 3457 3458unsigned fastEmit_ARMISD_VTST_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3459 if (RetVT.SimpleTy != MVT::v2i32) 3460 return 0; 3461 if ((Subtarget->hasNEON())) { 3462 return fastEmitInst_rr(ARM::VTSTv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3463 } 3464 return 0; 3465} 3466 3467unsigned fastEmit_ARMISD_VTST_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3468 if (RetVT.SimpleTy != MVT::v4i32) 3469 return 0; 3470 if ((Subtarget->hasNEON())) { 3471 return fastEmitInst_rr(ARM::VTSTv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3472 } 3473 return 0; 3474} 3475 3476unsigned fastEmit_ARMISD_VTST_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3477 switch (VT.SimpleTy) { 3478 case MVT::v8i8: return fastEmit_ARMISD_VTST_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3479 case MVT::v16i8: return fastEmit_ARMISD_VTST_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3480 case MVT::v4i16: return fastEmit_ARMISD_VTST_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3481 case MVT::v8i16: return fastEmit_ARMISD_VTST_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3482 case MVT::v2i32: return fastEmit_ARMISD_VTST_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3483 case MVT::v4i32: return fastEmit_ARMISD_VTST_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3484 default: return 0; 3485 } 3486} 3487 3488// FastEmit functions for ISD::ADD. 3489 3490unsigned fastEmit_ISD_ADD_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3491 if (RetVT.SimpleTy != MVT::i32) 3492 return 0; 3493 if ((Subtarget->isThumb2())) { 3494 return fastEmitInst_rr(ARM::t2ADDrr, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3495 } 3496 if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) { 3497 return fastEmitInst_rr(ARM::tADDrr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3498 } 3499 if ((!Subtarget->isThumb())) { 3500 return fastEmitInst_rr(ARM::ADDrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3501 } 3502 return 0; 3503} 3504 3505unsigned fastEmit_ISD_ADD_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3506 if (RetVT.SimpleTy != MVT::v8i8) 3507 return 0; 3508 if ((Subtarget->hasNEON())) { 3509 return fastEmitInst_rr(ARM::VADDv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3510 } 3511 return 0; 3512} 3513 3514unsigned fastEmit_ISD_ADD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3515 if (RetVT.SimpleTy != MVT::v16i8) 3516 return 0; 3517 if ((Subtarget->hasMVEIntegerOps())) { 3518 return fastEmitInst_rr(ARM::MVE_VADDi8, &ARM::MQPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3519 } 3520 if ((Subtarget->hasNEON())) { 3521 return fastEmitInst_rr(ARM::VADDv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3522 } 3523 return 0; 3524} 3525 3526unsigned fastEmit_ISD_ADD_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3527 if (RetVT.SimpleTy != MVT::v4i16) 3528 return 0; 3529 if ((Subtarget->hasNEON())) { 3530 return fastEmitInst_rr(ARM::VADDv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3531 } 3532 return 0; 3533} 3534 3535unsigned fastEmit_ISD_ADD_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3536 if (RetVT.SimpleTy != MVT::v8i16) 3537 return 0; 3538 if ((Subtarget->hasMVEIntegerOps())) { 3539 return fastEmitInst_rr(ARM::MVE_VADDi16, &ARM::MQPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3540 } 3541 if ((Subtarget->hasNEON())) { 3542 return fastEmitInst_rr(ARM::VADDv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3543 } 3544 return 0; 3545} 3546 3547unsigned fastEmit_ISD_ADD_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3548 if (RetVT.SimpleTy != MVT::v2i32) 3549 return 0; 3550 if ((Subtarget->hasNEON())) { 3551 return fastEmitInst_rr(ARM::VADDv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3552 } 3553 return 0; 3554} 3555 3556unsigned fastEmit_ISD_ADD_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3557 if (RetVT.SimpleTy != MVT::v4i32) 3558 return 0; 3559 if ((Subtarget->hasMVEIntegerOps())) { 3560 return fastEmitInst_rr(ARM::MVE_VADDi32, &ARM::MQPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3561 } 3562 if ((Subtarget->hasNEON())) { 3563 return fastEmitInst_rr(ARM::VADDv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3564 } 3565 return 0; 3566} 3567 3568unsigned fastEmit_ISD_ADD_MVT_v1i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3569 if (RetVT.SimpleTy != MVT::v1i64) 3570 return 0; 3571 if ((Subtarget->hasNEON())) { 3572 return fastEmitInst_rr(ARM::VADDv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3573 } 3574 return 0; 3575} 3576 3577unsigned fastEmit_ISD_ADD_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3578 if (RetVT.SimpleTy != MVT::v2i64) 3579 return 0; 3580 if ((Subtarget->hasNEON())) { 3581 return fastEmitInst_rr(ARM::VADDv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3582 } 3583 return 0; 3584} 3585 3586unsigned fastEmit_ISD_ADD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3587 switch (VT.SimpleTy) { 3588 case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3589 case MVT::v8i8: return fastEmit_ISD_ADD_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3590 case MVT::v16i8: return fastEmit_ISD_ADD_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3591 case MVT::v4i16: return fastEmit_ISD_ADD_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3592 case MVT::v8i16: return fastEmit_ISD_ADD_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3593 case MVT::v2i32: return fastEmit_ISD_ADD_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3594 case MVT::v4i32: return fastEmit_ISD_ADD_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3595 case MVT::v1i64: return fastEmit_ISD_ADD_MVT_v1i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3596 case MVT::v2i64: return fastEmit_ISD_ADD_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3597 default: return 0; 3598 } 3599} 3600 3601// FastEmit functions for ISD::AND. 3602 3603unsigned fastEmit_ISD_AND_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3604 if (RetVT.SimpleTy != MVT::i32) 3605 return 0; 3606 if ((Subtarget->isThumb2())) { 3607 return fastEmitInst_rr(ARM::t2ANDrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3608 } 3609 if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) { 3610 return fastEmitInst_rr(ARM::tAND, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3611 } 3612 if ((!Subtarget->isThumb())) { 3613 return fastEmitInst_rr(ARM::ANDrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3614 } 3615 return 0; 3616} 3617 3618unsigned fastEmit_ISD_AND_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3619 if (RetVT.SimpleTy != MVT::v16i8) 3620 return 0; 3621 if ((Subtarget->hasMVEIntegerOps())) { 3622 return fastEmitInst_rr(ARM::MVE_VAND, &ARM::MQPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3623 } 3624 return 0; 3625} 3626 3627unsigned fastEmit_ISD_AND_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3628 if (RetVT.SimpleTy != MVT::v8i16) 3629 return 0; 3630 if ((Subtarget->hasMVEIntegerOps())) { 3631 return fastEmitInst_rr(ARM::MVE_VAND, &ARM::MQPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3632 } 3633 return 0; 3634} 3635 3636unsigned fastEmit_ISD_AND_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3637 if (RetVT.SimpleTy != MVT::v2i32) 3638 return 0; 3639 if ((Subtarget->hasNEON())) { 3640 return fastEmitInst_rr(ARM::VANDd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3641 } 3642 return 0; 3643} 3644 3645unsigned fastEmit_ISD_AND_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3646 if (RetVT.SimpleTy != MVT::v4i32) 3647 return 0; 3648 if ((Subtarget->hasMVEIntegerOps())) { 3649 return fastEmitInst_rr(ARM::MVE_VAND, &ARM::MQPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3650 } 3651 if ((Subtarget->hasNEON())) { 3652 return fastEmitInst_rr(ARM::VANDq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3653 } 3654 return 0; 3655} 3656 3657unsigned fastEmit_ISD_AND_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3658 if (RetVT.SimpleTy != MVT::v2i64) 3659 return 0; 3660 if ((Subtarget->hasMVEIntegerOps())) { 3661 return fastEmitInst_rr(ARM::MVE_VAND, &ARM::MQPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3662 } 3663 return 0; 3664} 3665 3666unsigned fastEmit_ISD_AND_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3667 switch (VT.SimpleTy) { 3668 case MVT::i32: return fastEmit_ISD_AND_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3669 case MVT::v16i8: return fastEmit_ISD_AND_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3670 case MVT::v8i16: return fastEmit_ISD_AND_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3671 case MVT::v2i32: return fastEmit_ISD_AND_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3672 case MVT::v4i32: return fastEmit_ISD_AND_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3673 case MVT::v2i64: return fastEmit_ISD_AND_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3674 default: return 0; 3675 } 3676} 3677 3678// FastEmit functions for ISD::FADD. 3679 3680unsigned fastEmit_ISD_FADD_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3681 if (RetVT.SimpleTy != MVT::f16) 3682 return 0; 3683 if ((Subtarget->hasFullFP16())) { 3684 return fastEmitInst_rr(ARM::VADDH, &ARM::HPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3685 } 3686 return 0; 3687} 3688 3689unsigned fastEmit_ISD_FADD_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3690 if (RetVT.SimpleTy != MVT::f32) 3691 return 0; 3692 if ((!Subtarget->useNEONForSinglePrecisionFP()) && (Subtarget->hasVFP2Base())) { 3693 return fastEmitInst_rr(ARM::VADDS, &ARM::SPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3694 } 3695 return 0; 3696} 3697 3698unsigned fastEmit_ISD_FADD_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3699 if (RetVT.SimpleTy != MVT::f64) 3700 return 0; 3701 if ((Subtarget->hasFP64()) && (Subtarget->hasVFP2Base())) { 3702 return fastEmitInst_rr(ARM::VADDD, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3703 } 3704 return 0; 3705} 3706 3707unsigned fastEmit_ISD_FADD_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3708 if (RetVT.SimpleTy != MVT::v4f16) 3709 return 0; 3710 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 3711 return fastEmitInst_rr(ARM::VADDhd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3712 } 3713 return 0; 3714} 3715 3716unsigned fastEmit_ISD_FADD_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3717 if (RetVT.SimpleTy != MVT::v8f16) 3718 return 0; 3719 if ((Subtarget->hasMVEFloatOps())) { 3720 return fastEmitInst_rr(ARM::MVE_VADDf16, &ARM::MQPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3721 } 3722 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 3723 return fastEmitInst_rr(ARM::VADDhq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3724 } 3725 return 0; 3726} 3727 3728unsigned fastEmit_ISD_FADD_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3729 if (RetVT.SimpleTy != MVT::v2f32) 3730 return 0; 3731 if ((Subtarget->hasNEON())) { 3732 return fastEmitInst_rr(ARM::VADDfd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3733 } 3734 return 0; 3735} 3736 3737unsigned fastEmit_ISD_FADD_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3738 if (RetVT.SimpleTy != MVT::v4f32) 3739 return 0; 3740 if ((Subtarget->hasMVEFloatOps())) { 3741 return fastEmitInst_rr(ARM::MVE_VADDf32, &ARM::MQPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3742 } 3743 if ((Subtarget->hasNEON())) { 3744 return fastEmitInst_rr(ARM::VADDfq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3745 } 3746 return 0; 3747} 3748 3749unsigned fastEmit_ISD_FADD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3750 switch (VT.SimpleTy) { 3751 case MVT::f16: return fastEmit_ISD_FADD_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3752 case MVT::f32: return fastEmit_ISD_FADD_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3753 case MVT::f64: return fastEmit_ISD_FADD_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3754 case MVT::v4f16: return fastEmit_ISD_FADD_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3755 case MVT::v8f16: return fastEmit_ISD_FADD_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3756 case MVT::v2f32: return fastEmit_ISD_FADD_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3757 case MVT::v4f32: return fastEmit_ISD_FADD_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3758 default: return 0; 3759 } 3760} 3761 3762// FastEmit functions for ISD::FDIV. 3763 3764unsigned fastEmit_ISD_FDIV_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3765 if (RetVT.SimpleTy != MVT::f16) 3766 return 0; 3767 if ((Subtarget->hasFullFP16())) { 3768 return fastEmitInst_rr(ARM::VDIVH, &ARM::HPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3769 } 3770 return 0; 3771} 3772 3773unsigned fastEmit_ISD_FDIV_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3774 if (RetVT.SimpleTy != MVT::f32) 3775 return 0; 3776 if ((Subtarget->hasVFP2Base())) { 3777 return fastEmitInst_rr(ARM::VDIVS, &ARM::SPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3778 } 3779 return 0; 3780} 3781 3782unsigned fastEmit_ISD_FDIV_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3783 if (RetVT.SimpleTy != MVT::f64) 3784 return 0; 3785 if ((Subtarget->hasFP64()) && (Subtarget->hasVFP2Base())) { 3786 return fastEmitInst_rr(ARM::VDIVD, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3787 } 3788 return 0; 3789} 3790 3791unsigned fastEmit_ISD_FDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3792 switch (VT.SimpleTy) { 3793 case MVT::f16: return fastEmit_ISD_FDIV_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3794 case MVT::f32: return fastEmit_ISD_FDIV_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3795 case MVT::f64: return fastEmit_ISD_FDIV_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3796 default: return 0; 3797 } 3798} 3799 3800// FastEmit functions for ISD::FMAXIMUM. 3801 3802unsigned fastEmit_ISD_FMAXIMUM_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3803 if (RetVT.SimpleTy != MVT::v4f16) 3804 return 0; 3805 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 3806 return fastEmitInst_rr(ARM::VMAXhd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3807 } 3808 return 0; 3809} 3810 3811unsigned fastEmit_ISD_FMAXIMUM_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3812 if (RetVT.SimpleTy != MVT::v8f16) 3813 return 0; 3814 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 3815 return fastEmitInst_rr(ARM::VMAXhq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3816 } 3817 return 0; 3818} 3819 3820unsigned fastEmit_ISD_FMAXIMUM_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3821 if (RetVT.SimpleTy != MVT::v2f32) 3822 return 0; 3823 if ((Subtarget->hasNEON())) { 3824 return fastEmitInst_rr(ARM::VMAXfd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3825 } 3826 return 0; 3827} 3828 3829unsigned fastEmit_ISD_FMAXIMUM_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3830 if (RetVT.SimpleTy != MVT::v4f32) 3831 return 0; 3832 if ((Subtarget->hasNEON())) { 3833 return fastEmitInst_rr(ARM::VMAXfq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3834 } 3835 return 0; 3836} 3837 3838unsigned fastEmit_ISD_FMAXIMUM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3839 switch (VT.SimpleTy) { 3840 case MVT::v4f16: return fastEmit_ISD_FMAXIMUM_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3841 case MVT::v8f16: return fastEmit_ISD_FMAXIMUM_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3842 case MVT::v2f32: return fastEmit_ISD_FMAXIMUM_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3843 case MVT::v4f32: return fastEmit_ISD_FMAXIMUM_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3844 default: return 0; 3845 } 3846} 3847 3848// FastEmit functions for ISD::FMAXNUM. 3849 3850unsigned fastEmit_ISD_FMAXNUM_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3851 if (RetVT.SimpleTy != MVT::f16) 3852 return 0; 3853 if ((Subtarget->hasFullFP16())) { 3854 return fastEmitInst_rr(ARM::VFP_VMAXNMH, &ARM::HPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3855 } 3856 return 0; 3857} 3858 3859unsigned fastEmit_ISD_FMAXNUM_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3860 if (RetVT.SimpleTy != MVT::f32) 3861 return 0; 3862 if ((Subtarget->hasFPARMv8Base())) { 3863 return fastEmitInst_rr(ARM::VFP_VMAXNMS, &ARM::SPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3864 } 3865 return 0; 3866} 3867 3868unsigned fastEmit_ISD_FMAXNUM_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3869 if (RetVT.SimpleTy != MVT::f64) 3870 return 0; 3871 if ((Subtarget->hasFP64()) && (Subtarget->hasFPARMv8Base())) { 3872 return fastEmitInst_rr(ARM::VFP_VMAXNMD, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3873 } 3874 return 0; 3875} 3876 3877unsigned fastEmit_ISD_FMAXNUM_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3878 if (RetVT.SimpleTy != MVT::v4f16) 3879 return 0; 3880 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) { 3881 return fastEmitInst_rr(ARM::NEON_VMAXNMNDh, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3882 } 3883 return 0; 3884} 3885 3886unsigned fastEmit_ISD_FMAXNUM_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3887 if (RetVT.SimpleTy != MVT::v8f16) 3888 return 0; 3889 if ((Subtarget->hasMVEFloatOps())) { 3890 return fastEmitInst_rr(ARM::MVE_VMAXNMf16, &ARM::MQPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3891 } 3892 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) { 3893 return fastEmitInst_rr(ARM::NEON_VMAXNMNQh, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3894 } 3895 return 0; 3896} 3897 3898unsigned fastEmit_ISD_FMAXNUM_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3899 if (RetVT.SimpleTy != MVT::v2f32) 3900 return 0; 3901 if ((Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) { 3902 return fastEmitInst_rr(ARM::NEON_VMAXNMNDf, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3903 } 3904 return 0; 3905} 3906 3907unsigned fastEmit_ISD_FMAXNUM_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3908 if (RetVT.SimpleTy != MVT::v4f32) 3909 return 0; 3910 if ((Subtarget->hasMVEFloatOps())) { 3911 return fastEmitInst_rr(ARM::MVE_VMAXNMf32, &ARM::MQPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3912 } 3913 if ((Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) { 3914 return fastEmitInst_rr(ARM::NEON_VMAXNMNQf, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3915 } 3916 return 0; 3917} 3918 3919unsigned fastEmit_ISD_FMAXNUM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3920 switch (VT.SimpleTy) { 3921 case MVT::f16: return fastEmit_ISD_FMAXNUM_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3922 case MVT::f32: return fastEmit_ISD_FMAXNUM_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3923 case MVT::f64: return fastEmit_ISD_FMAXNUM_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3924 case MVT::v4f16: return fastEmit_ISD_FMAXNUM_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3925 case MVT::v8f16: return fastEmit_ISD_FMAXNUM_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3926 case MVT::v2f32: return fastEmit_ISD_FMAXNUM_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3927 case MVT::v4f32: return fastEmit_ISD_FMAXNUM_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3928 default: return 0; 3929 } 3930} 3931 3932// FastEmit functions for ISD::FMINIMUM. 3933 3934unsigned fastEmit_ISD_FMINIMUM_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3935 if (RetVT.SimpleTy != MVT::v4f16) 3936 return 0; 3937 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 3938 return fastEmitInst_rr(ARM::VMINhd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3939 } 3940 return 0; 3941} 3942 3943unsigned fastEmit_ISD_FMINIMUM_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3944 if (RetVT.SimpleTy != MVT::v8f16) 3945 return 0; 3946 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 3947 return fastEmitInst_rr(ARM::VMINhq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3948 } 3949 return 0; 3950} 3951 3952unsigned fastEmit_ISD_FMINIMUM_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3953 if (RetVT.SimpleTy != MVT::v2f32) 3954 return 0; 3955 if ((Subtarget->hasNEON())) { 3956 return fastEmitInst_rr(ARM::VMINfd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3957 } 3958 return 0; 3959} 3960 3961unsigned fastEmit_ISD_FMINIMUM_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3962 if (RetVT.SimpleTy != MVT::v4f32) 3963 return 0; 3964 if ((Subtarget->hasNEON())) { 3965 return fastEmitInst_rr(ARM::VMINfq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3966 } 3967 return 0; 3968} 3969 3970unsigned fastEmit_ISD_FMINIMUM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3971 switch (VT.SimpleTy) { 3972 case MVT::v4f16: return fastEmit_ISD_FMINIMUM_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3973 case MVT::v8f16: return fastEmit_ISD_FMINIMUM_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3974 case MVT::v2f32: return fastEmit_ISD_FMINIMUM_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3975 case MVT::v4f32: return fastEmit_ISD_FMINIMUM_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3976 default: return 0; 3977 } 3978} 3979 3980// FastEmit functions for ISD::FMINNUM. 3981 3982unsigned fastEmit_ISD_FMINNUM_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3983 if (RetVT.SimpleTy != MVT::f16) 3984 return 0; 3985 if ((Subtarget->hasFullFP16())) { 3986 return fastEmitInst_rr(ARM::VFP_VMINNMH, &ARM::HPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3987 } 3988 return 0; 3989} 3990 3991unsigned fastEmit_ISD_FMINNUM_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3992 if (RetVT.SimpleTy != MVT::f32) 3993 return 0; 3994 if ((Subtarget->hasFPARMv8Base())) { 3995 return fastEmitInst_rr(ARM::VFP_VMINNMS, &ARM::SPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3996 } 3997 return 0; 3998} 3999 4000unsigned fastEmit_ISD_FMINNUM_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4001 if (RetVT.SimpleTy != MVT::f64) 4002 return 0; 4003 if ((Subtarget->hasFP64()) && (Subtarget->hasFPARMv8Base())) { 4004 return fastEmitInst_rr(ARM::VFP_VMINNMD, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4005 } 4006 return 0; 4007} 4008 4009unsigned fastEmit_ISD_FMINNUM_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4010 if (RetVT.SimpleTy != MVT::v4f16) 4011 return 0; 4012 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) { 4013 return fastEmitInst_rr(ARM::NEON_VMINNMNDh, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4014 } 4015 return 0; 4016} 4017 4018unsigned fastEmit_ISD_FMINNUM_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4019 if (RetVT.SimpleTy != MVT::v8f16) 4020 return 0; 4021 if ((Subtarget->hasMVEFloatOps())) { 4022 return fastEmitInst_rr(ARM::MVE_VMINNMf16, &ARM::MQPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4023 } 4024 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) { 4025 return fastEmitInst_rr(ARM::NEON_VMINNMNQh, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4026 } 4027 return 0; 4028} 4029 4030unsigned fastEmit_ISD_FMINNUM_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4031 if (RetVT.SimpleTy != MVT::v2f32) 4032 return 0; 4033 if ((Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) { 4034 return fastEmitInst_rr(ARM::NEON_VMINNMNDf, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4035 } 4036 return 0; 4037} 4038 4039unsigned fastEmit_ISD_FMINNUM_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4040 if (RetVT.SimpleTy != MVT::v4f32) 4041 return 0; 4042 if ((Subtarget->hasMVEFloatOps())) { 4043 return fastEmitInst_rr(ARM::MVE_VMINNMf32, &ARM::MQPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4044 } 4045 if ((Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) { 4046 return fastEmitInst_rr(ARM::NEON_VMINNMNQf, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4047 } 4048 return 0; 4049} 4050 4051unsigned fastEmit_ISD_FMINNUM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4052 switch (VT.SimpleTy) { 4053 case MVT::f16: return fastEmit_ISD_FMINNUM_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4054 case MVT::f32: return fastEmit_ISD_FMINNUM_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4055 case MVT::f64: return fastEmit_ISD_FMINNUM_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4056 case MVT::v4f16: return fastEmit_ISD_FMINNUM_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4057 case MVT::v8f16: return fastEmit_ISD_FMINNUM_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4058 case MVT::v2f32: return fastEmit_ISD_FMINNUM_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4059 case MVT::v4f32: return fastEmit_ISD_FMINNUM_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4060 default: return 0; 4061 } 4062} 4063 4064// FastEmit functions for ISD::FMUL. 4065 4066unsigned fastEmit_ISD_FMUL_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4067 if (RetVT.SimpleTy != MVT::f16) 4068 return 0; 4069 if ((Subtarget->hasFullFP16())) { 4070 return fastEmitInst_rr(ARM::VMULH, &ARM::HPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4071 } 4072 return 0; 4073} 4074 4075unsigned fastEmit_ISD_FMUL_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4076 if (RetVT.SimpleTy != MVT::f32) 4077 return 0; 4078 if ((!Subtarget->useNEONForSinglePrecisionFP()) && (Subtarget->hasVFP2Base())) { 4079 return fastEmitInst_rr(ARM::VMULS, &ARM::SPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4080 } 4081 return 0; 4082} 4083 4084unsigned fastEmit_ISD_FMUL_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4085 if (RetVT.SimpleTy != MVT::f64) 4086 return 0; 4087 if ((Subtarget->hasFP64()) && (Subtarget->hasVFP2Base())) { 4088 return fastEmitInst_rr(ARM::VMULD, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4089 } 4090 return 0; 4091} 4092 4093unsigned fastEmit_ISD_FMUL_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4094 if (RetVT.SimpleTy != MVT::v4f16) 4095 return 0; 4096 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 4097 return fastEmitInst_rr(ARM::VMULhd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4098 } 4099 return 0; 4100} 4101 4102unsigned fastEmit_ISD_FMUL_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4103 if (RetVT.SimpleTy != MVT::v8f16) 4104 return 0; 4105 if ((Subtarget->hasMVEFloatOps())) { 4106 return fastEmitInst_rr(ARM::MVE_VMULf16, &ARM::MQPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4107 } 4108 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 4109 return fastEmitInst_rr(ARM::VMULhq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4110 } 4111 return 0; 4112} 4113 4114unsigned fastEmit_ISD_FMUL_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4115 if (RetVT.SimpleTy != MVT::v2f32) 4116 return 0; 4117 if ((Subtarget->hasNEON())) { 4118 return fastEmitInst_rr(ARM::VMULfd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4119 } 4120 return 0; 4121} 4122 4123unsigned fastEmit_ISD_FMUL_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4124 if (RetVT.SimpleTy != MVT::v4f32) 4125 return 0; 4126 if ((Subtarget->hasMVEFloatOps())) { 4127 return fastEmitInst_rr(ARM::MVE_VMULf32, &ARM::MQPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4128 } 4129 if ((Subtarget->hasNEON())) { 4130 return fastEmitInst_rr(ARM::VMULfq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4131 } 4132 return 0; 4133} 4134 4135unsigned fastEmit_ISD_FMUL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4136 switch (VT.SimpleTy) { 4137 case MVT::f16: return fastEmit_ISD_FMUL_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4138 case MVT::f32: return fastEmit_ISD_FMUL_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4139 case MVT::f64: return fastEmit_ISD_FMUL_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4140 case MVT::v4f16: return fastEmit_ISD_FMUL_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4141 case MVT::v8f16: return fastEmit_ISD_FMUL_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4142 case MVT::v2f32: return fastEmit_ISD_FMUL_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4143 case MVT::v4f32: return fastEmit_ISD_FMUL_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4144 default: return 0; 4145 } 4146} 4147 4148// FastEmit functions for ISD::FSUB. 4149 4150unsigned fastEmit_ISD_FSUB_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4151 if (RetVT.SimpleTy != MVT::f16) 4152 return 0; 4153 if ((Subtarget->hasFullFP16())) { 4154 return fastEmitInst_rr(ARM::VSUBH, &ARM::HPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4155 } 4156 return 0; 4157} 4158 4159unsigned fastEmit_ISD_FSUB_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4160 if (RetVT.SimpleTy != MVT::f32) 4161 return 0; 4162 if ((!Subtarget->useNEONForSinglePrecisionFP()) && (Subtarget->hasVFP2Base())) { 4163 return fastEmitInst_rr(ARM::VSUBS, &ARM::SPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4164 } 4165 return 0; 4166} 4167 4168unsigned fastEmit_ISD_FSUB_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4169 if (RetVT.SimpleTy != MVT::f64) 4170 return 0; 4171 if ((Subtarget->hasFP64()) && (Subtarget->hasVFP2Base())) { 4172 return fastEmitInst_rr(ARM::VSUBD, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4173 } 4174 return 0; 4175} 4176 4177unsigned fastEmit_ISD_FSUB_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4178 if (RetVT.SimpleTy != MVT::v4f16) 4179 return 0; 4180 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 4181 return fastEmitInst_rr(ARM::VSUBhd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4182 } 4183 return 0; 4184} 4185 4186unsigned fastEmit_ISD_FSUB_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4187 if (RetVT.SimpleTy != MVT::v8f16) 4188 return 0; 4189 if ((Subtarget->hasMVEFloatOps())) { 4190 return fastEmitInst_rr(ARM::MVE_VSUBf16, &ARM::MQPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4191 } 4192 if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) { 4193 return fastEmitInst_rr(ARM::VSUBhq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4194 } 4195 return 0; 4196} 4197 4198unsigned fastEmit_ISD_FSUB_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4199 if (RetVT.SimpleTy != MVT::v2f32) 4200 return 0; 4201 if ((Subtarget->hasNEON())) { 4202 return fastEmitInst_rr(ARM::VSUBfd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4203 } 4204 return 0; 4205} 4206 4207unsigned fastEmit_ISD_FSUB_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4208 if (RetVT.SimpleTy != MVT::v4f32) 4209 return 0; 4210 if ((Subtarget->hasMVEFloatOps())) { 4211 return fastEmitInst_rr(ARM::MVE_VSUBf32, &ARM::MQPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4212 } 4213 if ((Subtarget->hasNEON())) { 4214 return fastEmitInst_rr(ARM::VSUBfq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4215 } 4216 return 0; 4217} 4218 4219unsigned fastEmit_ISD_FSUB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4220 switch (VT.SimpleTy) { 4221 case MVT::f16: return fastEmit_ISD_FSUB_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4222 case MVT::f32: return fastEmit_ISD_FSUB_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4223 case MVT::f64: return fastEmit_ISD_FSUB_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4224 case MVT::v4f16: return fastEmit_ISD_FSUB_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4225 case MVT::v8f16: return fastEmit_ISD_FSUB_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4226 case MVT::v2f32: return fastEmit_ISD_FSUB_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4227 case MVT::v4f32: return fastEmit_ISD_FSUB_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4228 default: return 0; 4229 } 4230} 4231 4232// FastEmit functions for ISD::MUL. 4233 4234unsigned fastEmit_ISD_MUL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4235 if (RetVT.SimpleTy != MVT::i32) 4236 return 0; 4237 if ((Subtarget->isThumb2())) { 4238 return fastEmitInst_rr(ARM::t2MUL, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4239 } 4240 if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) { 4241 return fastEmitInst_rr(ARM::tMUL, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4242 } 4243 if ((!Subtarget->isThumb()) && (!Subtarget->hasV6Ops()) && (Subtarget->useMulOps())) { 4244 return fastEmitInst_rr(ARM::MULv5, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4245 } 4246 if ((Subtarget->hasV6Ops()) && (!Subtarget->isThumb())) { 4247 return fastEmitInst_rr(ARM::MUL, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4248 } 4249 return 0; 4250} 4251 4252unsigned fastEmit_ISD_MUL_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4253 if (RetVT.SimpleTy != MVT::v8i8) 4254 return 0; 4255 if ((Subtarget->hasNEON())) { 4256 return fastEmitInst_rr(ARM::VMULv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4257 } 4258 return 0; 4259} 4260 4261unsigned fastEmit_ISD_MUL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4262 if (RetVT.SimpleTy != MVT::v16i8) 4263 return 0; 4264 if ((Subtarget->hasMVEIntegerOps())) { 4265 return fastEmitInst_rr(ARM::MVE_VMULi8, &ARM::MQPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4266 } 4267 if ((Subtarget->hasNEON())) { 4268 return fastEmitInst_rr(ARM::VMULv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4269 } 4270 return 0; 4271} 4272 4273unsigned fastEmit_ISD_MUL_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4274 if (RetVT.SimpleTy != MVT::v4i16) 4275 return 0; 4276 if ((Subtarget->hasNEON())) { 4277 return fastEmitInst_rr(ARM::VMULv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4278 } 4279 return 0; 4280} 4281 4282unsigned fastEmit_ISD_MUL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4283 if (RetVT.SimpleTy != MVT::v8i16) 4284 return 0; 4285 if ((Subtarget->hasMVEIntegerOps())) { 4286 return fastEmitInst_rr(ARM::MVE_VMULi16, &ARM::MQPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4287 } 4288 if ((Subtarget->hasNEON())) { 4289 return fastEmitInst_rr(ARM::VMULv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4290 } 4291 return 0; 4292} 4293 4294unsigned fastEmit_ISD_MUL_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4295 if (RetVT.SimpleTy != MVT::v2i32) 4296 return 0; 4297 if ((Subtarget->hasNEON())) { 4298 return fastEmitInst_rr(ARM::VMULv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4299 } 4300 return 0; 4301} 4302 4303unsigned fastEmit_ISD_MUL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4304 if (RetVT.SimpleTy != MVT::v4i32) 4305 return 0; 4306 if ((Subtarget->hasMVEIntegerOps())) { 4307 return fastEmitInst_rr(ARM::MVE_VMULi32, &ARM::MQPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4308 } 4309 if ((Subtarget->hasNEON())) { 4310 return fastEmitInst_rr(ARM::VMULv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4311 } 4312 return 0; 4313} 4314 4315unsigned fastEmit_ISD_MUL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4316 switch (VT.SimpleTy) { 4317 case MVT::i32: return fastEmit_ISD_MUL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4318 case MVT::v8i8: return fastEmit_ISD_MUL_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4319 case MVT::v16i8: return fastEmit_ISD_MUL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4320 case MVT::v4i16: return fastEmit_ISD_MUL_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4321 case MVT::v8i16: return fastEmit_ISD_MUL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4322 case MVT::v2i32: return fastEmit_ISD_MUL_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4323 case MVT::v4i32: return fastEmit_ISD_MUL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4324 default: return 0; 4325 } 4326} 4327 4328// FastEmit functions for ISD::MULHS. 4329 4330unsigned fastEmit_ISD_MULHS_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4331 if (RetVT.SimpleTy != MVT::i32) 4332 return 0; 4333 if ((Subtarget->hasDSP()) && (Subtarget->isThumb2())) { 4334 return fastEmitInst_rr(ARM::t2SMMUL, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4335 } 4336 if ((Subtarget->hasV6Ops()) && (!Subtarget->isThumb())) { 4337 return fastEmitInst_rr(ARM::SMMUL, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4338 } 4339 return 0; 4340} 4341 4342unsigned fastEmit_ISD_MULHS_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4343 switch (VT.SimpleTy) { 4344 case MVT::i32: return fastEmit_ISD_MULHS_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4345 default: return 0; 4346 } 4347} 4348 4349// FastEmit functions for ISD::OR. 4350 4351unsigned fastEmit_ISD_OR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4352 if (RetVT.SimpleTy != MVT::i32) 4353 return 0; 4354 if ((Subtarget->isThumb2())) { 4355 return fastEmitInst_rr(ARM::t2ORRrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4356 } 4357 if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) { 4358 return fastEmitInst_rr(ARM::tORR, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4359 } 4360 if ((!Subtarget->isThumb())) { 4361 return fastEmitInst_rr(ARM::ORRrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4362 } 4363 return 0; 4364} 4365 4366unsigned fastEmit_ISD_OR_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4367 if (RetVT.SimpleTy != MVT::v16i8) 4368 return 0; 4369 if ((Subtarget->hasMVEIntegerOps())) { 4370 return fastEmitInst_rr(ARM::MVE_VORR, &ARM::MQPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4371 } 4372 return 0; 4373} 4374 4375unsigned fastEmit_ISD_OR_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4376 if (RetVT.SimpleTy != MVT::v8i16) 4377 return 0; 4378 if ((Subtarget->hasMVEIntegerOps())) { 4379 return fastEmitInst_rr(ARM::MVE_VORR, &ARM::MQPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4380 } 4381 return 0; 4382} 4383 4384unsigned fastEmit_ISD_OR_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4385 if (RetVT.SimpleTy != MVT::v2i32) 4386 return 0; 4387 if ((Subtarget->hasNEON())) { 4388 return fastEmitInst_rr(ARM::VORRd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4389 } 4390 return 0; 4391} 4392 4393unsigned fastEmit_ISD_OR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4394 if (RetVT.SimpleTy != MVT::v4i32) 4395 return 0; 4396 if ((Subtarget->hasMVEIntegerOps())) { 4397 return fastEmitInst_rr(ARM::MVE_VORR, &ARM::MQPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4398 } 4399 if ((Subtarget->hasNEON())) { 4400 return fastEmitInst_rr(ARM::VORRq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4401 } 4402 return 0; 4403} 4404 4405unsigned fastEmit_ISD_OR_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4406 if (RetVT.SimpleTy != MVT::v2i64) 4407 return 0; 4408 if ((Subtarget->hasMVEIntegerOps())) { 4409 return fastEmitInst_rr(ARM::MVE_VORR, &ARM::MQPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4410 } 4411 return 0; 4412} 4413 4414unsigned fastEmit_ISD_OR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4415 switch (VT.SimpleTy) { 4416 case MVT::i32: return fastEmit_ISD_OR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4417 case MVT::v16i8: return fastEmit_ISD_OR_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4418 case MVT::v8i16: return fastEmit_ISD_OR_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4419 case MVT::v2i32: return fastEmit_ISD_OR_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4420 case MVT::v4i32: return fastEmit_ISD_OR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4421 case MVT::v2i64: return fastEmit_ISD_OR_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4422 default: return 0; 4423 } 4424} 4425 4426// FastEmit functions for ISD::ROTR. 4427 4428unsigned fastEmit_ISD_ROTR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4429 if (RetVT.SimpleTy != MVT::i32) 4430 return 0; 4431 if ((Subtarget->isThumb2())) { 4432 return fastEmitInst_rr(ARM::t2RORrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4433 } 4434 if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) { 4435 return fastEmitInst_rr(ARM::tROR, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4436 } 4437 return 0; 4438} 4439 4440unsigned fastEmit_ISD_ROTR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4441 switch (VT.SimpleTy) { 4442 case MVT::i32: return fastEmit_ISD_ROTR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4443 default: return 0; 4444 } 4445} 4446 4447// FastEmit functions for ISD::SADDSAT. 4448 4449unsigned fastEmit_ISD_SADDSAT_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4450 if (RetVT.SimpleTy != MVT::i32) 4451 return 0; 4452 if ((Subtarget->hasDSP()) && (Subtarget->isThumb2())) { 4453 return fastEmitInst_rr(ARM::t2QADD, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4454 } 4455 if ((Subtarget->hasV5TEOps()) && (!Subtarget->isThumb())) { 4456 return fastEmitInst_rr(ARM::QADD, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4457 } 4458 return 0; 4459} 4460 4461unsigned fastEmit_ISD_SADDSAT_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4462 if (RetVT.SimpleTy != MVT::v8i8) 4463 return 0; 4464 if ((Subtarget->hasNEON())) { 4465 return fastEmitInst_rr(ARM::VQADDsv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4466 } 4467 return 0; 4468} 4469 4470unsigned fastEmit_ISD_SADDSAT_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4471 if (RetVT.SimpleTy != MVT::v16i8) 4472 return 0; 4473 if ((Subtarget->hasMVEIntegerOps())) { 4474 return fastEmitInst_rr(ARM::MVE_VQADDs8, &ARM::MQPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4475 } 4476 if ((Subtarget->hasNEON())) { 4477 return fastEmitInst_rr(ARM::VQADDsv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4478 } 4479 return 0; 4480} 4481 4482unsigned fastEmit_ISD_SADDSAT_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4483 if (RetVT.SimpleTy != MVT::v4i16) 4484 return 0; 4485 if ((Subtarget->hasNEON())) { 4486 return fastEmitInst_rr(ARM::VQADDsv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4487 } 4488 return 0; 4489} 4490 4491unsigned fastEmit_ISD_SADDSAT_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4492 if (RetVT.SimpleTy != MVT::v8i16) 4493 return 0; 4494 if ((Subtarget->hasMVEIntegerOps())) { 4495 return fastEmitInst_rr(ARM::MVE_VQADDs16, &ARM::MQPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4496 } 4497 if ((Subtarget->hasNEON())) { 4498 return fastEmitInst_rr(ARM::VQADDsv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4499 } 4500 return 0; 4501} 4502 4503unsigned fastEmit_ISD_SADDSAT_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4504 if (RetVT.SimpleTy != MVT::v2i32) 4505 return 0; 4506 if ((Subtarget->hasNEON())) { 4507 return fastEmitInst_rr(ARM::VQADDsv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4508 } 4509 return 0; 4510} 4511 4512unsigned fastEmit_ISD_SADDSAT_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4513 if (RetVT.SimpleTy != MVT::v4i32) 4514 return 0; 4515 if ((Subtarget->hasMVEIntegerOps())) { 4516 return fastEmitInst_rr(ARM::MVE_VQADDs32, &ARM::MQPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4517 } 4518 if ((Subtarget->hasNEON())) { 4519 return fastEmitInst_rr(ARM::VQADDsv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4520 } 4521 return 0; 4522} 4523 4524unsigned fastEmit_ISD_SADDSAT_MVT_v1i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4525 if (RetVT.SimpleTy != MVT::v1i64) 4526 return 0; 4527 if ((Subtarget->hasNEON())) { 4528 return fastEmitInst_rr(ARM::VQADDsv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4529 } 4530 return 0; 4531} 4532 4533unsigned fastEmit_ISD_SADDSAT_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4534 if (RetVT.SimpleTy != MVT::v2i64) 4535 return 0; 4536 if ((Subtarget->hasNEON())) { 4537 return fastEmitInst_rr(ARM::VQADDsv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4538 } 4539 return 0; 4540} 4541 4542unsigned fastEmit_ISD_SADDSAT_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4543 switch (VT.SimpleTy) { 4544 case MVT::i32: return fastEmit_ISD_SADDSAT_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4545 case MVT::v8i8: return fastEmit_ISD_SADDSAT_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4546 case MVT::v16i8: return fastEmit_ISD_SADDSAT_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4547 case MVT::v4i16: return fastEmit_ISD_SADDSAT_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4548 case MVT::v8i16: return fastEmit_ISD_SADDSAT_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4549 case MVT::v2i32: return fastEmit_ISD_SADDSAT_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4550 case MVT::v4i32: return fastEmit_ISD_SADDSAT_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4551 case MVT::v1i64: return fastEmit_ISD_SADDSAT_MVT_v1i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4552 case MVT::v2i64: return fastEmit_ISD_SADDSAT_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4553 default: return 0; 4554 } 4555} 4556 4557// FastEmit functions for ISD::SDIV. 4558 4559unsigned fastEmit_ISD_SDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4560 if (RetVT.SimpleTy != MVT::i32) 4561 return 0; 4562 if ((Subtarget->hasDivideInThumbMode()) && (Subtarget->hasV8MBaselineOps()) && (Subtarget->isThumb())) { 4563 return fastEmitInst_rr(ARM::t2SDIV, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4564 } 4565 if ((Subtarget->hasDivideInARMMode()) && (!Subtarget->isThumb())) { 4566 return fastEmitInst_rr(ARM::SDIV, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4567 } 4568 return 0; 4569} 4570 4571unsigned fastEmit_ISD_SDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4572 switch (VT.SimpleTy) { 4573 case MVT::i32: return fastEmit_ISD_SDIV_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4574 default: return 0; 4575 } 4576} 4577 4578// FastEmit functions for ISD::SHL. 4579 4580unsigned fastEmit_ISD_SHL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4581 if (RetVT.SimpleTy != MVT::i32) 4582 return 0; 4583 if ((Subtarget->isThumb2())) { 4584 return fastEmitInst_rr(ARM::t2LSLrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4585 } 4586 if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) { 4587 return fastEmitInst_rr(ARM::tLSLrr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4588 } 4589 return 0; 4590} 4591 4592unsigned fastEmit_ISD_SHL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4593 switch (VT.SimpleTy) { 4594 case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4595 default: return 0; 4596 } 4597} 4598 4599// FastEmit functions for ISD::SMAX. 4600 4601unsigned fastEmit_ISD_SMAX_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4602 if (RetVT.SimpleTy != MVT::v8i8) 4603 return 0; 4604 if ((Subtarget->hasNEON())) { 4605 return fastEmitInst_rr(ARM::VMAXsv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4606 } 4607 return 0; 4608} 4609 4610unsigned fastEmit_ISD_SMAX_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4611 if (RetVT.SimpleTy != MVT::v16i8) 4612 return 0; 4613 if ((Subtarget->hasMVEIntegerOps())) { 4614 return fastEmitInst_rr(ARM::MVE_VMAXs8, &ARM::MQPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4615 } 4616 if ((Subtarget->hasNEON())) { 4617 return fastEmitInst_rr(ARM::VMAXsv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4618 } 4619 return 0; 4620} 4621 4622unsigned fastEmit_ISD_SMAX_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4623 if (RetVT.SimpleTy != MVT::v4i16) 4624 return 0; 4625 if ((Subtarget->hasNEON())) { 4626 return fastEmitInst_rr(ARM::VMAXsv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4627 } 4628 return 0; 4629} 4630 4631unsigned fastEmit_ISD_SMAX_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4632 if (RetVT.SimpleTy != MVT::v8i16) 4633 return 0; 4634 if ((Subtarget->hasMVEIntegerOps())) { 4635 return fastEmitInst_rr(ARM::MVE_VMAXs16, &ARM::MQPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4636 } 4637 if ((Subtarget->hasNEON())) { 4638 return fastEmitInst_rr(ARM::VMAXsv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4639 } 4640 return 0; 4641} 4642 4643unsigned fastEmit_ISD_SMAX_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4644 if (RetVT.SimpleTy != MVT::v2i32) 4645 return 0; 4646 if ((Subtarget->hasNEON())) { 4647 return fastEmitInst_rr(ARM::VMAXsv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4648 } 4649 return 0; 4650} 4651 4652unsigned fastEmit_ISD_SMAX_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4653 if (RetVT.SimpleTy != MVT::v4i32) 4654 return 0; 4655 if ((Subtarget->hasMVEIntegerOps())) { 4656 return fastEmitInst_rr(ARM::MVE_VMAXs32, &ARM::MQPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4657 } 4658 if ((Subtarget->hasNEON())) { 4659 return fastEmitInst_rr(ARM::VMAXsv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4660 } 4661 return 0; 4662} 4663 4664unsigned fastEmit_ISD_SMAX_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4665 switch (VT.SimpleTy) { 4666 case MVT::v8i8: return fastEmit_ISD_SMAX_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4667 case MVT::v16i8: return fastEmit_ISD_SMAX_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4668 case MVT::v4i16: return fastEmit_ISD_SMAX_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4669 case MVT::v8i16: return fastEmit_ISD_SMAX_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4670 case MVT::v2i32: return fastEmit_ISD_SMAX_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4671 case MVT::v4i32: return fastEmit_ISD_SMAX_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4672 default: return 0; 4673 } 4674} 4675 4676// FastEmit functions for ISD::SMIN. 4677 4678unsigned fastEmit_ISD_SMIN_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4679 if (RetVT.SimpleTy != MVT::v8i8) 4680 return 0; 4681 if ((Subtarget->hasNEON())) { 4682 return fastEmitInst_rr(ARM::VMINsv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4683 } 4684 return 0; 4685} 4686 4687unsigned fastEmit_ISD_SMIN_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4688 if (RetVT.SimpleTy != MVT::v16i8) 4689 return 0; 4690 if ((Subtarget->hasMVEIntegerOps())) { 4691 return fastEmitInst_rr(ARM::MVE_VMINs8, &ARM::MQPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4692 } 4693 if ((Subtarget->hasNEON())) { 4694 return fastEmitInst_rr(ARM::VMINsv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4695 } 4696 return 0; 4697} 4698 4699unsigned fastEmit_ISD_SMIN_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4700 if (RetVT.SimpleTy != MVT::v4i16) 4701 return 0; 4702 if ((Subtarget->hasNEON())) { 4703 return fastEmitInst_rr(ARM::VMINsv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4704 } 4705 return 0; 4706} 4707 4708unsigned fastEmit_ISD_SMIN_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4709 if (RetVT.SimpleTy != MVT::v8i16) 4710 return 0; 4711 if ((Subtarget->hasMVEIntegerOps())) { 4712 return fastEmitInst_rr(ARM::MVE_VMINs16, &ARM::MQPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4713 } 4714 if ((Subtarget->hasNEON())) { 4715 return fastEmitInst_rr(ARM::VMINsv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4716 } 4717 return 0; 4718} 4719 4720unsigned fastEmit_ISD_SMIN_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4721 if (RetVT.SimpleTy != MVT::v2i32) 4722 return 0; 4723 if ((Subtarget->hasNEON())) { 4724 return fastEmitInst_rr(ARM::VMINsv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4725 } 4726 return 0; 4727} 4728 4729unsigned fastEmit_ISD_SMIN_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4730 if (RetVT.SimpleTy != MVT::v4i32) 4731 return 0; 4732 if ((Subtarget->hasMVEIntegerOps())) { 4733 return fastEmitInst_rr(ARM::MVE_VMINs32, &ARM::MQPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4734 } 4735 if ((Subtarget->hasNEON())) { 4736 return fastEmitInst_rr(ARM::VMINsv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4737 } 4738 return 0; 4739} 4740 4741unsigned fastEmit_ISD_SMIN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4742 switch (VT.SimpleTy) { 4743 case MVT::v8i8: return fastEmit_ISD_SMIN_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4744 case MVT::v16i8: return fastEmit_ISD_SMIN_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4745 case MVT::v4i16: return fastEmit_ISD_SMIN_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4746 case MVT::v8i16: return fastEmit_ISD_SMIN_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4747 case MVT::v2i32: return fastEmit_ISD_SMIN_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4748 case MVT::v4i32: return fastEmit_ISD_SMIN_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4749 default: return 0; 4750 } 4751} 4752 4753// FastEmit functions for ISD::SRA. 4754 4755unsigned fastEmit_ISD_SRA_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4756 if (RetVT.SimpleTy != MVT::i32) 4757 return 0; 4758 if ((Subtarget->isThumb2())) { 4759 return fastEmitInst_rr(ARM::t2ASRrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4760 } 4761 if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) { 4762 return fastEmitInst_rr(ARM::tASRrr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4763 } 4764 return 0; 4765} 4766 4767unsigned fastEmit_ISD_SRA_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4768 switch (VT.SimpleTy) { 4769 case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4770 default: return 0; 4771 } 4772} 4773 4774// FastEmit functions for ISD::SRL. 4775 4776unsigned fastEmit_ISD_SRL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4777 if (RetVT.SimpleTy != MVT::i32) 4778 return 0; 4779 if ((Subtarget->isThumb2())) { 4780 return fastEmitInst_rr(ARM::t2LSRrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4781 } 4782 if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) { 4783 return fastEmitInst_rr(ARM::tLSRrr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4784 } 4785 return 0; 4786} 4787 4788unsigned fastEmit_ISD_SRL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4789 switch (VT.SimpleTy) { 4790 case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4791 default: return 0; 4792 } 4793} 4794 4795// FastEmit functions for ISD::SSUBSAT. 4796 4797unsigned fastEmit_ISD_SSUBSAT_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4798 if (RetVT.SimpleTy != MVT::i32) 4799 return 0; 4800 if ((Subtarget->hasDSP()) && (Subtarget->isThumb2())) { 4801 return fastEmitInst_rr(ARM::t2QSUB, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4802 } 4803 if ((Subtarget->hasV5TEOps()) && (!Subtarget->isThumb())) { 4804 return fastEmitInst_rr(ARM::QSUB, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4805 } 4806 return 0; 4807} 4808 4809unsigned fastEmit_ISD_SSUBSAT_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4810 if (RetVT.SimpleTy != MVT::v8i8) 4811 return 0; 4812 if ((Subtarget->hasNEON())) { 4813 return fastEmitInst_rr(ARM::VQSUBsv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4814 } 4815 return 0; 4816} 4817 4818unsigned fastEmit_ISD_SSUBSAT_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4819 if (RetVT.SimpleTy != MVT::v16i8) 4820 return 0; 4821 if ((Subtarget->hasMVEIntegerOps())) { 4822 return fastEmitInst_rr(ARM::MVE_VQSUBs8, &ARM::MQPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4823 } 4824 if ((Subtarget->hasNEON())) { 4825 return fastEmitInst_rr(ARM::VQSUBsv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4826 } 4827 return 0; 4828} 4829 4830unsigned fastEmit_ISD_SSUBSAT_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4831 if (RetVT.SimpleTy != MVT::v4i16) 4832 return 0; 4833 if ((Subtarget->hasNEON())) { 4834 return fastEmitInst_rr(ARM::VQSUBsv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4835 } 4836 return 0; 4837} 4838 4839unsigned fastEmit_ISD_SSUBSAT_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4840 if (RetVT.SimpleTy != MVT::v8i16) 4841 return 0; 4842 if ((Subtarget->hasMVEIntegerOps())) { 4843 return fastEmitInst_rr(ARM::MVE_VQSUBs16, &ARM::MQPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4844 } 4845 if ((Subtarget->hasNEON())) { 4846 return fastEmitInst_rr(ARM::VQSUBsv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4847 } 4848 return 0; 4849} 4850 4851unsigned fastEmit_ISD_SSUBSAT_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4852 if (RetVT.SimpleTy != MVT::v2i32) 4853 return 0; 4854 if ((Subtarget->hasNEON())) { 4855 return fastEmitInst_rr(ARM::VQSUBsv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4856 } 4857 return 0; 4858} 4859 4860unsigned fastEmit_ISD_SSUBSAT_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4861 if (RetVT.SimpleTy != MVT::v4i32) 4862 return 0; 4863 if ((Subtarget->hasMVEIntegerOps())) { 4864 return fastEmitInst_rr(ARM::MVE_VQSUBs32, &ARM::MQPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4865 } 4866 if ((Subtarget->hasNEON())) { 4867 return fastEmitInst_rr(ARM::VQSUBsv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4868 } 4869 return 0; 4870} 4871 4872unsigned fastEmit_ISD_SSUBSAT_MVT_v1i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4873 if (RetVT.SimpleTy != MVT::v1i64) 4874 return 0; 4875 if ((Subtarget->hasNEON())) { 4876 return fastEmitInst_rr(ARM::VQSUBsv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4877 } 4878 return 0; 4879} 4880 4881unsigned fastEmit_ISD_SSUBSAT_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4882 if (RetVT.SimpleTy != MVT::v2i64) 4883 return 0; 4884 if ((Subtarget->hasNEON())) { 4885 return fastEmitInst_rr(ARM::VQSUBsv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4886 } 4887 return 0; 4888} 4889 4890unsigned fastEmit_ISD_SSUBSAT_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4891 switch (VT.SimpleTy) { 4892 case MVT::i32: return fastEmit_ISD_SSUBSAT_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4893 case MVT::v8i8: return fastEmit_ISD_SSUBSAT_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4894 case MVT::v16i8: return fastEmit_ISD_SSUBSAT_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4895 case MVT::v4i16: return fastEmit_ISD_SSUBSAT_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4896 case MVT::v8i16: return fastEmit_ISD_SSUBSAT_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4897 case MVT::v2i32: return fastEmit_ISD_SSUBSAT_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4898 case MVT::v4i32: return fastEmit_ISD_SSUBSAT_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4899 case MVT::v1i64: return fastEmit_ISD_SSUBSAT_MVT_v1i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4900 case MVT::v2i64: return fastEmit_ISD_SSUBSAT_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 4901 default: return 0; 4902 } 4903} 4904 4905// FastEmit functions for ISD::SUB. 4906 4907unsigned fastEmit_ISD_SUB_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4908 if (RetVT.SimpleTy != MVT::i32) 4909 return 0; 4910 if ((Subtarget->isThumb2())) { 4911 return fastEmitInst_rr(ARM::t2SUBrr, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4912 } 4913 if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) { 4914 return fastEmitInst_rr(ARM::tSUBrr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4915 } 4916 if ((!Subtarget->isThumb())) { 4917 return fastEmitInst_rr(ARM::SUBrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4918 } 4919 return 0; 4920} 4921 4922unsigned fastEmit_ISD_SUB_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4923 if (RetVT.SimpleTy != MVT::v8i8) 4924 return 0; 4925 if ((Subtarget->hasNEON())) { 4926 return fastEmitInst_rr(ARM::VSUBv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4927 } 4928 return 0; 4929} 4930 4931unsigned fastEmit_ISD_SUB_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4932 if (RetVT.SimpleTy != MVT::v16i8) 4933 return 0; 4934 if ((Subtarget->hasMVEIntegerOps())) { 4935 return fastEmitInst_rr(ARM::MVE_VSUBi8, &ARM::MQPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4936 } 4937 if ((Subtarget->hasNEON())) { 4938 return fastEmitInst_rr(ARM::VSUBv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4939 } 4940 return 0; 4941} 4942 4943unsigned fastEmit_ISD_SUB_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4944 if (RetVT.SimpleTy != MVT::v4i16) 4945 return 0; 4946 if ((Subtarget->hasNEON())) { 4947 return fastEmitInst_rr(ARM::VSUBv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4948 } 4949 return 0; 4950} 4951 4952unsigned fastEmit_ISD_SUB_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4953 if (RetVT.SimpleTy != MVT::v8i16) 4954 return 0; 4955 if ((Subtarget->hasMVEIntegerOps())) { 4956 return fastEmitInst_rr(ARM::MVE_VSUBi16, &ARM::MQPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4957 } 4958 if ((Subtarget->hasNEON())) { 4959 return fastEmitInst_rr(ARM::VSUBv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4960 } 4961 return 0; 4962} 4963 4964unsigned fastEmit_ISD_SUB_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4965 if (RetVT.SimpleTy != MVT::v2i32) 4966 return 0; 4967 if ((Subtarget->hasNEON())) { 4968 return fastEmitInst_rr(ARM::VSUBv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4969 } 4970 return 0; 4971} 4972 4973unsigned fastEmit_ISD_SUB_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4974 if (RetVT.SimpleTy != MVT::v4i32) 4975 return 0; 4976 if ((Subtarget->hasMVEIntegerOps())) { 4977 return fastEmitInst_rr(ARM::MVE_VSUBi32, &ARM::MQPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4978 } 4979 if ((Subtarget->hasNEON())) { 4980 return fastEmitInst_rr(ARM::VSUBv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4981 } 4982 return 0; 4983} 4984 4985unsigned fastEmit_ISD_SUB_MVT_v1i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4986 if (RetVT.SimpleTy != MVT::v1i64) 4987 return 0; 4988 if ((Subtarget->hasNEON())) { 4989 return fastEmitInst_rr(ARM::VSUBv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4990 } 4991 return 0; 4992} 4993 4994unsigned fastEmit_ISD_SUB_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 4995 if (RetVT.SimpleTy != MVT::v2i64) 4996 return 0; 4997 if ((Subtarget->hasNEON())) { 4998 return fastEmitInst_rr(ARM::VSUBv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 4999 } 5000 return 0; 5001} 5002 5003unsigned fastEmit_ISD_SUB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5004 switch (VT.SimpleTy) { 5005 case MVT::i32: return fastEmit_ISD_SUB_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5006 case MVT::v8i8: return fastEmit_ISD_SUB_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5007 case MVT::v16i8: return fastEmit_ISD_SUB_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5008 case MVT::v4i16: return fastEmit_ISD_SUB_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5009 case MVT::v8i16: return fastEmit_ISD_SUB_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5010 case MVT::v2i32: return fastEmit_ISD_SUB_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5011 case MVT::v4i32: return fastEmit_ISD_SUB_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5012 case MVT::v1i64: return fastEmit_ISD_SUB_MVT_v1i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5013 case MVT::v2i64: return fastEmit_ISD_SUB_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5014 default: return 0; 5015 } 5016} 5017 5018// FastEmit functions for ISD::UADDSAT. 5019 5020unsigned fastEmit_ISD_UADDSAT_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5021 if (RetVT.SimpleTy != MVT::v8i8) 5022 return 0; 5023 if ((Subtarget->hasNEON())) { 5024 return fastEmitInst_rr(ARM::VQADDuv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5025 } 5026 return 0; 5027} 5028 5029unsigned fastEmit_ISD_UADDSAT_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5030 if (RetVT.SimpleTy != MVT::v16i8) 5031 return 0; 5032 if ((Subtarget->hasMVEIntegerOps())) { 5033 return fastEmitInst_rr(ARM::MVE_VQADDu8, &ARM::MQPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5034 } 5035 if ((Subtarget->hasNEON())) { 5036 return fastEmitInst_rr(ARM::VQADDuv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5037 } 5038 return 0; 5039} 5040 5041unsigned fastEmit_ISD_UADDSAT_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5042 if (RetVT.SimpleTy != MVT::v4i16) 5043 return 0; 5044 if ((Subtarget->hasNEON())) { 5045 return fastEmitInst_rr(ARM::VQADDuv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5046 } 5047 return 0; 5048} 5049 5050unsigned fastEmit_ISD_UADDSAT_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5051 if (RetVT.SimpleTy != MVT::v8i16) 5052 return 0; 5053 if ((Subtarget->hasMVEIntegerOps())) { 5054 return fastEmitInst_rr(ARM::MVE_VQADDu16, &ARM::MQPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5055 } 5056 if ((Subtarget->hasNEON())) { 5057 return fastEmitInst_rr(ARM::VQADDuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5058 } 5059 return 0; 5060} 5061 5062unsigned fastEmit_ISD_UADDSAT_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5063 if (RetVT.SimpleTy != MVT::v2i32) 5064 return 0; 5065 if ((Subtarget->hasNEON())) { 5066 return fastEmitInst_rr(ARM::VQADDuv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5067 } 5068 return 0; 5069} 5070 5071unsigned fastEmit_ISD_UADDSAT_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5072 if (RetVT.SimpleTy != MVT::v4i32) 5073 return 0; 5074 if ((Subtarget->hasMVEIntegerOps())) { 5075 return fastEmitInst_rr(ARM::MVE_VQADDu32, &ARM::MQPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5076 } 5077 if ((Subtarget->hasNEON())) { 5078 return fastEmitInst_rr(ARM::VQADDuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5079 } 5080 return 0; 5081} 5082 5083unsigned fastEmit_ISD_UADDSAT_MVT_v1i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5084 if (RetVT.SimpleTy != MVT::v1i64) 5085 return 0; 5086 if ((Subtarget->hasNEON())) { 5087 return fastEmitInst_rr(ARM::VQADDuv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5088 } 5089 return 0; 5090} 5091 5092unsigned fastEmit_ISD_UADDSAT_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5093 if (RetVT.SimpleTy != MVT::v2i64) 5094 return 0; 5095 if ((Subtarget->hasNEON())) { 5096 return fastEmitInst_rr(ARM::VQADDuv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5097 } 5098 return 0; 5099} 5100 5101unsigned fastEmit_ISD_UADDSAT_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5102 switch (VT.SimpleTy) { 5103 case MVT::v8i8: return fastEmit_ISD_UADDSAT_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5104 case MVT::v16i8: return fastEmit_ISD_UADDSAT_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5105 case MVT::v4i16: return fastEmit_ISD_UADDSAT_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5106 case MVT::v8i16: return fastEmit_ISD_UADDSAT_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5107 case MVT::v2i32: return fastEmit_ISD_UADDSAT_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5108 case MVT::v4i32: return fastEmit_ISD_UADDSAT_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5109 case MVT::v1i64: return fastEmit_ISD_UADDSAT_MVT_v1i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5110 case MVT::v2i64: return fastEmit_ISD_UADDSAT_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5111 default: return 0; 5112 } 5113} 5114 5115// FastEmit functions for ISD::UDIV. 5116 5117unsigned fastEmit_ISD_UDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5118 if (RetVT.SimpleTy != MVT::i32) 5119 return 0; 5120 if ((Subtarget->hasDivideInThumbMode()) && (Subtarget->hasV8MBaselineOps()) && (Subtarget->isThumb())) { 5121 return fastEmitInst_rr(ARM::t2UDIV, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5122 } 5123 if ((Subtarget->hasDivideInARMMode()) && (!Subtarget->isThumb())) { 5124 return fastEmitInst_rr(ARM::UDIV, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5125 } 5126 return 0; 5127} 5128 5129unsigned fastEmit_ISD_UDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5130 switch (VT.SimpleTy) { 5131 case MVT::i32: return fastEmit_ISD_UDIV_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5132 default: return 0; 5133 } 5134} 5135 5136// FastEmit functions for ISD::UMAX. 5137 5138unsigned fastEmit_ISD_UMAX_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5139 if (RetVT.SimpleTy != MVT::v8i8) 5140 return 0; 5141 if ((Subtarget->hasNEON())) { 5142 return fastEmitInst_rr(ARM::VMAXuv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5143 } 5144 return 0; 5145} 5146 5147unsigned fastEmit_ISD_UMAX_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5148 if (RetVT.SimpleTy != MVT::v16i8) 5149 return 0; 5150 if ((Subtarget->hasMVEIntegerOps())) { 5151 return fastEmitInst_rr(ARM::MVE_VMAXu8, &ARM::MQPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5152 } 5153 if ((Subtarget->hasNEON())) { 5154 return fastEmitInst_rr(ARM::VMAXuv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5155 } 5156 return 0; 5157} 5158 5159unsigned fastEmit_ISD_UMAX_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5160 if (RetVT.SimpleTy != MVT::v4i16) 5161 return 0; 5162 if ((Subtarget->hasNEON())) { 5163 return fastEmitInst_rr(ARM::VMAXuv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5164 } 5165 return 0; 5166} 5167 5168unsigned fastEmit_ISD_UMAX_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5169 if (RetVT.SimpleTy != MVT::v8i16) 5170 return 0; 5171 if ((Subtarget->hasMVEIntegerOps())) { 5172 return fastEmitInst_rr(ARM::MVE_VMAXu16, &ARM::MQPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5173 } 5174 if ((Subtarget->hasNEON())) { 5175 return fastEmitInst_rr(ARM::VMAXuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5176 } 5177 return 0; 5178} 5179 5180unsigned fastEmit_ISD_UMAX_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5181 if (RetVT.SimpleTy != MVT::v2i32) 5182 return 0; 5183 if ((Subtarget->hasNEON())) { 5184 return fastEmitInst_rr(ARM::VMAXuv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5185 } 5186 return 0; 5187} 5188 5189unsigned fastEmit_ISD_UMAX_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5190 if (RetVT.SimpleTy != MVT::v4i32) 5191 return 0; 5192 if ((Subtarget->hasMVEIntegerOps())) { 5193 return fastEmitInst_rr(ARM::MVE_VMAXu32, &ARM::MQPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5194 } 5195 if ((Subtarget->hasNEON())) { 5196 return fastEmitInst_rr(ARM::VMAXuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5197 } 5198 return 0; 5199} 5200 5201unsigned fastEmit_ISD_UMAX_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5202 switch (VT.SimpleTy) { 5203 case MVT::v8i8: return fastEmit_ISD_UMAX_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5204 case MVT::v16i8: return fastEmit_ISD_UMAX_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5205 case MVT::v4i16: return fastEmit_ISD_UMAX_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5206 case MVT::v8i16: return fastEmit_ISD_UMAX_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5207 case MVT::v2i32: return fastEmit_ISD_UMAX_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5208 case MVT::v4i32: return fastEmit_ISD_UMAX_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5209 default: return 0; 5210 } 5211} 5212 5213// FastEmit functions for ISD::UMIN. 5214 5215unsigned fastEmit_ISD_UMIN_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5216 if (RetVT.SimpleTy != MVT::v8i8) 5217 return 0; 5218 if ((Subtarget->hasNEON())) { 5219 return fastEmitInst_rr(ARM::VMINuv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5220 } 5221 return 0; 5222} 5223 5224unsigned fastEmit_ISD_UMIN_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5225 if (RetVT.SimpleTy != MVT::v16i8) 5226 return 0; 5227 if ((Subtarget->hasMVEIntegerOps())) { 5228 return fastEmitInst_rr(ARM::MVE_VMINu8, &ARM::MQPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5229 } 5230 if ((Subtarget->hasNEON())) { 5231 return fastEmitInst_rr(ARM::VMINuv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5232 } 5233 return 0; 5234} 5235 5236unsigned fastEmit_ISD_UMIN_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5237 if (RetVT.SimpleTy != MVT::v4i16) 5238 return 0; 5239 if ((Subtarget->hasNEON())) { 5240 return fastEmitInst_rr(ARM::VMINuv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5241 } 5242 return 0; 5243} 5244 5245unsigned fastEmit_ISD_UMIN_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5246 if (RetVT.SimpleTy != MVT::v8i16) 5247 return 0; 5248 if ((Subtarget->hasMVEIntegerOps())) { 5249 return fastEmitInst_rr(ARM::MVE_VMINu16, &ARM::MQPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5250 } 5251 if ((Subtarget->hasNEON())) { 5252 return fastEmitInst_rr(ARM::VMINuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5253 } 5254 return 0; 5255} 5256 5257unsigned fastEmit_ISD_UMIN_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5258 if (RetVT.SimpleTy != MVT::v2i32) 5259 return 0; 5260 if ((Subtarget->hasNEON())) { 5261 return fastEmitInst_rr(ARM::VMINuv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5262 } 5263 return 0; 5264} 5265 5266unsigned fastEmit_ISD_UMIN_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5267 if (RetVT.SimpleTy != MVT::v4i32) 5268 return 0; 5269 if ((Subtarget->hasMVEIntegerOps())) { 5270 return fastEmitInst_rr(ARM::MVE_VMINu32, &ARM::MQPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5271 } 5272 if ((Subtarget->hasNEON())) { 5273 return fastEmitInst_rr(ARM::VMINuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5274 } 5275 return 0; 5276} 5277 5278unsigned fastEmit_ISD_UMIN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5279 switch (VT.SimpleTy) { 5280 case MVT::v8i8: return fastEmit_ISD_UMIN_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5281 case MVT::v16i8: return fastEmit_ISD_UMIN_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5282 case MVT::v4i16: return fastEmit_ISD_UMIN_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5283 case MVT::v8i16: return fastEmit_ISD_UMIN_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5284 case MVT::v2i32: return fastEmit_ISD_UMIN_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5285 case MVT::v4i32: return fastEmit_ISD_UMIN_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5286 default: return 0; 5287 } 5288} 5289 5290// FastEmit functions for ISD::USUBSAT. 5291 5292unsigned fastEmit_ISD_USUBSAT_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5293 if (RetVT.SimpleTy != MVT::v8i8) 5294 return 0; 5295 if ((Subtarget->hasNEON())) { 5296 return fastEmitInst_rr(ARM::VQSUBuv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5297 } 5298 return 0; 5299} 5300 5301unsigned fastEmit_ISD_USUBSAT_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5302 if (RetVT.SimpleTy != MVT::v16i8) 5303 return 0; 5304 if ((Subtarget->hasMVEIntegerOps())) { 5305 return fastEmitInst_rr(ARM::MVE_VQSUBu8, &ARM::MQPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5306 } 5307 if ((Subtarget->hasNEON())) { 5308 return fastEmitInst_rr(ARM::VQSUBuv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5309 } 5310 return 0; 5311} 5312 5313unsigned fastEmit_ISD_USUBSAT_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5314 if (RetVT.SimpleTy != MVT::v4i16) 5315 return 0; 5316 if ((Subtarget->hasNEON())) { 5317 return fastEmitInst_rr(ARM::VQSUBuv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5318 } 5319 return 0; 5320} 5321 5322unsigned fastEmit_ISD_USUBSAT_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5323 if (RetVT.SimpleTy != MVT::v8i16) 5324 return 0; 5325 if ((Subtarget->hasMVEIntegerOps())) { 5326 return fastEmitInst_rr(ARM::MVE_VQSUBu16, &ARM::MQPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5327 } 5328 if ((Subtarget->hasNEON())) { 5329 return fastEmitInst_rr(ARM::VQSUBuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5330 } 5331 return 0; 5332} 5333 5334unsigned fastEmit_ISD_USUBSAT_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5335 if (RetVT.SimpleTy != MVT::v2i32) 5336 return 0; 5337 if ((Subtarget->hasNEON())) { 5338 return fastEmitInst_rr(ARM::VQSUBuv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5339 } 5340 return 0; 5341} 5342 5343unsigned fastEmit_ISD_USUBSAT_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5344 if (RetVT.SimpleTy != MVT::v4i32) 5345 return 0; 5346 if ((Subtarget->hasMVEIntegerOps())) { 5347 return fastEmitInst_rr(ARM::MVE_VQSUBu32, &ARM::MQPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5348 } 5349 if ((Subtarget->hasNEON())) { 5350 return fastEmitInst_rr(ARM::VQSUBuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5351 } 5352 return 0; 5353} 5354 5355unsigned fastEmit_ISD_USUBSAT_MVT_v1i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5356 if (RetVT.SimpleTy != MVT::v1i64) 5357 return 0; 5358 if ((Subtarget->hasNEON())) { 5359 return fastEmitInst_rr(ARM::VQSUBuv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5360 } 5361 return 0; 5362} 5363 5364unsigned fastEmit_ISD_USUBSAT_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5365 if (RetVT.SimpleTy != MVT::v2i64) 5366 return 0; 5367 if ((Subtarget->hasNEON())) { 5368 return fastEmitInst_rr(ARM::VQSUBuv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5369 } 5370 return 0; 5371} 5372 5373unsigned fastEmit_ISD_USUBSAT_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5374 switch (VT.SimpleTy) { 5375 case MVT::v8i8: return fastEmit_ISD_USUBSAT_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5376 case MVT::v16i8: return fastEmit_ISD_USUBSAT_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5377 case MVT::v4i16: return fastEmit_ISD_USUBSAT_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5378 case MVT::v8i16: return fastEmit_ISD_USUBSAT_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5379 case MVT::v2i32: return fastEmit_ISD_USUBSAT_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5380 case MVT::v4i32: return fastEmit_ISD_USUBSAT_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5381 case MVT::v1i64: return fastEmit_ISD_USUBSAT_MVT_v1i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5382 case MVT::v2i64: return fastEmit_ISD_USUBSAT_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5383 default: return 0; 5384 } 5385} 5386 5387// FastEmit functions for ISD::XOR. 5388 5389unsigned fastEmit_ISD_XOR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5390 if (RetVT.SimpleTy != MVT::i32) 5391 return 0; 5392 if ((Subtarget->isThumb2())) { 5393 return fastEmitInst_rr(ARM::t2EORrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5394 } 5395 if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) { 5396 return fastEmitInst_rr(ARM::tEOR, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5397 } 5398 if ((!Subtarget->isThumb())) { 5399 return fastEmitInst_rr(ARM::EORrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5400 } 5401 return 0; 5402} 5403 5404unsigned fastEmit_ISD_XOR_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5405 if (RetVT.SimpleTy != MVT::v16i8) 5406 return 0; 5407 if ((Subtarget->hasMVEIntegerOps())) { 5408 return fastEmitInst_rr(ARM::MVE_VEOR, &ARM::MQPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5409 } 5410 return 0; 5411} 5412 5413unsigned fastEmit_ISD_XOR_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5414 if (RetVT.SimpleTy != MVT::v8i16) 5415 return 0; 5416 if ((Subtarget->hasMVEIntegerOps())) { 5417 return fastEmitInst_rr(ARM::MVE_VEOR, &ARM::MQPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5418 } 5419 return 0; 5420} 5421 5422unsigned fastEmit_ISD_XOR_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5423 if (RetVT.SimpleTy != MVT::v2i32) 5424 return 0; 5425 if ((Subtarget->hasNEON())) { 5426 return fastEmitInst_rr(ARM::VEORd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5427 } 5428 return 0; 5429} 5430 5431unsigned fastEmit_ISD_XOR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5432 if (RetVT.SimpleTy != MVT::v4i32) 5433 return 0; 5434 if ((Subtarget->hasMVEIntegerOps())) { 5435 return fastEmitInst_rr(ARM::MVE_VEOR, &ARM::MQPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5436 } 5437 if ((Subtarget->hasNEON())) { 5438 return fastEmitInst_rr(ARM::VEORq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5439 } 5440 return 0; 5441} 5442 5443unsigned fastEmit_ISD_XOR_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5444 if (RetVT.SimpleTy != MVT::v2i64) 5445 return 0; 5446 if ((Subtarget->hasMVEIntegerOps())) { 5447 return fastEmitInst_rr(ARM::MVE_VEOR, &ARM::MQPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 5448 } 5449 return 0; 5450} 5451 5452unsigned fastEmit_ISD_XOR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 5453 switch (VT.SimpleTy) { 5454 case MVT::i32: return fastEmit_ISD_XOR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5455 case MVT::v16i8: return fastEmit_ISD_XOR_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5456 case MVT::v8i16: return fastEmit_ISD_XOR_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5457 case MVT::v2i32: return fastEmit_ISD_XOR_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5458 case MVT::v4i32: return fastEmit_ISD_XOR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5459 case MVT::v2i64: return fastEmit_ISD_XOR_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5460 default: return 0; 5461 } 5462} 5463 5464// Top-level FastEmit function. 5465 5466unsigned fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) override { 5467 switch (Opcode) { 5468 case ARMISD::CMP: return fastEmit_ARMISD_CMP_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5469 case ARMISD::CMPFP: return fastEmit_ARMISD_CMPFP_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5470 case ARMISD::CMPFPE: return fastEmit_ARMISD_CMPFPE_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5471 case ARMISD::CMPZ: return fastEmit_ARMISD_CMPZ_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5472 case ARMISD::EH_SJLJ_LONGJMP: return fastEmit_ARMISD_EH_SJLJ_LONGJMP_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5473 case ARMISD::EH_SJLJ_SETJMP: return fastEmit_ARMISD_EH_SJLJ_SETJMP_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5474 case ARMISD::QADD16b: return fastEmit_ARMISD_QADD16b_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5475 case ARMISD::QADD8b: return fastEmit_ARMISD_QADD8b_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5476 case ARMISD::QSUB16b: return fastEmit_ARMISD_QSUB16b_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5477 case ARMISD::QSUB8b: return fastEmit_ARMISD_QSUB8b_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5478 case ARMISD::SMULWB: return fastEmit_ARMISD_SMULWB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5479 case ARMISD::SMULWT: return fastEmit_ARMISD_SMULWT_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5480 case ARMISD::SUBS: return fastEmit_ARMISD_SUBS_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5481 case ARMISD::VMOVDRR: return fastEmit_ARMISD_VMOVDRR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5482 case ARMISD::VMULLs: return fastEmit_ARMISD_VMULLs_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5483 case ARMISD::VMULLu: return fastEmit_ARMISD_VMULLu_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5484 case ARMISD::VSHLs: return fastEmit_ARMISD_VSHLs_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5485 case ARMISD::VSHLu: return fastEmit_ARMISD_VSHLu_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5486 case ARMISD::VTBL1: return fastEmit_ARMISD_VTBL1_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5487 case ARMISD::VTST: return fastEmit_ARMISD_VTST_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5488 case ISD::ADD: return fastEmit_ISD_ADD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5489 case ISD::AND: return fastEmit_ISD_AND_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5490 case ISD::FADD: return fastEmit_ISD_FADD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5491 case ISD::FDIV: return fastEmit_ISD_FDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5492 case ISD::FMAXIMUM: return fastEmit_ISD_FMAXIMUM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5493 case ISD::FMAXNUM: return fastEmit_ISD_FMAXNUM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5494 case ISD::FMINIMUM: return fastEmit_ISD_FMINIMUM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5495 case ISD::FMINNUM: return fastEmit_ISD_FMINNUM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5496 case ISD::FMUL: return fastEmit_ISD_FMUL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5497 case ISD::FSUB: return fastEmit_ISD_FSUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5498 case ISD::MUL: return fastEmit_ISD_MUL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5499 case ISD::MULHS: return fastEmit_ISD_MULHS_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5500 case ISD::OR: return fastEmit_ISD_OR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5501 case ISD::ROTR: return fastEmit_ISD_ROTR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5502 case ISD::SADDSAT: return fastEmit_ISD_SADDSAT_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5503 case ISD::SDIV: return fastEmit_ISD_SDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5504 case ISD::SHL: return fastEmit_ISD_SHL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5505 case ISD::SMAX: return fastEmit_ISD_SMAX_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5506 case ISD::SMIN: return fastEmit_ISD_SMIN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5507 case ISD::SRA: return fastEmit_ISD_SRA_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5508 case ISD::SRL: return fastEmit_ISD_SRL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5509 case ISD::SSUBSAT: return fastEmit_ISD_SSUBSAT_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5510 case ISD::SUB: return fastEmit_ISD_SUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5511 case ISD::UADDSAT: return fastEmit_ISD_UADDSAT_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5512 case ISD::UDIV: return fastEmit_ISD_UDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5513 case ISD::UMAX: return fastEmit_ISD_UMAX_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5514 case ISD::UMIN: return fastEmit_ISD_UMIN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5515 case ISD::USUBSAT: return fastEmit_ISD_USUBSAT_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5516 case ISD::XOR: return fastEmit_ISD_XOR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 5517 default: return 0; 5518 } 5519} 5520 5521// FastEmit functions for ARMISD::PIC_ADD. 5522 5523unsigned fastEmit_ARMISD_PIC_ADD_MVT_i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5524 if (RetVT.SimpleTy != MVT::i32) 5525 return 0; 5526 if ((Subtarget->isThumb())) { 5527 return fastEmitInst_ri(ARM::tPICADD, &ARM::GPRRegClass, Op0, Op0IsKill, imm1); 5528 } 5529 if ((!Subtarget->isThumb())) { 5530 return fastEmitInst_ri(ARM::PICADD, &ARM::GPRRegClass, Op0, Op0IsKill, imm1); 5531 } 5532 return 0; 5533} 5534 5535unsigned fastEmit_ARMISD_PIC_ADD_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5536 switch (VT.SimpleTy) { 5537 case MVT::i32: return fastEmit_ARMISD_PIC_ADD_MVT_i32_ri(RetVT, Op0, Op0IsKill, imm1); 5538 default: return 0; 5539 } 5540} 5541 5542// FastEmit functions for ARMISD::VDUPLANE. 5543 5544unsigned fastEmit_ARMISD_VDUPLANE_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5545 if (RetVT.SimpleTy != MVT::v8i8) 5546 return 0; 5547 if ((Subtarget->hasNEON())) { 5548 return fastEmitInst_ri(ARM::VDUPLN8d, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 5549 } 5550 return 0; 5551} 5552 5553unsigned fastEmit_ARMISD_VDUPLANE_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5554 if (RetVT.SimpleTy != MVT::v4i16) 5555 return 0; 5556 if ((Subtarget->hasNEON())) { 5557 return fastEmitInst_ri(ARM::VDUPLN16d, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 5558 } 5559 return 0; 5560} 5561 5562unsigned fastEmit_ARMISD_VDUPLANE_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5563 if (RetVT.SimpleTy != MVT::v2i32) 5564 return 0; 5565 if ((Subtarget->hasNEON())) { 5566 return fastEmitInst_ri(ARM::VDUPLN32d, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 5567 } 5568 return 0; 5569} 5570 5571unsigned fastEmit_ARMISD_VDUPLANE_MVT_v4f16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5572 if (RetVT.SimpleTy != MVT::v4f16) 5573 return 0; 5574 if ((Subtarget->hasNEON())) { 5575 return fastEmitInst_ri(ARM::VDUPLN32d, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 5576 } 5577 return 0; 5578} 5579 5580unsigned fastEmit_ARMISD_VDUPLANE_MVT_v2f32_MVT_v2f32_ri(unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5581 if ((Subtarget->hasNEON())) { 5582 return fastEmitInst_ri(ARM::VDUPLN32d, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 5583 } 5584 return 0; 5585} 5586 5587unsigned fastEmit_ARMISD_VDUPLANE_MVT_v2f32_MVT_v4f32_ri(unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5588 if ((Subtarget->hasNEON())) { 5589 return fastEmitInst_ri(ARM::VDUPLN32q, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 5590 } 5591 return 0; 5592} 5593 5594unsigned fastEmit_ARMISD_VDUPLANE_MVT_v2f32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5595switch (RetVT.SimpleTy) { 5596 case MVT::v2f32: return fastEmit_ARMISD_VDUPLANE_MVT_v2f32_MVT_v2f32_ri(Op0, Op0IsKill, imm1); 5597 case MVT::v4f32: return fastEmit_ARMISD_VDUPLANE_MVT_v2f32_MVT_v4f32_ri(Op0, Op0IsKill, imm1); 5598 default: return 0; 5599} 5600} 5601 5602unsigned fastEmit_ARMISD_VDUPLANE_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5603 switch (VT.SimpleTy) { 5604 case MVT::v8i8: return fastEmit_ARMISD_VDUPLANE_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1); 5605 case MVT::v4i16: return fastEmit_ARMISD_VDUPLANE_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1); 5606 case MVT::v2i32: return fastEmit_ARMISD_VDUPLANE_MVT_v2i32_ri(RetVT, Op0, Op0IsKill, imm1); 5607 case MVT::v4f16: return fastEmit_ARMISD_VDUPLANE_MVT_v4f16_ri(RetVT, Op0, Op0IsKill, imm1); 5608 case MVT::v2f32: return fastEmit_ARMISD_VDUPLANE_MVT_v2f32_ri(RetVT, Op0, Op0IsKill, imm1); 5609 default: return 0; 5610 } 5611} 5612 5613// FastEmit functions for ARMISD::VGETLANEs. 5614 5615unsigned fastEmit_ARMISD_VGETLANEs_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5616 if (RetVT.SimpleTy != MVT::i32) 5617 return 0; 5618 if ((Subtarget->hasNEON())) { 5619 return fastEmitInst_ri(ARM::VGETLNs8, &ARM::GPRRegClass, Op0, Op0IsKill, imm1); 5620 } 5621 return 0; 5622} 5623 5624unsigned fastEmit_ARMISD_VGETLANEs_MVT_v16i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5625 if (RetVT.SimpleTy != MVT::i32) 5626 return 0; 5627 if ((Subtarget->hasMVEIntegerOps())) { 5628 return fastEmitInst_ri(ARM::MVE_VMOV_from_lane_s8, &ARM::rGPRRegClass, Op0, Op0IsKill, imm1); 5629 } 5630 return 0; 5631} 5632 5633unsigned fastEmit_ARMISD_VGETLANEs_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5634 if (RetVT.SimpleTy != MVT::i32) 5635 return 0; 5636 if ((Subtarget->hasNEON())) { 5637 return fastEmitInst_ri(ARM::VGETLNs16, &ARM::GPRRegClass, Op0, Op0IsKill, imm1); 5638 } 5639 return 0; 5640} 5641 5642unsigned fastEmit_ARMISD_VGETLANEs_MVT_v8i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5643 if (RetVT.SimpleTy != MVT::i32) 5644 return 0; 5645 if ((Subtarget->hasMVEIntegerOps())) { 5646 return fastEmitInst_ri(ARM::MVE_VMOV_from_lane_s16, &ARM::rGPRRegClass, Op0, Op0IsKill, imm1); 5647 } 5648 return 0; 5649} 5650 5651unsigned fastEmit_ARMISD_VGETLANEs_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5652 switch (VT.SimpleTy) { 5653 case MVT::v8i8: return fastEmit_ARMISD_VGETLANEs_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1); 5654 case MVT::v16i8: return fastEmit_ARMISD_VGETLANEs_MVT_v16i8_ri(RetVT, Op0, Op0IsKill, imm1); 5655 case MVT::v4i16: return fastEmit_ARMISD_VGETLANEs_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1); 5656 case MVT::v8i16: return fastEmit_ARMISD_VGETLANEs_MVT_v8i16_ri(RetVT, Op0, Op0IsKill, imm1); 5657 default: return 0; 5658 } 5659} 5660 5661// FastEmit functions for ARMISD::VGETLANEu. 5662 5663unsigned fastEmit_ARMISD_VGETLANEu_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5664 if (RetVT.SimpleTy != MVT::i32) 5665 return 0; 5666 if ((Subtarget->hasNEON())) { 5667 return fastEmitInst_ri(ARM::VGETLNu8, &ARM::GPRRegClass, Op0, Op0IsKill, imm1); 5668 } 5669 return 0; 5670} 5671 5672unsigned fastEmit_ARMISD_VGETLANEu_MVT_v16i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5673 if (RetVT.SimpleTy != MVT::i32) 5674 return 0; 5675 if ((Subtarget->hasMVEIntegerOps())) { 5676 return fastEmitInst_ri(ARM::MVE_VMOV_from_lane_u8, &ARM::rGPRRegClass, Op0, Op0IsKill, imm1); 5677 } 5678 return 0; 5679} 5680 5681unsigned fastEmit_ARMISD_VGETLANEu_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5682 if (RetVT.SimpleTy != MVT::i32) 5683 return 0; 5684 if ((Subtarget->hasNEON())) { 5685 return fastEmitInst_ri(ARM::VGETLNu16, &ARM::GPRRegClass, Op0, Op0IsKill, imm1); 5686 } 5687 return 0; 5688} 5689 5690unsigned fastEmit_ARMISD_VGETLANEu_MVT_v8i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5691 if (RetVT.SimpleTy != MVT::i32) 5692 return 0; 5693 if ((Subtarget->hasMVEIntegerOps())) { 5694 return fastEmitInst_ri(ARM::MVE_VMOV_from_lane_u16, &ARM::rGPRRegClass, Op0, Op0IsKill, imm1); 5695 } 5696 return 0; 5697} 5698 5699unsigned fastEmit_ARMISD_VGETLANEu_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5700 switch (VT.SimpleTy) { 5701 case MVT::v8i8: return fastEmit_ARMISD_VGETLANEu_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1); 5702 case MVT::v16i8: return fastEmit_ARMISD_VGETLANEu_MVT_v16i8_ri(RetVT, Op0, Op0IsKill, imm1); 5703 case MVT::v4i16: return fastEmit_ARMISD_VGETLANEu_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1); 5704 case MVT::v8i16: return fastEmit_ARMISD_VGETLANEu_MVT_v8i16_ri(RetVT, Op0, Op0IsKill, imm1); 5705 default: return 0; 5706 } 5707} 5708 5709// FastEmit functions for ARMISD::VQSHLsIMM. 5710 5711unsigned fastEmit_ARMISD_VQSHLsIMM_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5712 if (RetVT.SimpleTy != MVT::v8i8) 5713 return 0; 5714 if ((Subtarget->hasNEON())) { 5715 return fastEmitInst_ri(ARM::VQSHLsiv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 5716 } 5717 return 0; 5718} 5719 5720unsigned fastEmit_ARMISD_VQSHLsIMM_MVT_v16i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5721 if (RetVT.SimpleTy != MVT::v16i8) 5722 return 0; 5723 if ((Subtarget->hasNEON())) { 5724 return fastEmitInst_ri(ARM::VQSHLsiv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 5725 } 5726 return 0; 5727} 5728 5729unsigned fastEmit_ARMISD_VQSHLsIMM_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5730 if (RetVT.SimpleTy != MVT::v4i16) 5731 return 0; 5732 if ((Subtarget->hasNEON())) { 5733 return fastEmitInst_ri(ARM::VQSHLsiv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 5734 } 5735 return 0; 5736} 5737 5738unsigned fastEmit_ARMISD_VQSHLsIMM_MVT_v8i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5739 if (RetVT.SimpleTy != MVT::v8i16) 5740 return 0; 5741 if ((Subtarget->hasNEON())) { 5742 return fastEmitInst_ri(ARM::VQSHLsiv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 5743 } 5744 return 0; 5745} 5746 5747unsigned fastEmit_ARMISD_VQSHLsIMM_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5748 if (RetVT.SimpleTy != MVT::v2i32) 5749 return 0; 5750 if ((Subtarget->hasNEON())) { 5751 return fastEmitInst_ri(ARM::VQSHLsiv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 5752 } 5753 return 0; 5754} 5755 5756unsigned fastEmit_ARMISD_VQSHLsIMM_MVT_v4i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5757 if (RetVT.SimpleTy != MVT::v4i32) 5758 return 0; 5759 if ((Subtarget->hasNEON())) { 5760 return fastEmitInst_ri(ARM::VQSHLsiv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 5761 } 5762 return 0; 5763} 5764 5765unsigned fastEmit_ARMISD_VQSHLsIMM_MVT_v1i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5766 if (RetVT.SimpleTy != MVT::v1i64) 5767 return 0; 5768 if ((Subtarget->hasNEON())) { 5769 return fastEmitInst_ri(ARM::VQSHLsiv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 5770 } 5771 return 0; 5772} 5773 5774unsigned fastEmit_ARMISD_VQSHLsIMM_MVT_v2i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5775 if (RetVT.SimpleTy != MVT::v2i64) 5776 return 0; 5777 if ((Subtarget->hasNEON())) { 5778 return fastEmitInst_ri(ARM::VQSHLsiv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 5779 } 5780 return 0; 5781} 5782 5783unsigned fastEmit_ARMISD_VQSHLsIMM_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5784 switch (VT.SimpleTy) { 5785 case MVT::v8i8: return fastEmit_ARMISD_VQSHLsIMM_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1); 5786 case MVT::v16i8: return fastEmit_ARMISD_VQSHLsIMM_MVT_v16i8_ri(RetVT, Op0, Op0IsKill, imm1); 5787 case MVT::v4i16: return fastEmit_ARMISD_VQSHLsIMM_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1); 5788 case MVT::v8i16: return fastEmit_ARMISD_VQSHLsIMM_MVT_v8i16_ri(RetVT, Op0, Op0IsKill, imm1); 5789 case MVT::v2i32: return fastEmit_ARMISD_VQSHLsIMM_MVT_v2i32_ri(RetVT, Op0, Op0IsKill, imm1); 5790 case MVT::v4i32: return fastEmit_ARMISD_VQSHLsIMM_MVT_v4i32_ri(RetVT, Op0, Op0IsKill, imm1); 5791 case MVT::v1i64: return fastEmit_ARMISD_VQSHLsIMM_MVT_v1i64_ri(RetVT, Op0, Op0IsKill, imm1); 5792 case MVT::v2i64: return fastEmit_ARMISD_VQSHLsIMM_MVT_v2i64_ri(RetVT, Op0, Op0IsKill, imm1); 5793 default: return 0; 5794 } 5795} 5796 5797// FastEmit functions for ARMISD::VQSHLsuIMM. 5798 5799unsigned fastEmit_ARMISD_VQSHLsuIMM_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5800 if (RetVT.SimpleTy != MVT::v8i8) 5801 return 0; 5802 if ((Subtarget->hasNEON())) { 5803 return fastEmitInst_ri(ARM::VQSHLsuv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 5804 } 5805 return 0; 5806} 5807 5808unsigned fastEmit_ARMISD_VQSHLsuIMM_MVT_v16i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5809 if (RetVT.SimpleTy != MVT::v16i8) 5810 return 0; 5811 if ((Subtarget->hasNEON())) { 5812 return fastEmitInst_ri(ARM::VQSHLsuv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 5813 } 5814 return 0; 5815} 5816 5817unsigned fastEmit_ARMISD_VQSHLsuIMM_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5818 if (RetVT.SimpleTy != MVT::v4i16) 5819 return 0; 5820 if ((Subtarget->hasNEON())) { 5821 return fastEmitInst_ri(ARM::VQSHLsuv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 5822 } 5823 return 0; 5824} 5825 5826unsigned fastEmit_ARMISD_VQSHLsuIMM_MVT_v8i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5827 if (RetVT.SimpleTy != MVT::v8i16) 5828 return 0; 5829 if ((Subtarget->hasNEON())) { 5830 return fastEmitInst_ri(ARM::VQSHLsuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 5831 } 5832 return 0; 5833} 5834 5835unsigned fastEmit_ARMISD_VQSHLsuIMM_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5836 if (RetVT.SimpleTy != MVT::v2i32) 5837 return 0; 5838 if ((Subtarget->hasNEON())) { 5839 return fastEmitInst_ri(ARM::VQSHLsuv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 5840 } 5841 return 0; 5842} 5843 5844unsigned fastEmit_ARMISD_VQSHLsuIMM_MVT_v4i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5845 if (RetVT.SimpleTy != MVT::v4i32) 5846 return 0; 5847 if ((Subtarget->hasNEON())) { 5848 return fastEmitInst_ri(ARM::VQSHLsuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 5849 } 5850 return 0; 5851} 5852 5853unsigned fastEmit_ARMISD_VQSHLsuIMM_MVT_v1i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5854 if (RetVT.SimpleTy != MVT::v1i64) 5855 return 0; 5856 if ((Subtarget->hasNEON())) { 5857 return fastEmitInst_ri(ARM::VQSHLsuv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 5858 } 5859 return 0; 5860} 5861 5862unsigned fastEmit_ARMISD_VQSHLsuIMM_MVT_v2i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5863 if (RetVT.SimpleTy != MVT::v2i64) 5864 return 0; 5865 if ((Subtarget->hasNEON())) { 5866 return fastEmitInst_ri(ARM::VQSHLsuv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 5867 } 5868 return 0; 5869} 5870 5871unsigned fastEmit_ARMISD_VQSHLsuIMM_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5872 switch (VT.SimpleTy) { 5873 case MVT::v8i8: return fastEmit_ARMISD_VQSHLsuIMM_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1); 5874 case MVT::v16i8: return fastEmit_ARMISD_VQSHLsuIMM_MVT_v16i8_ri(RetVT, Op0, Op0IsKill, imm1); 5875 case MVT::v4i16: return fastEmit_ARMISD_VQSHLsuIMM_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1); 5876 case MVT::v8i16: return fastEmit_ARMISD_VQSHLsuIMM_MVT_v8i16_ri(RetVT, Op0, Op0IsKill, imm1); 5877 case MVT::v2i32: return fastEmit_ARMISD_VQSHLsuIMM_MVT_v2i32_ri(RetVT, Op0, Op0IsKill, imm1); 5878 case MVT::v4i32: return fastEmit_ARMISD_VQSHLsuIMM_MVT_v4i32_ri(RetVT, Op0, Op0IsKill, imm1); 5879 case MVT::v1i64: return fastEmit_ARMISD_VQSHLsuIMM_MVT_v1i64_ri(RetVT, Op0, Op0IsKill, imm1); 5880 case MVT::v2i64: return fastEmit_ARMISD_VQSHLsuIMM_MVT_v2i64_ri(RetVT, Op0, Op0IsKill, imm1); 5881 default: return 0; 5882 } 5883} 5884 5885// FastEmit functions for ARMISD::VQSHLuIMM. 5886 5887unsigned fastEmit_ARMISD_VQSHLuIMM_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5888 if (RetVT.SimpleTy != MVT::v8i8) 5889 return 0; 5890 if ((Subtarget->hasNEON())) { 5891 return fastEmitInst_ri(ARM::VQSHLuiv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 5892 } 5893 return 0; 5894} 5895 5896unsigned fastEmit_ARMISD_VQSHLuIMM_MVT_v16i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5897 if (RetVT.SimpleTy != MVT::v16i8) 5898 return 0; 5899 if ((Subtarget->hasNEON())) { 5900 return fastEmitInst_ri(ARM::VQSHLuiv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 5901 } 5902 return 0; 5903} 5904 5905unsigned fastEmit_ARMISD_VQSHLuIMM_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5906 if (RetVT.SimpleTy != MVT::v4i16) 5907 return 0; 5908 if ((Subtarget->hasNEON())) { 5909 return fastEmitInst_ri(ARM::VQSHLuiv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 5910 } 5911 return 0; 5912} 5913 5914unsigned fastEmit_ARMISD_VQSHLuIMM_MVT_v8i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5915 if (RetVT.SimpleTy != MVT::v8i16) 5916 return 0; 5917 if ((Subtarget->hasNEON())) { 5918 return fastEmitInst_ri(ARM::VQSHLuiv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 5919 } 5920 return 0; 5921} 5922 5923unsigned fastEmit_ARMISD_VQSHLuIMM_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5924 if (RetVT.SimpleTy != MVT::v2i32) 5925 return 0; 5926 if ((Subtarget->hasNEON())) { 5927 return fastEmitInst_ri(ARM::VQSHLuiv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 5928 } 5929 return 0; 5930} 5931 5932unsigned fastEmit_ARMISD_VQSHLuIMM_MVT_v4i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5933 if (RetVT.SimpleTy != MVT::v4i32) 5934 return 0; 5935 if ((Subtarget->hasNEON())) { 5936 return fastEmitInst_ri(ARM::VQSHLuiv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 5937 } 5938 return 0; 5939} 5940 5941unsigned fastEmit_ARMISD_VQSHLuIMM_MVT_v1i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5942 if (RetVT.SimpleTy != MVT::v1i64) 5943 return 0; 5944 if ((Subtarget->hasNEON())) { 5945 return fastEmitInst_ri(ARM::VQSHLuiv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 5946 } 5947 return 0; 5948} 5949 5950unsigned fastEmit_ARMISD_VQSHLuIMM_MVT_v2i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5951 if (RetVT.SimpleTy != MVT::v2i64) 5952 return 0; 5953 if ((Subtarget->hasNEON())) { 5954 return fastEmitInst_ri(ARM::VQSHLuiv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 5955 } 5956 return 0; 5957} 5958 5959unsigned fastEmit_ARMISD_VQSHLuIMM_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5960 switch (VT.SimpleTy) { 5961 case MVT::v8i8: return fastEmit_ARMISD_VQSHLuIMM_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1); 5962 case MVT::v16i8: return fastEmit_ARMISD_VQSHLuIMM_MVT_v16i8_ri(RetVT, Op0, Op0IsKill, imm1); 5963 case MVT::v4i16: return fastEmit_ARMISD_VQSHLuIMM_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1); 5964 case MVT::v8i16: return fastEmit_ARMISD_VQSHLuIMM_MVT_v8i16_ri(RetVT, Op0, Op0IsKill, imm1); 5965 case MVT::v2i32: return fastEmit_ARMISD_VQSHLuIMM_MVT_v2i32_ri(RetVT, Op0, Op0IsKill, imm1); 5966 case MVT::v4i32: return fastEmit_ARMISD_VQSHLuIMM_MVT_v4i32_ri(RetVT, Op0, Op0IsKill, imm1); 5967 case MVT::v1i64: return fastEmit_ARMISD_VQSHLuIMM_MVT_v1i64_ri(RetVT, Op0, Op0IsKill, imm1); 5968 case MVT::v2i64: return fastEmit_ARMISD_VQSHLuIMM_MVT_v2i64_ri(RetVT, Op0, Op0IsKill, imm1); 5969 default: return 0; 5970 } 5971} 5972 5973// FastEmit functions for ARMISD::VRSHRsIMM. 5974 5975unsigned fastEmit_ARMISD_VRSHRsIMM_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5976 if (RetVT.SimpleTy != MVT::v8i8) 5977 return 0; 5978 if ((Subtarget->hasNEON())) { 5979 return fastEmitInst_ri(ARM::VRSHRsv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 5980 } 5981 return 0; 5982} 5983 5984unsigned fastEmit_ARMISD_VRSHRsIMM_MVT_v16i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5985 if (RetVT.SimpleTy != MVT::v16i8) 5986 return 0; 5987 if ((Subtarget->hasNEON())) { 5988 return fastEmitInst_ri(ARM::VRSHRsv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 5989 } 5990 return 0; 5991} 5992 5993unsigned fastEmit_ARMISD_VRSHRsIMM_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 5994 if (RetVT.SimpleTy != MVT::v4i16) 5995 return 0; 5996 if ((Subtarget->hasNEON())) { 5997 return fastEmitInst_ri(ARM::VRSHRsv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 5998 } 5999 return 0; 6000} 6001 6002unsigned fastEmit_ARMISD_VRSHRsIMM_MVT_v8i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6003 if (RetVT.SimpleTy != MVT::v8i16) 6004 return 0; 6005 if ((Subtarget->hasNEON())) { 6006 return fastEmitInst_ri(ARM::VRSHRsv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 6007 } 6008 return 0; 6009} 6010 6011unsigned fastEmit_ARMISD_VRSHRsIMM_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6012 if (RetVT.SimpleTy != MVT::v2i32) 6013 return 0; 6014 if ((Subtarget->hasNEON())) { 6015 return fastEmitInst_ri(ARM::VRSHRsv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 6016 } 6017 return 0; 6018} 6019 6020unsigned fastEmit_ARMISD_VRSHRsIMM_MVT_v4i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6021 if (RetVT.SimpleTy != MVT::v4i32) 6022 return 0; 6023 if ((Subtarget->hasNEON())) { 6024 return fastEmitInst_ri(ARM::VRSHRsv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 6025 } 6026 return 0; 6027} 6028 6029unsigned fastEmit_ARMISD_VRSHRsIMM_MVT_v1i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6030 if (RetVT.SimpleTy != MVT::v1i64) 6031 return 0; 6032 if ((Subtarget->hasNEON())) { 6033 return fastEmitInst_ri(ARM::VRSHRsv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 6034 } 6035 return 0; 6036} 6037 6038unsigned fastEmit_ARMISD_VRSHRsIMM_MVT_v2i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6039 if (RetVT.SimpleTy != MVT::v2i64) 6040 return 0; 6041 if ((Subtarget->hasNEON())) { 6042 return fastEmitInst_ri(ARM::VRSHRsv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 6043 } 6044 return 0; 6045} 6046 6047unsigned fastEmit_ARMISD_VRSHRsIMM_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6048 switch (VT.SimpleTy) { 6049 case MVT::v8i8: return fastEmit_ARMISD_VRSHRsIMM_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1); 6050 case MVT::v16i8: return fastEmit_ARMISD_VRSHRsIMM_MVT_v16i8_ri(RetVT, Op0, Op0IsKill, imm1); 6051 case MVT::v4i16: return fastEmit_ARMISD_VRSHRsIMM_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1); 6052 case MVT::v8i16: return fastEmit_ARMISD_VRSHRsIMM_MVT_v8i16_ri(RetVT, Op0, Op0IsKill, imm1); 6053 case MVT::v2i32: return fastEmit_ARMISD_VRSHRsIMM_MVT_v2i32_ri(RetVT, Op0, Op0IsKill, imm1); 6054 case MVT::v4i32: return fastEmit_ARMISD_VRSHRsIMM_MVT_v4i32_ri(RetVT, Op0, Op0IsKill, imm1); 6055 case MVT::v1i64: return fastEmit_ARMISD_VRSHRsIMM_MVT_v1i64_ri(RetVT, Op0, Op0IsKill, imm1); 6056 case MVT::v2i64: return fastEmit_ARMISD_VRSHRsIMM_MVT_v2i64_ri(RetVT, Op0, Op0IsKill, imm1); 6057 default: return 0; 6058 } 6059} 6060 6061// FastEmit functions for ARMISD::VRSHRuIMM. 6062 6063unsigned fastEmit_ARMISD_VRSHRuIMM_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6064 if (RetVT.SimpleTy != MVT::v8i8) 6065 return 0; 6066 if ((Subtarget->hasNEON())) { 6067 return fastEmitInst_ri(ARM::VRSHRuv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 6068 } 6069 return 0; 6070} 6071 6072unsigned fastEmit_ARMISD_VRSHRuIMM_MVT_v16i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6073 if (RetVT.SimpleTy != MVT::v16i8) 6074 return 0; 6075 if ((Subtarget->hasNEON())) { 6076 return fastEmitInst_ri(ARM::VRSHRuv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 6077 } 6078 return 0; 6079} 6080 6081unsigned fastEmit_ARMISD_VRSHRuIMM_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6082 if (RetVT.SimpleTy != MVT::v4i16) 6083 return 0; 6084 if ((Subtarget->hasNEON())) { 6085 return fastEmitInst_ri(ARM::VRSHRuv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 6086 } 6087 return 0; 6088} 6089 6090unsigned fastEmit_ARMISD_VRSHRuIMM_MVT_v8i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6091 if (RetVT.SimpleTy != MVT::v8i16) 6092 return 0; 6093 if ((Subtarget->hasNEON())) { 6094 return fastEmitInst_ri(ARM::VRSHRuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 6095 } 6096 return 0; 6097} 6098 6099unsigned fastEmit_ARMISD_VRSHRuIMM_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6100 if (RetVT.SimpleTy != MVT::v2i32) 6101 return 0; 6102 if ((Subtarget->hasNEON())) { 6103 return fastEmitInst_ri(ARM::VRSHRuv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 6104 } 6105 return 0; 6106} 6107 6108unsigned fastEmit_ARMISD_VRSHRuIMM_MVT_v4i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6109 if (RetVT.SimpleTy != MVT::v4i32) 6110 return 0; 6111 if ((Subtarget->hasNEON())) { 6112 return fastEmitInst_ri(ARM::VRSHRuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 6113 } 6114 return 0; 6115} 6116 6117unsigned fastEmit_ARMISD_VRSHRuIMM_MVT_v1i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6118 if (RetVT.SimpleTy != MVT::v1i64) 6119 return 0; 6120 if ((Subtarget->hasNEON())) { 6121 return fastEmitInst_ri(ARM::VRSHRuv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 6122 } 6123 return 0; 6124} 6125 6126unsigned fastEmit_ARMISD_VRSHRuIMM_MVT_v2i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6127 if (RetVT.SimpleTy != MVT::v2i64) 6128 return 0; 6129 if ((Subtarget->hasNEON())) { 6130 return fastEmitInst_ri(ARM::VRSHRuv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 6131 } 6132 return 0; 6133} 6134 6135unsigned fastEmit_ARMISD_VRSHRuIMM_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6136 switch (VT.SimpleTy) { 6137 case MVT::v8i8: return fastEmit_ARMISD_VRSHRuIMM_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1); 6138 case MVT::v16i8: return fastEmit_ARMISD_VRSHRuIMM_MVT_v16i8_ri(RetVT, Op0, Op0IsKill, imm1); 6139 case MVT::v4i16: return fastEmit_ARMISD_VRSHRuIMM_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1); 6140 case MVT::v8i16: return fastEmit_ARMISD_VRSHRuIMM_MVT_v8i16_ri(RetVT, Op0, Op0IsKill, imm1); 6141 case MVT::v2i32: return fastEmit_ARMISD_VRSHRuIMM_MVT_v2i32_ri(RetVT, Op0, Op0IsKill, imm1); 6142 case MVT::v4i32: return fastEmit_ARMISD_VRSHRuIMM_MVT_v4i32_ri(RetVT, Op0, Op0IsKill, imm1); 6143 case MVT::v1i64: return fastEmit_ARMISD_VRSHRuIMM_MVT_v1i64_ri(RetVT, Op0, Op0IsKill, imm1); 6144 case MVT::v2i64: return fastEmit_ARMISD_VRSHRuIMM_MVT_v2i64_ri(RetVT, Op0, Op0IsKill, imm1); 6145 default: return 0; 6146 } 6147} 6148 6149// FastEmit functions for ARMISD::VSHLIMM. 6150 6151unsigned fastEmit_ARMISD_VSHLIMM_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6152 if (RetVT.SimpleTy != MVT::v8i8) 6153 return 0; 6154 if ((Subtarget->hasNEON())) { 6155 return fastEmitInst_ri(ARM::VSHLiv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 6156 } 6157 return 0; 6158} 6159 6160unsigned fastEmit_ARMISD_VSHLIMM_MVT_v16i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6161 if (RetVT.SimpleTy != MVT::v16i8) 6162 return 0; 6163 if ((Subtarget->hasNEON())) { 6164 return fastEmitInst_ri(ARM::VSHLiv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 6165 } 6166 return 0; 6167} 6168 6169unsigned fastEmit_ARMISD_VSHLIMM_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6170 if (RetVT.SimpleTy != MVT::v4i16) 6171 return 0; 6172 if ((Subtarget->hasNEON())) { 6173 return fastEmitInst_ri(ARM::VSHLiv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 6174 } 6175 return 0; 6176} 6177 6178unsigned fastEmit_ARMISD_VSHLIMM_MVT_v8i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6179 if (RetVT.SimpleTy != MVT::v8i16) 6180 return 0; 6181 if ((Subtarget->hasNEON())) { 6182 return fastEmitInst_ri(ARM::VSHLiv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 6183 } 6184 return 0; 6185} 6186 6187unsigned fastEmit_ARMISD_VSHLIMM_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6188 if (RetVT.SimpleTy != MVT::v2i32) 6189 return 0; 6190 if ((Subtarget->hasNEON())) { 6191 return fastEmitInst_ri(ARM::VSHLiv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 6192 } 6193 return 0; 6194} 6195 6196unsigned fastEmit_ARMISD_VSHLIMM_MVT_v4i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6197 if (RetVT.SimpleTy != MVT::v4i32) 6198 return 0; 6199 if ((Subtarget->hasNEON())) { 6200 return fastEmitInst_ri(ARM::VSHLiv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 6201 } 6202 return 0; 6203} 6204 6205unsigned fastEmit_ARMISD_VSHLIMM_MVT_v1i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6206 if (RetVT.SimpleTy != MVT::v1i64) 6207 return 0; 6208 if ((Subtarget->hasNEON())) { 6209 return fastEmitInst_ri(ARM::VSHLiv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 6210 } 6211 return 0; 6212} 6213 6214unsigned fastEmit_ARMISD_VSHLIMM_MVT_v2i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6215 if (RetVT.SimpleTy != MVT::v2i64) 6216 return 0; 6217 if ((Subtarget->hasNEON())) { 6218 return fastEmitInst_ri(ARM::VSHLiv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 6219 } 6220 return 0; 6221} 6222 6223unsigned fastEmit_ARMISD_VSHLIMM_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6224 switch (VT.SimpleTy) { 6225 case MVT::v8i8: return fastEmit_ARMISD_VSHLIMM_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1); 6226 case MVT::v16i8: return fastEmit_ARMISD_VSHLIMM_MVT_v16i8_ri(RetVT, Op0, Op0IsKill, imm1); 6227 case MVT::v4i16: return fastEmit_ARMISD_VSHLIMM_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1); 6228 case MVT::v8i16: return fastEmit_ARMISD_VSHLIMM_MVT_v8i16_ri(RetVT, Op0, Op0IsKill, imm1); 6229 case MVT::v2i32: return fastEmit_ARMISD_VSHLIMM_MVT_v2i32_ri(RetVT, Op0, Op0IsKill, imm1); 6230 case MVT::v4i32: return fastEmit_ARMISD_VSHLIMM_MVT_v4i32_ri(RetVT, Op0, Op0IsKill, imm1); 6231 case MVT::v1i64: return fastEmit_ARMISD_VSHLIMM_MVT_v1i64_ri(RetVT, Op0, Op0IsKill, imm1); 6232 case MVT::v2i64: return fastEmit_ARMISD_VSHLIMM_MVT_v2i64_ri(RetVT, Op0, Op0IsKill, imm1); 6233 default: return 0; 6234 } 6235} 6236 6237// FastEmit functions for ARMISD::VSHRsIMM. 6238 6239unsigned fastEmit_ARMISD_VSHRsIMM_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6240 if (RetVT.SimpleTy != MVT::v8i8) 6241 return 0; 6242 if ((Subtarget->hasNEON())) { 6243 return fastEmitInst_ri(ARM::VSHRsv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 6244 } 6245 return 0; 6246} 6247 6248unsigned fastEmit_ARMISD_VSHRsIMM_MVT_v16i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6249 if (RetVT.SimpleTy != MVT::v16i8) 6250 return 0; 6251 if ((Subtarget->hasNEON())) { 6252 return fastEmitInst_ri(ARM::VSHRsv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 6253 } 6254 return 0; 6255} 6256 6257unsigned fastEmit_ARMISD_VSHRsIMM_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6258 if (RetVT.SimpleTy != MVT::v4i16) 6259 return 0; 6260 if ((Subtarget->hasNEON())) { 6261 return fastEmitInst_ri(ARM::VSHRsv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 6262 } 6263 return 0; 6264} 6265 6266unsigned fastEmit_ARMISD_VSHRsIMM_MVT_v8i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6267 if (RetVT.SimpleTy != MVT::v8i16) 6268 return 0; 6269 if ((Subtarget->hasNEON())) { 6270 return fastEmitInst_ri(ARM::VSHRsv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 6271 } 6272 return 0; 6273} 6274 6275unsigned fastEmit_ARMISD_VSHRsIMM_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6276 if (RetVT.SimpleTy != MVT::v2i32) 6277 return 0; 6278 if ((Subtarget->hasNEON())) { 6279 return fastEmitInst_ri(ARM::VSHRsv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 6280 } 6281 return 0; 6282} 6283 6284unsigned fastEmit_ARMISD_VSHRsIMM_MVT_v4i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6285 if (RetVT.SimpleTy != MVT::v4i32) 6286 return 0; 6287 if ((Subtarget->hasNEON())) { 6288 return fastEmitInst_ri(ARM::VSHRsv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 6289 } 6290 return 0; 6291} 6292 6293unsigned fastEmit_ARMISD_VSHRsIMM_MVT_v1i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6294 if (RetVT.SimpleTy != MVT::v1i64) 6295 return 0; 6296 if ((Subtarget->hasNEON())) { 6297 return fastEmitInst_ri(ARM::VSHRsv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 6298 } 6299 return 0; 6300} 6301 6302unsigned fastEmit_ARMISD_VSHRsIMM_MVT_v2i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6303 if (RetVT.SimpleTy != MVT::v2i64) 6304 return 0; 6305 if ((Subtarget->hasNEON())) { 6306 return fastEmitInst_ri(ARM::VSHRsv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 6307 } 6308 return 0; 6309} 6310 6311unsigned fastEmit_ARMISD_VSHRsIMM_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6312 switch (VT.SimpleTy) { 6313 case MVT::v8i8: return fastEmit_ARMISD_VSHRsIMM_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1); 6314 case MVT::v16i8: return fastEmit_ARMISD_VSHRsIMM_MVT_v16i8_ri(RetVT, Op0, Op0IsKill, imm1); 6315 case MVT::v4i16: return fastEmit_ARMISD_VSHRsIMM_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1); 6316 case MVT::v8i16: return fastEmit_ARMISD_VSHRsIMM_MVT_v8i16_ri(RetVT, Op0, Op0IsKill, imm1); 6317 case MVT::v2i32: return fastEmit_ARMISD_VSHRsIMM_MVT_v2i32_ri(RetVT, Op0, Op0IsKill, imm1); 6318 case MVT::v4i32: return fastEmit_ARMISD_VSHRsIMM_MVT_v4i32_ri(RetVT, Op0, Op0IsKill, imm1); 6319 case MVT::v1i64: return fastEmit_ARMISD_VSHRsIMM_MVT_v1i64_ri(RetVT, Op0, Op0IsKill, imm1); 6320 case MVT::v2i64: return fastEmit_ARMISD_VSHRsIMM_MVT_v2i64_ri(RetVT, Op0, Op0IsKill, imm1); 6321 default: return 0; 6322 } 6323} 6324 6325// FastEmit functions for ARMISD::VSHRuIMM. 6326 6327unsigned fastEmit_ARMISD_VSHRuIMM_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6328 if (RetVT.SimpleTy != MVT::v8i8) 6329 return 0; 6330 if ((Subtarget->hasNEON())) { 6331 return fastEmitInst_ri(ARM::VSHRuv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 6332 } 6333 return 0; 6334} 6335 6336unsigned fastEmit_ARMISD_VSHRuIMM_MVT_v16i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6337 if (RetVT.SimpleTy != MVT::v16i8) 6338 return 0; 6339 if ((Subtarget->hasNEON())) { 6340 return fastEmitInst_ri(ARM::VSHRuv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 6341 } 6342 return 0; 6343} 6344 6345unsigned fastEmit_ARMISD_VSHRuIMM_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6346 if (RetVT.SimpleTy != MVT::v4i16) 6347 return 0; 6348 if ((Subtarget->hasNEON())) { 6349 return fastEmitInst_ri(ARM::VSHRuv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 6350 } 6351 return 0; 6352} 6353 6354unsigned fastEmit_ARMISD_VSHRuIMM_MVT_v8i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6355 if (RetVT.SimpleTy != MVT::v8i16) 6356 return 0; 6357 if ((Subtarget->hasNEON())) { 6358 return fastEmitInst_ri(ARM::VSHRuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 6359 } 6360 return 0; 6361} 6362 6363unsigned fastEmit_ARMISD_VSHRuIMM_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6364 if (RetVT.SimpleTy != MVT::v2i32) 6365 return 0; 6366 if ((Subtarget->hasNEON())) { 6367 return fastEmitInst_ri(ARM::VSHRuv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 6368 } 6369 return 0; 6370} 6371 6372unsigned fastEmit_ARMISD_VSHRuIMM_MVT_v4i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6373 if (RetVT.SimpleTy != MVT::v4i32) 6374 return 0; 6375 if ((Subtarget->hasNEON())) { 6376 return fastEmitInst_ri(ARM::VSHRuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 6377 } 6378 return 0; 6379} 6380 6381unsigned fastEmit_ARMISD_VSHRuIMM_MVT_v1i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6382 if (RetVT.SimpleTy != MVT::v1i64) 6383 return 0; 6384 if ((Subtarget->hasNEON())) { 6385 return fastEmitInst_ri(ARM::VSHRuv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 6386 } 6387 return 0; 6388} 6389 6390unsigned fastEmit_ARMISD_VSHRuIMM_MVT_v2i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6391 if (RetVT.SimpleTy != MVT::v2i64) 6392 return 0; 6393 if ((Subtarget->hasNEON())) { 6394 return fastEmitInst_ri(ARM::VSHRuv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 6395 } 6396 return 0; 6397} 6398 6399unsigned fastEmit_ARMISD_VSHRuIMM_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6400 switch (VT.SimpleTy) { 6401 case MVT::v8i8: return fastEmit_ARMISD_VSHRuIMM_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1); 6402 case MVT::v16i8: return fastEmit_ARMISD_VSHRuIMM_MVT_v16i8_ri(RetVT, Op0, Op0IsKill, imm1); 6403 case MVT::v4i16: return fastEmit_ARMISD_VSHRuIMM_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1); 6404 case MVT::v8i16: return fastEmit_ARMISD_VSHRuIMM_MVT_v8i16_ri(RetVT, Op0, Op0IsKill, imm1); 6405 case MVT::v2i32: return fastEmit_ARMISD_VSHRuIMM_MVT_v2i32_ri(RetVT, Op0, Op0IsKill, imm1); 6406 case MVT::v4i32: return fastEmit_ARMISD_VSHRuIMM_MVT_v4i32_ri(RetVT, Op0, Op0IsKill, imm1); 6407 case MVT::v1i64: return fastEmit_ARMISD_VSHRuIMM_MVT_v1i64_ri(RetVT, Op0, Op0IsKill, imm1); 6408 case MVT::v2i64: return fastEmit_ARMISD_VSHRuIMM_MVT_v2i64_ri(RetVT, Op0, Op0IsKill, imm1); 6409 default: return 0; 6410 } 6411} 6412 6413// FastEmit functions for ISD::EXTRACT_VECTOR_ELT. 6414 6415unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6416 if (RetVT.SimpleTy != MVT::i32) 6417 return 0; 6418 if ((Subtarget->hasFPRegs()) && (!Subtarget->hasSlowVGETLNi32())) { 6419 return fastEmitInst_ri(ARM::VGETLNi32, &ARM::GPRRegClass, Op0, Op0IsKill, imm1); 6420 } 6421 return 0; 6422} 6423 6424unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6425 switch (VT.SimpleTy) { 6426 case MVT::v2i32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2i32_ri(RetVT, Op0, Op0IsKill, imm1); 6427 default: return 0; 6428 } 6429} 6430 6431// FastEmit functions for ISD::SHL. 6432 6433unsigned fastEmit_ISD_SHL_MVT_i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6434 if (RetVT.SimpleTy != MVT::i32) 6435 return 0; 6436 if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) { 6437 return fastEmitInst_ri(ARM::tLSLri, &ARM::tGPRRegClass, Op0, Op0IsKill, imm1); 6438 } 6439 return 0; 6440} 6441 6442unsigned fastEmit_ISD_SHL_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6443 switch (VT.SimpleTy) { 6444 case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_ri(RetVT, Op0, Op0IsKill, imm1); 6445 default: return 0; 6446 } 6447} 6448 6449// Top-level FastEmit function. 6450 6451unsigned fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) override { 6452 if (VT == MVT::i32 && Predicate_mod_imm(imm1)) 6453 if (unsigned Reg = fastEmit_ri_Predicate_mod_imm(VT, RetVT, Opcode, Op0, Op0IsKill, imm1)) 6454 return Reg; 6455 6456 if (VT == MVT::i32 && Predicate_imm0_7(imm1)) 6457 if (unsigned Reg = fastEmit_ri_Predicate_imm0_7(VT, RetVT, Opcode, Op0, Op0IsKill, imm1)) 6458 return Reg; 6459 6460 if (VT == MVT::i32 && Predicate_imm8_255(imm1)) 6461 if (unsigned Reg = fastEmit_ri_Predicate_imm8_255(VT, RetVT, Opcode, Op0, Op0IsKill, imm1)) 6462 return Reg; 6463 6464 if (VT == MVT::i32 && Predicate_imm0_255(imm1)) 6465 if (unsigned Reg = fastEmit_ri_Predicate_imm0_255(VT, RetVT, Opcode, Op0, Op0IsKill, imm1)) 6466 return Reg; 6467 6468 if (VT == MVT::i32 && Predicate_t2_so_imm(imm1)) 6469 if (unsigned Reg = fastEmit_ri_Predicate_t2_so_imm(VT, RetVT, Opcode, Op0, Op0IsKill, imm1)) 6470 return Reg; 6471 6472 if (VT == MVT::i32 && Predicate_imm0_4095(imm1)) 6473 if (unsigned Reg = fastEmit_ri_Predicate_imm0_4095(VT, RetVT, Opcode, Op0, Op0IsKill, imm1)) 6474 return Reg; 6475 6476 if (VT == MVT::i32 && Predicate_imm1_31(imm1)) 6477 if (unsigned Reg = fastEmit_ri_Predicate_imm1_31(VT, RetVT, Opcode, Op0, Op0IsKill, imm1)) 6478 return Reg; 6479 6480 if (VT == MVT::i32 && Predicate_imm0_31(imm1)) 6481 if (unsigned Reg = fastEmit_ri_Predicate_imm0_31(VT, RetVT, Opcode, Op0, Op0IsKill, imm1)) 6482 return Reg; 6483 6484 if (VT == MVT::i32 && Predicate_shr_imm8(imm1)) 6485 if (unsigned Reg = fastEmit_ri_Predicate_shr_imm8(VT, RetVT, Opcode, Op0, Op0IsKill, imm1)) 6486 return Reg; 6487 6488 if (VT == MVT::i32 && Predicate_shr_imm16(imm1)) 6489 if (unsigned Reg = fastEmit_ri_Predicate_shr_imm16(VT, RetVT, Opcode, Op0, Op0IsKill, imm1)) 6490 return Reg; 6491 6492 if (VT == MVT::i32 && Predicate_shr_imm32(imm1)) 6493 if (unsigned Reg = fastEmit_ri_Predicate_shr_imm32(VT, RetVT, Opcode, Op0, Op0IsKill, imm1)) 6494 return Reg; 6495 6496 if (VT == MVT::i32 && Predicate_VectorIndex32(imm1)) 6497 if (unsigned Reg = fastEmit_ri_Predicate_VectorIndex32(VT, RetVT, Opcode, Op0, Op0IsKill, imm1)) 6498 return Reg; 6499 6500 if (VT == MVT::i32 && Predicate_imm0_15(imm1)) 6501 if (unsigned Reg = fastEmit_ri_Predicate_imm0_15(VT, RetVT, Opcode, Op0, Op0IsKill, imm1)) 6502 return Reg; 6503 6504 switch (Opcode) { 6505 case ARMISD::PIC_ADD: return fastEmit_ARMISD_PIC_ADD_ri(VT, RetVT, Op0, Op0IsKill, imm1); 6506 case ARMISD::VDUPLANE: return fastEmit_ARMISD_VDUPLANE_ri(VT, RetVT, Op0, Op0IsKill, imm1); 6507 case ARMISD::VGETLANEs: return fastEmit_ARMISD_VGETLANEs_ri(VT, RetVT, Op0, Op0IsKill, imm1); 6508 case ARMISD::VGETLANEu: return fastEmit_ARMISD_VGETLANEu_ri(VT, RetVT, Op0, Op0IsKill, imm1); 6509 case ARMISD::VQSHLsIMM: return fastEmit_ARMISD_VQSHLsIMM_ri(VT, RetVT, Op0, Op0IsKill, imm1); 6510 case ARMISD::VQSHLsuIMM: return fastEmit_ARMISD_VQSHLsuIMM_ri(VT, RetVT, Op0, Op0IsKill, imm1); 6511 case ARMISD::VQSHLuIMM: return fastEmit_ARMISD_VQSHLuIMM_ri(VT, RetVT, Op0, Op0IsKill, imm1); 6512 case ARMISD::VRSHRsIMM: return fastEmit_ARMISD_VRSHRsIMM_ri(VT, RetVT, Op0, Op0IsKill, imm1); 6513 case ARMISD::VRSHRuIMM: return fastEmit_ARMISD_VRSHRuIMM_ri(VT, RetVT, Op0, Op0IsKill, imm1); 6514 case ARMISD::VSHLIMM: return fastEmit_ARMISD_VSHLIMM_ri(VT, RetVT, Op0, Op0IsKill, imm1); 6515 case ARMISD::VSHRsIMM: return fastEmit_ARMISD_VSHRsIMM_ri(VT, RetVT, Op0, Op0IsKill, imm1); 6516 case ARMISD::VSHRuIMM: return fastEmit_ARMISD_VSHRuIMM_ri(VT, RetVT, Op0, Op0IsKill, imm1); 6517 case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri(VT, RetVT, Op0, Op0IsKill, imm1); 6518 case ISD::SHL: return fastEmit_ISD_SHL_ri(VT, RetVT, Op0, Op0IsKill, imm1); 6519 default: return 0; 6520 } 6521} 6522 6523// FastEmit functions for ARMISD::CMN. 6524 6525unsigned fastEmit_ARMISD_CMN_MVT_i32_ri_Predicate_mod_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6526 if (RetVT.SimpleTy != MVT::isVoid) 6527 return 0; 6528 if ((!Subtarget->isThumb())) { 6529 return fastEmitInst_ri(ARM::CMNri, &ARM::GPRRegClass, Op0, Op0IsKill, imm1); 6530 } 6531 return 0; 6532} 6533 6534unsigned fastEmit_ARMISD_CMN_ri_Predicate_mod_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6535 switch (VT.SimpleTy) { 6536 case MVT::i32: return fastEmit_ARMISD_CMN_MVT_i32_ri_Predicate_mod_imm(RetVT, Op0, Op0IsKill, imm1); 6537 default: return 0; 6538 } 6539} 6540 6541// FastEmit functions for ARMISD::CMP. 6542 6543unsigned fastEmit_ARMISD_CMP_MVT_i32_ri_Predicate_mod_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6544 if (RetVT.SimpleTy != MVT::isVoid) 6545 return 0; 6546 if ((!Subtarget->isThumb())) { 6547 return fastEmitInst_ri(ARM::CMPri, &ARM::GPRRegClass, Op0, Op0IsKill, imm1); 6548 } 6549 return 0; 6550} 6551 6552unsigned fastEmit_ARMISD_CMP_ri_Predicate_mod_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6553 switch (VT.SimpleTy) { 6554 case MVT::i32: return fastEmit_ARMISD_CMP_MVT_i32_ri_Predicate_mod_imm(RetVT, Op0, Op0IsKill, imm1); 6555 default: return 0; 6556 } 6557} 6558 6559// FastEmit functions for ARMISD::CMPZ. 6560 6561unsigned fastEmit_ARMISD_CMPZ_MVT_i32_ri_Predicate_mod_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6562 if (RetVT.SimpleTy != MVT::isVoid) 6563 return 0; 6564 if ((!Subtarget->isThumb())) { 6565 return fastEmitInst_ri(ARM::CMPri, &ARM::GPRRegClass, Op0, Op0IsKill, imm1); 6566 } 6567 return 0; 6568} 6569 6570unsigned fastEmit_ARMISD_CMPZ_ri_Predicate_mod_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6571 switch (VT.SimpleTy) { 6572 case MVT::i32: return fastEmit_ARMISD_CMPZ_MVT_i32_ri_Predicate_mod_imm(RetVT, Op0, Op0IsKill, imm1); 6573 default: return 0; 6574 } 6575} 6576 6577// FastEmit functions for ARMISD::SUBS. 6578 6579unsigned fastEmit_ARMISD_SUBS_MVT_i32_ri_Predicate_mod_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6580 if (RetVT.SimpleTy != MVT::i32) 6581 return 0; 6582 if ((!Subtarget->isThumb())) { 6583 return fastEmitInst_ri(ARM::SUBSri, &ARM::GPRRegClass, Op0, Op0IsKill, imm1); 6584 } 6585 return 0; 6586} 6587 6588unsigned fastEmit_ARMISD_SUBS_ri_Predicate_mod_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6589 switch (VT.SimpleTy) { 6590 case MVT::i32: return fastEmit_ARMISD_SUBS_MVT_i32_ri_Predicate_mod_imm(RetVT, Op0, Op0IsKill, imm1); 6591 default: return 0; 6592 } 6593} 6594 6595// FastEmit functions for ISD::ADD. 6596 6597unsigned fastEmit_ISD_ADD_MVT_i32_ri_Predicate_mod_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6598 if (RetVT.SimpleTy != MVT::i32) 6599 return 0; 6600 if ((!Subtarget->isThumb())) { 6601 return fastEmitInst_ri(ARM::ADDri, &ARM::GPRRegClass, Op0, Op0IsKill, imm1); 6602 } 6603 return 0; 6604} 6605 6606unsigned fastEmit_ISD_ADD_ri_Predicate_mod_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6607 switch (VT.SimpleTy) { 6608 case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_mod_imm(RetVT, Op0, Op0IsKill, imm1); 6609 default: return 0; 6610 } 6611} 6612 6613// FastEmit functions for ISD::AND. 6614 6615unsigned fastEmit_ISD_AND_MVT_i32_ri_Predicate_mod_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6616 if (RetVT.SimpleTy != MVT::i32) 6617 return 0; 6618 if ((!Subtarget->isThumb())) { 6619 return fastEmitInst_ri(ARM::ANDri, &ARM::GPRRegClass, Op0, Op0IsKill, imm1); 6620 } 6621 return 0; 6622} 6623 6624unsigned fastEmit_ISD_AND_ri_Predicate_mod_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6625 switch (VT.SimpleTy) { 6626 case MVT::i32: return fastEmit_ISD_AND_MVT_i32_ri_Predicate_mod_imm(RetVT, Op0, Op0IsKill, imm1); 6627 default: return 0; 6628 } 6629} 6630 6631// FastEmit functions for ISD::OR. 6632 6633unsigned fastEmit_ISD_OR_MVT_i32_ri_Predicate_mod_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6634 if (RetVT.SimpleTy != MVT::i32) 6635 return 0; 6636 if ((!Subtarget->isThumb())) { 6637 return fastEmitInst_ri(ARM::ORRri, &ARM::GPRRegClass, Op0, Op0IsKill, imm1); 6638 } 6639 return 0; 6640} 6641 6642unsigned fastEmit_ISD_OR_ri_Predicate_mod_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6643 switch (VT.SimpleTy) { 6644 case MVT::i32: return fastEmit_ISD_OR_MVT_i32_ri_Predicate_mod_imm(RetVT, Op0, Op0IsKill, imm1); 6645 default: return 0; 6646 } 6647} 6648 6649// FastEmit functions for ISD::SUB. 6650 6651unsigned fastEmit_ISD_SUB_MVT_i32_ri_Predicate_mod_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6652 if (RetVT.SimpleTy != MVT::i32) 6653 return 0; 6654 if ((!Subtarget->isThumb())) { 6655 return fastEmitInst_ri(ARM::SUBri, &ARM::GPRRegClass, Op0, Op0IsKill, imm1); 6656 } 6657 return 0; 6658} 6659 6660unsigned fastEmit_ISD_SUB_ri_Predicate_mod_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6661 switch (VT.SimpleTy) { 6662 case MVT::i32: return fastEmit_ISD_SUB_MVT_i32_ri_Predicate_mod_imm(RetVT, Op0, Op0IsKill, imm1); 6663 default: return 0; 6664 } 6665} 6666 6667// FastEmit functions for ISD::XOR. 6668 6669unsigned fastEmit_ISD_XOR_MVT_i32_ri_Predicate_mod_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6670 if (RetVT.SimpleTy != MVT::i32) 6671 return 0; 6672 if ((!Subtarget->isThumb())) { 6673 return fastEmitInst_ri(ARM::EORri, &ARM::GPRRegClass, Op0, Op0IsKill, imm1); 6674 } 6675 return 0; 6676} 6677 6678unsigned fastEmit_ISD_XOR_ri_Predicate_mod_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6679 switch (VT.SimpleTy) { 6680 case MVT::i32: return fastEmit_ISD_XOR_MVT_i32_ri_Predicate_mod_imm(RetVT, Op0, Op0IsKill, imm1); 6681 default: return 0; 6682 } 6683} 6684 6685// Top-level FastEmit function. 6686 6687unsigned fastEmit_ri_Predicate_mod_imm(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6688 switch (Opcode) { 6689 case ARMISD::CMN: return fastEmit_ARMISD_CMN_ri_Predicate_mod_imm(VT, RetVT, Op0, Op0IsKill, imm1); 6690 case ARMISD::CMP: return fastEmit_ARMISD_CMP_ri_Predicate_mod_imm(VT, RetVT, Op0, Op0IsKill, imm1); 6691 case ARMISD::CMPZ: return fastEmit_ARMISD_CMPZ_ri_Predicate_mod_imm(VT, RetVT, Op0, Op0IsKill, imm1); 6692 case ARMISD::SUBS: return fastEmit_ARMISD_SUBS_ri_Predicate_mod_imm(VT, RetVT, Op0, Op0IsKill, imm1); 6693 case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_mod_imm(VT, RetVT, Op0, Op0IsKill, imm1); 6694 case ISD::AND: return fastEmit_ISD_AND_ri_Predicate_mod_imm(VT, RetVT, Op0, Op0IsKill, imm1); 6695 case ISD::OR: return fastEmit_ISD_OR_ri_Predicate_mod_imm(VT, RetVT, Op0, Op0IsKill, imm1); 6696 case ISD::SUB: return fastEmit_ISD_SUB_ri_Predicate_mod_imm(VT, RetVT, Op0, Op0IsKill, imm1); 6697 case ISD::XOR: return fastEmit_ISD_XOR_ri_Predicate_mod_imm(VT, RetVT, Op0, Op0IsKill, imm1); 6698 default: return 0; 6699 } 6700} 6701 6702// FastEmit functions for ARMISD::SUBS. 6703 6704unsigned fastEmit_ARMISD_SUBS_MVT_i32_ri_Predicate_imm0_7(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6705 if (RetVT.SimpleTy != MVT::i32) 6706 return 0; 6707 if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) { 6708 return fastEmitInst_ri(ARM::tSUBSi3, &ARM::tGPRRegClass, Op0, Op0IsKill, imm1); 6709 } 6710 return 0; 6711} 6712 6713unsigned fastEmit_ARMISD_SUBS_ri_Predicate_imm0_7(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6714 switch (VT.SimpleTy) { 6715 case MVT::i32: return fastEmit_ARMISD_SUBS_MVT_i32_ri_Predicate_imm0_7(RetVT, Op0, Op0IsKill, imm1); 6716 default: return 0; 6717 } 6718} 6719 6720// FastEmit functions for ARMISD::VSHLIMM. 6721 6722unsigned fastEmit_ARMISD_VSHLIMM_MVT_v16i8_ri_Predicate_imm0_7(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6723 if (RetVT.SimpleTy != MVT::v16i8) 6724 return 0; 6725 if ((Subtarget->hasMVEIntegerOps())) { 6726 return fastEmitInst_ri(ARM::MVE_VSHL_immi8, &ARM::MQPRRegClass, Op0, Op0IsKill, imm1); 6727 } 6728 return 0; 6729} 6730 6731unsigned fastEmit_ARMISD_VSHLIMM_ri_Predicate_imm0_7(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6732 switch (VT.SimpleTy) { 6733 case MVT::v16i8: return fastEmit_ARMISD_VSHLIMM_MVT_v16i8_ri_Predicate_imm0_7(RetVT, Op0, Op0IsKill, imm1); 6734 default: return 0; 6735 } 6736} 6737 6738// FastEmit functions for ARMISD::VSHRsIMM. 6739 6740unsigned fastEmit_ARMISD_VSHRsIMM_MVT_v16i8_ri_Predicate_imm0_7(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6741 if (RetVT.SimpleTy != MVT::v16i8) 6742 return 0; 6743 if ((Subtarget->hasMVEIntegerOps())) { 6744 return fastEmitInst_ri(ARM::MVE_VSHR_imms8, &ARM::MQPRRegClass, Op0, Op0IsKill, imm1); 6745 } 6746 return 0; 6747} 6748 6749unsigned fastEmit_ARMISD_VSHRsIMM_ri_Predicate_imm0_7(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6750 switch (VT.SimpleTy) { 6751 case MVT::v16i8: return fastEmit_ARMISD_VSHRsIMM_MVT_v16i8_ri_Predicate_imm0_7(RetVT, Op0, Op0IsKill, imm1); 6752 default: return 0; 6753 } 6754} 6755 6756// FastEmit functions for ARMISD::VSHRuIMM. 6757 6758unsigned fastEmit_ARMISD_VSHRuIMM_MVT_v16i8_ri_Predicate_imm0_7(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6759 if (RetVT.SimpleTy != MVT::v16i8) 6760 return 0; 6761 if ((Subtarget->hasMVEIntegerOps())) { 6762 return fastEmitInst_ri(ARM::MVE_VSHR_immu8, &ARM::MQPRRegClass, Op0, Op0IsKill, imm1); 6763 } 6764 return 0; 6765} 6766 6767unsigned fastEmit_ARMISD_VSHRuIMM_ri_Predicate_imm0_7(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6768 switch (VT.SimpleTy) { 6769 case MVT::v16i8: return fastEmit_ARMISD_VSHRuIMM_MVT_v16i8_ri_Predicate_imm0_7(RetVT, Op0, Op0IsKill, imm1); 6770 default: return 0; 6771 } 6772} 6773 6774// FastEmit functions for ISD::ADD. 6775 6776unsigned fastEmit_ISD_ADD_MVT_i32_ri_Predicate_imm0_7(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6777 if (RetVT.SimpleTy != MVT::i32) 6778 return 0; 6779 if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) { 6780 return fastEmitInst_ri(ARM::tADDi3, &ARM::tGPRRegClass, Op0, Op0IsKill, imm1); 6781 } 6782 return 0; 6783} 6784 6785unsigned fastEmit_ISD_ADD_ri_Predicate_imm0_7(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6786 switch (VT.SimpleTy) { 6787 case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_imm0_7(RetVT, Op0, Op0IsKill, imm1); 6788 default: return 0; 6789 } 6790} 6791 6792// Top-level FastEmit function. 6793 6794unsigned fastEmit_ri_Predicate_imm0_7(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6795 switch (Opcode) { 6796 case ARMISD::SUBS: return fastEmit_ARMISD_SUBS_ri_Predicate_imm0_7(VT, RetVT, Op0, Op0IsKill, imm1); 6797 case ARMISD::VSHLIMM: return fastEmit_ARMISD_VSHLIMM_ri_Predicate_imm0_7(VT, RetVT, Op0, Op0IsKill, imm1); 6798 case ARMISD::VSHRsIMM: return fastEmit_ARMISD_VSHRsIMM_ri_Predicate_imm0_7(VT, RetVT, Op0, Op0IsKill, imm1); 6799 case ARMISD::VSHRuIMM: return fastEmit_ARMISD_VSHRuIMM_ri_Predicate_imm0_7(VT, RetVT, Op0, Op0IsKill, imm1); 6800 case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_imm0_7(VT, RetVT, Op0, Op0IsKill, imm1); 6801 default: return 0; 6802 } 6803} 6804 6805// FastEmit functions for ISD::ADD. 6806 6807unsigned fastEmit_ISD_ADD_MVT_i32_ri_Predicate_imm8_255(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6808 if (RetVT.SimpleTy != MVT::i32) 6809 return 0; 6810 if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) { 6811 return fastEmitInst_ri(ARM::tADDi8, &ARM::tGPRRegClass, Op0, Op0IsKill, imm1); 6812 } 6813 return 0; 6814} 6815 6816unsigned fastEmit_ISD_ADD_ri_Predicate_imm8_255(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6817 switch (VT.SimpleTy) { 6818 case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_imm8_255(RetVT, Op0, Op0IsKill, imm1); 6819 default: return 0; 6820 } 6821} 6822 6823// Top-level FastEmit function. 6824 6825unsigned fastEmit_ri_Predicate_imm8_255(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6826 switch (Opcode) { 6827 case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_imm8_255(VT, RetVT, Op0, Op0IsKill, imm1); 6828 default: return 0; 6829 } 6830} 6831 6832// FastEmit functions for ARMISD::CMP. 6833 6834unsigned fastEmit_ARMISD_CMP_MVT_i32_ri_Predicate_imm0_255(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6835 if (RetVT.SimpleTy != MVT::isVoid) 6836 return 0; 6837 if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) { 6838 return fastEmitInst_ri(ARM::tCMPi8, &ARM::tGPRRegClass, Op0, Op0IsKill, imm1); 6839 } 6840 return 0; 6841} 6842 6843unsigned fastEmit_ARMISD_CMP_ri_Predicate_imm0_255(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6844 switch (VT.SimpleTy) { 6845 case MVT::i32: return fastEmit_ARMISD_CMP_MVT_i32_ri_Predicate_imm0_255(RetVT, Op0, Op0IsKill, imm1); 6846 default: return 0; 6847 } 6848} 6849 6850// FastEmit functions for ARMISD::CMPZ. 6851 6852unsigned fastEmit_ARMISD_CMPZ_MVT_i32_ri_Predicate_imm0_255(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6853 if (RetVT.SimpleTy != MVT::isVoid) 6854 return 0; 6855 if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) { 6856 return fastEmitInst_ri(ARM::tCMPi8, &ARM::tGPRRegClass, Op0, Op0IsKill, imm1); 6857 } 6858 return 0; 6859} 6860 6861unsigned fastEmit_ARMISD_CMPZ_ri_Predicate_imm0_255(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6862 switch (VT.SimpleTy) { 6863 case MVT::i32: return fastEmit_ARMISD_CMPZ_MVT_i32_ri_Predicate_imm0_255(RetVT, Op0, Op0IsKill, imm1); 6864 default: return 0; 6865 } 6866} 6867 6868// FastEmit functions for ARMISD::SUBS. 6869 6870unsigned fastEmit_ARMISD_SUBS_MVT_i32_ri_Predicate_imm0_255(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6871 if (RetVT.SimpleTy != MVT::i32) 6872 return 0; 6873 if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) { 6874 return fastEmitInst_ri(ARM::tSUBSi8, &ARM::tGPRRegClass, Op0, Op0IsKill, imm1); 6875 } 6876 return 0; 6877} 6878 6879unsigned fastEmit_ARMISD_SUBS_ri_Predicate_imm0_255(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6880 switch (VT.SimpleTy) { 6881 case MVT::i32: return fastEmit_ARMISD_SUBS_MVT_i32_ri_Predicate_imm0_255(RetVT, Op0, Op0IsKill, imm1); 6882 default: return 0; 6883 } 6884} 6885 6886// Top-level FastEmit function. 6887 6888unsigned fastEmit_ri_Predicate_imm0_255(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6889 switch (Opcode) { 6890 case ARMISD::CMP: return fastEmit_ARMISD_CMP_ri_Predicate_imm0_255(VT, RetVT, Op0, Op0IsKill, imm1); 6891 case ARMISD::CMPZ: return fastEmit_ARMISD_CMPZ_ri_Predicate_imm0_255(VT, RetVT, Op0, Op0IsKill, imm1); 6892 case ARMISD::SUBS: return fastEmit_ARMISD_SUBS_ri_Predicate_imm0_255(VT, RetVT, Op0, Op0IsKill, imm1); 6893 default: return 0; 6894 } 6895} 6896 6897// FastEmit functions for ARMISD::CMP. 6898 6899unsigned fastEmit_ARMISD_CMP_MVT_i32_ri_Predicate_t2_so_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6900 if (RetVT.SimpleTy != MVT::isVoid) 6901 return 0; 6902 if ((Subtarget->isThumb2())) { 6903 return fastEmitInst_ri(ARM::t2CMPri, &ARM::GPRnopcRegClass, Op0, Op0IsKill, imm1); 6904 } 6905 return 0; 6906} 6907 6908unsigned fastEmit_ARMISD_CMP_ri_Predicate_t2_so_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6909 switch (VT.SimpleTy) { 6910 case MVT::i32: return fastEmit_ARMISD_CMP_MVT_i32_ri_Predicate_t2_so_imm(RetVT, Op0, Op0IsKill, imm1); 6911 default: return 0; 6912 } 6913} 6914 6915// FastEmit functions for ARMISD::CMPZ. 6916 6917unsigned fastEmit_ARMISD_CMPZ_MVT_i32_ri_Predicate_t2_so_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6918 if (RetVT.SimpleTy != MVT::isVoid) 6919 return 0; 6920 if ((Subtarget->isThumb2())) { 6921 return fastEmitInst_ri(ARM::t2CMPri, &ARM::GPRnopcRegClass, Op0, Op0IsKill, imm1); 6922 } 6923 return 0; 6924} 6925 6926unsigned fastEmit_ARMISD_CMPZ_ri_Predicate_t2_so_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6927 switch (VT.SimpleTy) { 6928 case MVT::i32: return fastEmit_ARMISD_CMPZ_MVT_i32_ri_Predicate_t2_so_imm(RetVT, Op0, Op0IsKill, imm1); 6929 default: return 0; 6930 } 6931} 6932 6933// FastEmit functions for ARMISD::SUBS. 6934 6935unsigned fastEmit_ARMISD_SUBS_MVT_i32_ri_Predicate_t2_so_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6936 if (RetVT.SimpleTy != MVT::i32) 6937 return 0; 6938 if ((Subtarget->isThumb2())) { 6939 return fastEmitInst_ri(ARM::t2SUBSri, &ARM::rGPRRegClass, Op0, Op0IsKill, imm1); 6940 } 6941 return 0; 6942} 6943 6944unsigned fastEmit_ARMISD_SUBS_ri_Predicate_t2_so_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6945 switch (VT.SimpleTy) { 6946 case MVT::i32: return fastEmit_ARMISD_SUBS_MVT_i32_ri_Predicate_t2_so_imm(RetVT, Op0, Op0IsKill, imm1); 6947 default: return 0; 6948 } 6949} 6950 6951// FastEmit functions for ISD::ADD. 6952 6953unsigned fastEmit_ISD_ADD_MVT_i32_ri_Predicate_t2_so_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6954 if (RetVT.SimpleTy != MVT::i32) 6955 return 0; 6956 if ((Subtarget->isThumb2())) { 6957 return fastEmitInst_ri(ARM::t2ADDri, &ARM::rGPRRegClass, Op0, Op0IsKill, imm1); 6958 } 6959 return 0; 6960} 6961 6962unsigned fastEmit_ISD_ADD_ri_Predicate_t2_so_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6963 switch (VT.SimpleTy) { 6964 case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_t2_so_imm(RetVT, Op0, Op0IsKill, imm1); 6965 default: return 0; 6966 } 6967} 6968 6969// FastEmit functions for ISD::AND. 6970 6971unsigned fastEmit_ISD_AND_MVT_i32_ri_Predicate_t2_so_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6972 if (RetVT.SimpleTy != MVT::i32) 6973 return 0; 6974 if ((Subtarget->isThumb2())) { 6975 return fastEmitInst_ri(ARM::t2ANDri, &ARM::rGPRRegClass, Op0, Op0IsKill, imm1); 6976 } 6977 return 0; 6978} 6979 6980unsigned fastEmit_ISD_AND_ri_Predicate_t2_so_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6981 switch (VT.SimpleTy) { 6982 case MVT::i32: return fastEmit_ISD_AND_MVT_i32_ri_Predicate_t2_so_imm(RetVT, Op0, Op0IsKill, imm1); 6983 default: return 0; 6984 } 6985} 6986 6987// FastEmit functions for ISD::OR. 6988 6989unsigned fastEmit_ISD_OR_MVT_i32_ri_Predicate_t2_so_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6990 if (RetVT.SimpleTy != MVT::i32) 6991 return 0; 6992 if ((Subtarget->isThumb2())) { 6993 return fastEmitInst_ri(ARM::t2ORRri, &ARM::rGPRRegClass, Op0, Op0IsKill, imm1); 6994 } 6995 return 0; 6996} 6997 6998unsigned fastEmit_ISD_OR_ri_Predicate_t2_so_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 6999 switch (VT.SimpleTy) { 7000 case MVT::i32: return fastEmit_ISD_OR_MVT_i32_ri_Predicate_t2_so_imm(RetVT, Op0, Op0IsKill, imm1); 7001 default: return 0; 7002 } 7003} 7004 7005// FastEmit functions for ISD::SUB. 7006 7007unsigned fastEmit_ISD_SUB_MVT_i32_ri_Predicate_t2_so_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7008 if (RetVT.SimpleTy != MVT::i32) 7009 return 0; 7010 if ((Subtarget->isThumb2())) { 7011 return fastEmitInst_ri(ARM::t2SUBri, &ARM::rGPRRegClass, Op0, Op0IsKill, imm1); 7012 } 7013 return 0; 7014} 7015 7016unsigned fastEmit_ISD_SUB_ri_Predicate_t2_so_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7017 switch (VT.SimpleTy) { 7018 case MVT::i32: return fastEmit_ISD_SUB_MVT_i32_ri_Predicate_t2_so_imm(RetVT, Op0, Op0IsKill, imm1); 7019 default: return 0; 7020 } 7021} 7022 7023// FastEmit functions for ISD::XOR. 7024 7025unsigned fastEmit_ISD_XOR_MVT_i32_ri_Predicate_t2_so_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7026 if (RetVT.SimpleTy != MVT::i32) 7027 return 0; 7028 if ((Subtarget->isThumb2())) { 7029 return fastEmitInst_ri(ARM::t2EORri, &ARM::rGPRRegClass, Op0, Op0IsKill, imm1); 7030 } 7031 return 0; 7032} 7033 7034unsigned fastEmit_ISD_XOR_ri_Predicate_t2_so_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7035 switch (VT.SimpleTy) { 7036 case MVT::i32: return fastEmit_ISD_XOR_MVT_i32_ri_Predicate_t2_so_imm(RetVT, Op0, Op0IsKill, imm1); 7037 default: return 0; 7038 } 7039} 7040 7041// Top-level FastEmit function. 7042 7043unsigned fastEmit_ri_Predicate_t2_so_imm(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7044 switch (Opcode) { 7045 case ARMISD::CMP: return fastEmit_ARMISD_CMP_ri_Predicate_t2_so_imm(VT, RetVT, Op0, Op0IsKill, imm1); 7046 case ARMISD::CMPZ: return fastEmit_ARMISD_CMPZ_ri_Predicate_t2_so_imm(VT, RetVT, Op0, Op0IsKill, imm1); 7047 case ARMISD::SUBS: return fastEmit_ARMISD_SUBS_ri_Predicate_t2_so_imm(VT, RetVT, Op0, Op0IsKill, imm1); 7048 case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_t2_so_imm(VT, RetVT, Op0, Op0IsKill, imm1); 7049 case ISD::AND: return fastEmit_ISD_AND_ri_Predicate_t2_so_imm(VT, RetVT, Op0, Op0IsKill, imm1); 7050 case ISD::OR: return fastEmit_ISD_OR_ri_Predicate_t2_so_imm(VT, RetVT, Op0, Op0IsKill, imm1); 7051 case ISD::SUB: return fastEmit_ISD_SUB_ri_Predicate_t2_so_imm(VT, RetVT, Op0, Op0IsKill, imm1); 7052 case ISD::XOR: return fastEmit_ISD_XOR_ri_Predicate_t2_so_imm(VT, RetVT, Op0, Op0IsKill, imm1); 7053 default: return 0; 7054 } 7055} 7056 7057// FastEmit functions for ISD::ADD. 7058 7059unsigned fastEmit_ISD_ADD_MVT_i32_ri_Predicate_imm0_4095(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7060 if (RetVT.SimpleTy != MVT::i32) 7061 return 0; 7062 if ((Subtarget->isThumb2())) { 7063 return fastEmitInst_ri(ARM::t2ADDri12, &ARM::rGPRRegClass, Op0, Op0IsKill, imm1); 7064 } 7065 return 0; 7066} 7067 7068unsigned fastEmit_ISD_ADD_ri_Predicate_imm0_4095(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7069 switch (VT.SimpleTy) { 7070 case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_imm0_4095(RetVT, Op0, Op0IsKill, imm1); 7071 default: return 0; 7072 } 7073} 7074 7075// FastEmit functions for ISD::SUB. 7076 7077unsigned fastEmit_ISD_SUB_MVT_i32_ri_Predicate_imm0_4095(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7078 if (RetVT.SimpleTy != MVT::i32) 7079 return 0; 7080 if ((Subtarget->isThumb2())) { 7081 return fastEmitInst_ri(ARM::t2SUBri12, &ARM::rGPRRegClass, Op0, Op0IsKill, imm1); 7082 } 7083 return 0; 7084} 7085 7086unsigned fastEmit_ISD_SUB_ri_Predicate_imm0_4095(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7087 switch (VT.SimpleTy) { 7088 case MVT::i32: return fastEmit_ISD_SUB_MVT_i32_ri_Predicate_imm0_4095(RetVT, Op0, Op0IsKill, imm1); 7089 default: return 0; 7090 } 7091} 7092 7093// Top-level FastEmit function. 7094 7095unsigned fastEmit_ri_Predicate_imm0_4095(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7096 switch (Opcode) { 7097 case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_imm0_4095(VT, RetVT, Op0, Op0IsKill, imm1); 7098 case ISD::SUB: return fastEmit_ISD_SUB_ri_Predicate_imm0_4095(VT, RetVT, Op0, Op0IsKill, imm1); 7099 default: return 0; 7100 } 7101} 7102 7103// FastEmit functions for ISD::SHL. 7104 7105unsigned fastEmit_ISD_SHL_MVT_i32_ri_Predicate_imm1_31(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7106 if (RetVT.SimpleTy != MVT::i32) 7107 return 0; 7108 if ((Subtarget->isThumb2())) { 7109 return fastEmitInst_ri(ARM::t2LSLri, &ARM::rGPRRegClass, Op0, Op0IsKill, imm1); 7110 } 7111 return 0; 7112} 7113 7114unsigned fastEmit_ISD_SHL_ri_Predicate_imm1_31(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7115 switch (VT.SimpleTy) { 7116 case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_ri_Predicate_imm1_31(RetVT, Op0, Op0IsKill, imm1); 7117 default: return 0; 7118 } 7119} 7120 7121// Top-level FastEmit function. 7122 7123unsigned fastEmit_ri_Predicate_imm1_31(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7124 switch (Opcode) { 7125 case ISD::SHL: return fastEmit_ISD_SHL_ri_Predicate_imm1_31(VT, RetVT, Op0, Op0IsKill, imm1); 7126 default: return 0; 7127 } 7128} 7129 7130// FastEmit functions for ARMISD::VSHLIMM. 7131 7132unsigned fastEmit_ARMISD_VSHLIMM_MVT_v4i32_ri_Predicate_imm0_31(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7133 if (RetVT.SimpleTy != MVT::v4i32) 7134 return 0; 7135 if ((Subtarget->hasMVEIntegerOps())) { 7136 return fastEmitInst_ri(ARM::MVE_VSHL_immi32, &ARM::MQPRRegClass, Op0, Op0IsKill, imm1); 7137 } 7138 return 0; 7139} 7140 7141unsigned fastEmit_ARMISD_VSHLIMM_ri_Predicate_imm0_31(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7142 switch (VT.SimpleTy) { 7143 case MVT::v4i32: return fastEmit_ARMISD_VSHLIMM_MVT_v4i32_ri_Predicate_imm0_31(RetVT, Op0, Op0IsKill, imm1); 7144 default: return 0; 7145 } 7146} 7147 7148// FastEmit functions for ARMISD::VSHRsIMM. 7149 7150unsigned fastEmit_ARMISD_VSHRsIMM_MVT_v4i32_ri_Predicate_imm0_31(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7151 if (RetVT.SimpleTy != MVT::v4i32) 7152 return 0; 7153 if ((Subtarget->hasMVEIntegerOps())) { 7154 return fastEmitInst_ri(ARM::MVE_VSHR_imms32, &ARM::MQPRRegClass, Op0, Op0IsKill, imm1); 7155 } 7156 return 0; 7157} 7158 7159unsigned fastEmit_ARMISD_VSHRsIMM_ri_Predicate_imm0_31(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7160 switch (VT.SimpleTy) { 7161 case MVT::v4i32: return fastEmit_ARMISD_VSHRsIMM_MVT_v4i32_ri_Predicate_imm0_31(RetVT, Op0, Op0IsKill, imm1); 7162 default: return 0; 7163 } 7164} 7165 7166// FastEmit functions for ARMISD::VSHRuIMM. 7167 7168unsigned fastEmit_ARMISD_VSHRuIMM_MVT_v4i32_ri_Predicate_imm0_31(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7169 if (RetVT.SimpleTy != MVT::v4i32) 7170 return 0; 7171 if ((Subtarget->hasMVEIntegerOps())) { 7172 return fastEmitInst_ri(ARM::MVE_VSHR_immu32, &ARM::MQPRRegClass, Op0, Op0IsKill, imm1); 7173 } 7174 return 0; 7175} 7176 7177unsigned fastEmit_ARMISD_VSHRuIMM_ri_Predicate_imm0_31(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7178 switch (VT.SimpleTy) { 7179 case MVT::v4i32: return fastEmit_ARMISD_VSHRuIMM_MVT_v4i32_ri_Predicate_imm0_31(RetVT, Op0, Op0IsKill, imm1); 7180 default: return 0; 7181 } 7182} 7183 7184// FastEmit functions for ISD::ROTR. 7185 7186unsigned fastEmit_ISD_ROTR_MVT_i32_ri_Predicate_imm0_31(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7187 if (RetVT.SimpleTy != MVT::i32) 7188 return 0; 7189 if ((Subtarget->isThumb2())) { 7190 return fastEmitInst_ri(ARM::t2RORri, &ARM::rGPRRegClass, Op0, Op0IsKill, imm1); 7191 } 7192 return 0; 7193} 7194 7195unsigned fastEmit_ISD_ROTR_ri_Predicate_imm0_31(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7196 switch (VT.SimpleTy) { 7197 case MVT::i32: return fastEmit_ISD_ROTR_MVT_i32_ri_Predicate_imm0_31(RetVT, Op0, Op0IsKill, imm1); 7198 default: return 0; 7199 } 7200} 7201 7202// Top-level FastEmit function. 7203 7204unsigned fastEmit_ri_Predicate_imm0_31(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7205 switch (Opcode) { 7206 case ARMISD::VSHLIMM: return fastEmit_ARMISD_VSHLIMM_ri_Predicate_imm0_31(VT, RetVT, Op0, Op0IsKill, imm1); 7207 case ARMISD::VSHRsIMM: return fastEmit_ARMISD_VSHRsIMM_ri_Predicate_imm0_31(VT, RetVT, Op0, Op0IsKill, imm1); 7208 case ARMISD::VSHRuIMM: return fastEmit_ARMISD_VSHRuIMM_ri_Predicate_imm0_31(VT, RetVT, Op0, Op0IsKill, imm1); 7209 case ISD::ROTR: return fastEmit_ISD_ROTR_ri_Predicate_imm0_31(VT, RetVT, Op0, Op0IsKill, imm1); 7210 default: return 0; 7211 } 7212} 7213 7214// FastEmit functions for ARMISD::VQRSHRNsIMM. 7215 7216unsigned fastEmit_ARMISD_VQRSHRNsIMM_MVT_v8i16_ri_Predicate_shr_imm8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7217 if (RetVT.SimpleTy != MVT::v8i8) 7218 return 0; 7219 if ((Subtarget->hasNEON())) { 7220 return fastEmitInst_ri(ARM::VQRSHRNsv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 7221 } 7222 return 0; 7223} 7224 7225unsigned fastEmit_ARMISD_VQRSHRNsIMM_ri_Predicate_shr_imm8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7226 switch (VT.SimpleTy) { 7227 case MVT::v8i16: return fastEmit_ARMISD_VQRSHRNsIMM_MVT_v8i16_ri_Predicate_shr_imm8(RetVT, Op0, Op0IsKill, imm1); 7228 default: return 0; 7229 } 7230} 7231 7232// FastEmit functions for ARMISD::VQRSHRNsuIMM. 7233 7234unsigned fastEmit_ARMISD_VQRSHRNsuIMM_MVT_v8i16_ri_Predicate_shr_imm8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7235 if (RetVT.SimpleTy != MVT::v8i8) 7236 return 0; 7237 if ((Subtarget->hasNEON())) { 7238 return fastEmitInst_ri(ARM::VQRSHRUNv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 7239 } 7240 return 0; 7241} 7242 7243unsigned fastEmit_ARMISD_VQRSHRNsuIMM_ri_Predicate_shr_imm8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7244 switch (VT.SimpleTy) { 7245 case MVT::v8i16: return fastEmit_ARMISD_VQRSHRNsuIMM_MVT_v8i16_ri_Predicate_shr_imm8(RetVT, Op0, Op0IsKill, imm1); 7246 default: return 0; 7247 } 7248} 7249 7250// FastEmit functions for ARMISD::VQRSHRNuIMM. 7251 7252unsigned fastEmit_ARMISD_VQRSHRNuIMM_MVT_v8i16_ri_Predicate_shr_imm8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7253 if (RetVT.SimpleTy != MVT::v8i8) 7254 return 0; 7255 if ((Subtarget->hasNEON())) { 7256 return fastEmitInst_ri(ARM::VQRSHRNuv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 7257 } 7258 return 0; 7259} 7260 7261unsigned fastEmit_ARMISD_VQRSHRNuIMM_ri_Predicate_shr_imm8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7262 switch (VT.SimpleTy) { 7263 case MVT::v8i16: return fastEmit_ARMISD_VQRSHRNuIMM_MVT_v8i16_ri_Predicate_shr_imm8(RetVT, Op0, Op0IsKill, imm1); 7264 default: return 0; 7265 } 7266} 7267 7268// FastEmit functions for ARMISD::VQSHRNsIMM. 7269 7270unsigned fastEmit_ARMISD_VQSHRNsIMM_MVT_v8i16_ri_Predicate_shr_imm8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7271 if (RetVT.SimpleTy != MVT::v8i8) 7272 return 0; 7273 if ((Subtarget->hasNEON())) { 7274 return fastEmitInst_ri(ARM::VQSHRNsv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 7275 } 7276 return 0; 7277} 7278 7279unsigned fastEmit_ARMISD_VQSHRNsIMM_ri_Predicate_shr_imm8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7280 switch (VT.SimpleTy) { 7281 case MVT::v8i16: return fastEmit_ARMISD_VQSHRNsIMM_MVT_v8i16_ri_Predicate_shr_imm8(RetVT, Op0, Op0IsKill, imm1); 7282 default: return 0; 7283 } 7284} 7285 7286// FastEmit functions for ARMISD::VQSHRNsuIMM. 7287 7288unsigned fastEmit_ARMISD_VQSHRNsuIMM_MVT_v8i16_ri_Predicate_shr_imm8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7289 if (RetVT.SimpleTy != MVT::v8i8) 7290 return 0; 7291 if ((Subtarget->hasNEON())) { 7292 return fastEmitInst_ri(ARM::VQSHRUNv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 7293 } 7294 return 0; 7295} 7296 7297unsigned fastEmit_ARMISD_VQSHRNsuIMM_ri_Predicate_shr_imm8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7298 switch (VT.SimpleTy) { 7299 case MVT::v8i16: return fastEmit_ARMISD_VQSHRNsuIMM_MVT_v8i16_ri_Predicate_shr_imm8(RetVT, Op0, Op0IsKill, imm1); 7300 default: return 0; 7301 } 7302} 7303 7304// FastEmit functions for ARMISD::VQSHRNuIMM. 7305 7306unsigned fastEmit_ARMISD_VQSHRNuIMM_MVT_v8i16_ri_Predicate_shr_imm8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7307 if (RetVT.SimpleTy != MVT::v8i8) 7308 return 0; 7309 if ((Subtarget->hasNEON())) { 7310 return fastEmitInst_ri(ARM::VQSHRNuv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 7311 } 7312 return 0; 7313} 7314 7315unsigned fastEmit_ARMISD_VQSHRNuIMM_ri_Predicate_shr_imm8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7316 switch (VT.SimpleTy) { 7317 case MVT::v8i16: return fastEmit_ARMISD_VQSHRNuIMM_MVT_v8i16_ri_Predicate_shr_imm8(RetVT, Op0, Op0IsKill, imm1); 7318 default: return 0; 7319 } 7320} 7321 7322// FastEmit functions for ARMISD::VRSHRNIMM. 7323 7324unsigned fastEmit_ARMISD_VRSHRNIMM_MVT_v8i16_ri_Predicate_shr_imm8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7325 if (RetVT.SimpleTy != MVT::v8i8) 7326 return 0; 7327 if ((Subtarget->hasNEON())) { 7328 return fastEmitInst_ri(ARM::VRSHRNv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 7329 } 7330 return 0; 7331} 7332 7333unsigned fastEmit_ARMISD_VRSHRNIMM_ri_Predicate_shr_imm8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7334 switch (VT.SimpleTy) { 7335 case MVT::v8i16: return fastEmit_ARMISD_VRSHRNIMM_MVT_v8i16_ri_Predicate_shr_imm8(RetVT, Op0, Op0IsKill, imm1); 7336 default: return 0; 7337 } 7338} 7339 7340// Top-level FastEmit function. 7341 7342unsigned fastEmit_ri_Predicate_shr_imm8(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7343 switch (Opcode) { 7344 case ARMISD::VQRSHRNsIMM: return fastEmit_ARMISD_VQRSHRNsIMM_ri_Predicate_shr_imm8(VT, RetVT, Op0, Op0IsKill, imm1); 7345 case ARMISD::VQRSHRNsuIMM: return fastEmit_ARMISD_VQRSHRNsuIMM_ri_Predicate_shr_imm8(VT, RetVT, Op0, Op0IsKill, imm1); 7346 case ARMISD::VQRSHRNuIMM: return fastEmit_ARMISD_VQRSHRNuIMM_ri_Predicate_shr_imm8(VT, RetVT, Op0, Op0IsKill, imm1); 7347 case ARMISD::VQSHRNsIMM: return fastEmit_ARMISD_VQSHRNsIMM_ri_Predicate_shr_imm8(VT, RetVT, Op0, Op0IsKill, imm1); 7348 case ARMISD::VQSHRNsuIMM: return fastEmit_ARMISD_VQSHRNsuIMM_ri_Predicate_shr_imm8(VT, RetVT, Op0, Op0IsKill, imm1); 7349 case ARMISD::VQSHRNuIMM: return fastEmit_ARMISD_VQSHRNuIMM_ri_Predicate_shr_imm8(VT, RetVT, Op0, Op0IsKill, imm1); 7350 case ARMISD::VRSHRNIMM: return fastEmit_ARMISD_VRSHRNIMM_ri_Predicate_shr_imm8(VT, RetVT, Op0, Op0IsKill, imm1); 7351 default: return 0; 7352 } 7353} 7354 7355// FastEmit functions for ARMISD::VQRSHRNsIMM. 7356 7357unsigned fastEmit_ARMISD_VQRSHRNsIMM_MVT_v4i32_ri_Predicate_shr_imm16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7358 if (RetVT.SimpleTy != MVT::v4i16) 7359 return 0; 7360 if ((Subtarget->hasNEON())) { 7361 return fastEmitInst_ri(ARM::VQRSHRNsv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 7362 } 7363 return 0; 7364} 7365 7366unsigned fastEmit_ARMISD_VQRSHRNsIMM_ri_Predicate_shr_imm16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7367 switch (VT.SimpleTy) { 7368 case MVT::v4i32: return fastEmit_ARMISD_VQRSHRNsIMM_MVT_v4i32_ri_Predicate_shr_imm16(RetVT, Op0, Op0IsKill, imm1); 7369 default: return 0; 7370 } 7371} 7372 7373// FastEmit functions for ARMISD::VQRSHRNsuIMM. 7374 7375unsigned fastEmit_ARMISD_VQRSHRNsuIMM_MVT_v4i32_ri_Predicate_shr_imm16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7376 if (RetVT.SimpleTy != MVT::v4i16) 7377 return 0; 7378 if ((Subtarget->hasNEON())) { 7379 return fastEmitInst_ri(ARM::VQRSHRUNv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 7380 } 7381 return 0; 7382} 7383 7384unsigned fastEmit_ARMISD_VQRSHRNsuIMM_ri_Predicate_shr_imm16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7385 switch (VT.SimpleTy) { 7386 case MVT::v4i32: return fastEmit_ARMISD_VQRSHRNsuIMM_MVT_v4i32_ri_Predicate_shr_imm16(RetVT, Op0, Op0IsKill, imm1); 7387 default: return 0; 7388 } 7389} 7390 7391// FastEmit functions for ARMISD::VQRSHRNuIMM. 7392 7393unsigned fastEmit_ARMISD_VQRSHRNuIMM_MVT_v4i32_ri_Predicate_shr_imm16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7394 if (RetVT.SimpleTy != MVT::v4i16) 7395 return 0; 7396 if ((Subtarget->hasNEON())) { 7397 return fastEmitInst_ri(ARM::VQRSHRNuv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 7398 } 7399 return 0; 7400} 7401 7402unsigned fastEmit_ARMISD_VQRSHRNuIMM_ri_Predicate_shr_imm16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7403 switch (VT.SimpleTy) { 7404 case MVT::v4i32: return fastEmit_ARMISD_VQRSHRNuIMM_MVT_v4i32_ri_Predicate_shr_imm16(RetVT, Op0, Op0IsKill, imm1); 7405 default: return 0; 7406 } 7407} 7408 7409// FastEmit functions for ARMISD::VQSHRNsIMM. 7410 7411unsigned fastEmit_ARMISD_VQSHRNsIMM_MVT_v4i32_ri_Predicate_shr_imm16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7412 if (RetVT.SimpleTy != MVT::v4i16) 7413 return 0; 7414 if ((Subtarget->hasNEON())) { 7415 return fastEmitInst_ri(ARM::VQSHRNsv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 7416 } 7417 return 0; 7418} 7419 7420unsigned fastEmit_ARMISD_VQSHRNsIMM_ri_Predicate_shr_imm16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7421 switch (VT.SimpleTy) { 7422 case MVT::v4i32: return fastEmit_ARMISD_VQSHRNsIMM_MVT_v4i32_ri_Predicate_shr_imm16(RetVT, Op0, Op0IsKill, imm1); 7423 default: return 0; 7424 } 7425} 7426 7427// FastEmit functions for ARMISD::VQSHRNsuIMM. 7428 7429unsigned fastEmit_ARMISD_VQSHRNsuIMM_MVT_v4i32_ri_Predicate_shr_imm16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7430 if (RetVT.SimpleTy != MVT::v4i16) 7431 return 0; 7432 if ((Subtarget->hasNEON())) { 7433 return fastEmitInst_ri(ARM::VQSHRUNv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 7434 } 7435 return 0; 7436} 7437 7438unsigned fastEmit_ARMISD_VQSHRNsuIMM_ri_Predicate_shr_imm16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7439 switch (VT.SimpleTy) { 7440 case MVT::v4i32: return fastEmit_ARMISD_VQSHRNsuIMM_MVT_v4i32_ri_Predicate_shr_imm16(RetVT, Op0, Op0IsKill, imm1); 7441 default: return 0; 7442 } 7443} 7444 7445// FastEmit functions for ARMISD::VQSHRNuIMM. 7446 7447unsigned fastEmit_ARMISD_VQSHRNuIMM_MVT_v4i32_ri_Predicate_shr_imm16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7448 if (RetVT.SimpleTy != MVT::v4i16) 7449 return 0; 7450 if ((Subtarget->hasNEON())) { 7451 return fastEmitInst_ri(ARM::VQSHRNuv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 7452 } 7453 return 0; 7454} 7455 7456unsigned fastEmit_ARMISD_VQSHRNuIMM_ri_Predicate_shr_imm16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7457 switch (VT.SimpleTy) { 7458 case MVT::v4i32: return fastEmit_ARMISD_VQSHRNuIMM_MVT_v4i32_ri_Predicate_shr_imm16(RetVT, Op0, Op0IsKill, imm1); 7459 default: return 0; 7460 } 7461} 7462 7463// FastEmit functions for ARMISD::VRSHRNIMM. 7464 7465unsigned fastEmit_ARMISD_VRSHRNIMM_MVT_v4i32_ri_Predicate_shr_imm16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7466 if (RetVT.SimpleTy != MVT::v4i16) 7467 return 0; 7468 if ((Subtarget->hasNEON())) { 7469 return fastEmitInst_ri(ARM::VRSHRNv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 7470 } 7471 return 0; 7472} 7473 7474unsigned fastEmit_ARMISD_VRSHRNIMM_ri_Predicate_shr_imm16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7475 switch (VT.SimpleTy) { 7476 case MVT::v4i32: return fastEmit_ARMISD_VRSHRNIMM_MVT_v4i32_ri_Predicate_shr_imm16(RetVT, Op0, Op0IsKill, imm1); 7477 default: return 0; 7478 } 7479} 7480 7481// Top-level FastEmit function. 7482 7483unsigned fastEmit_ri_Predicate_shr_imm16(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7484 switch (Opcode) { 7485 case ARMISD::VQRSHRNsIMM: return fastEmit_ARMISD_VQRSHRNsIMM_ri_Predicate_shr_imm16(VT, RetVT, Op0, Op0IsKill, imm1); 7486 case ARMISD::VQRSHRNsuIMM: return fastEmit_ARMISD_VQRSHRNsuIMM_ri_Predicate_shr_imm16(VT, RetVT, Op0, Op0IsKill, imm1); 7487 case ARMISD::VQRSHRNuIMM: return fastEmit_ARMISD_VQRSHRNuIMM_ri_Predicate_shr_imm16(VT, RetVT, Op0, Op0IsKill, imm1); 7488 case ARMISD::VQSHRNsIMM: return fastEmit_ARMISD_VQSHRNsIMM_ri_Predicate_shr_imm16(VT, RetVT, Op0, Op0IsKill, imm1); 7489 case ARMISD::VQSHRNsuIMM: return fastEmit_ARMISD_VQSHRNsuIMM_ri_Predicate_shr_imm16(VT, RetVT, Op0, Op0IsKill, imm1); 7490 case ARMISD::VQSHRNuIMM: return fastEmit_ARMISD_VQSHRNuIMM_ri_Predicate_shr_imm16(VT, RetVT, Op0, Op0IsKill, imm1); 7491 case ARMISD::VRSHRNIMM: return fastEmit_ARMISD_VRSHRNIMM_ri_Predicate_shr_imm16(VT, RetVT, Op0, Op0IsKill, imm1); 7492 default: return 0; 7493 } 7494} 7495 7496// FastEmit functions for ARMISD::VQRSHRNsIMM. 7497 7498unsigned fastEmit_ARMISD_VQRSHRNsIMM_MVT_v2i64_ri_Predicate_shr_imm32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7499 if (RetVT.SimpleTy != MVT::v2i32) 7500 return 0; 7501 if ((Subtarget->hasNEON())) { 7502 return fastEmitInst_ri(ARM::VQRSHRNsv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 7503 } 7504 return 0; 7505} 7506 7507unsigned fastEmit_ARMISD_VQRSHRNsIMM_ri_Predicate_shr_imm32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7508 switch (VT.SimpleTy) { 7509 case MVT::v2i64: return fastEmit_ARMISD_VQRSHRNsIMM_MVT_v2i64_ri_Predicate_shr_imm32(RetVT, Op0, Op0IsKill, imm1); 7510 default: return 0; 7511 } 7512} 7513 7514// FastEmit functions for ARMISD::VQRSHRNsuIMM. 7515 7516unsigned fastEmit_ARMISD_VQRSHRNsuIMM_MVT_v2i64_ri_Predicate_shr_imm32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7517 if (RetVT.SimpleTy != MVT::v2i32) 7518 return 0; 7519 if ((Subtarget->hasNEON())) { 7520 return fastEmitInst_ri(ARM::VQRSHRUNv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 7521 } 7522 return 0; 7523} 7524 7525unsigned fastEmit_ARMISD_VQRSHRNsuIMM_ri_Predicate_shr_imm32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7526 switch (VT.SimpleTy) { 7527 case MVT::v2i64: return fastEmit_ARMISD_VQRSHRNsuIMM_MVT_v2i64_ri_Predicate_shr_imm32(RetVT, Op0, Op0IsKill, imm1); 7528 default: return 0; 7529 } 7530} 7531 7532// FastEmit functions for ARMISD::VQRSHRNuIMM. 7533 7534unsigned fastEmit_ARMISD_VQRSHRNuIMM_MVT_v2i64_ri_Predicate_shr_imm32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7535 if (RetVT.SimpleTy != MVT::v2i32) 7536 return 0; 7537 if ((Subtarget->hasNEON())) { 7538 return fastEmitInst_ri(ARM::VQRSHRNuv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 7539 } 7540 return 0; 7541} 7542 7543unsigned fastEmit_ARMISD_VQRSHRNuIMM_ri_Predicate_shr_imm32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7544 switch (VT.SimpleTy) { 7545 case MVT::v2i64: return fastEmit_ARMISD_VQRSHRNuIMM_MVT_v2i64_ri_Predicate_shr_imm32(RetVT, Op0, Op0IsKill, imm1); 7546 default: return 0; 7547 } 7548} 7549 7550// FastEmit functions for ARMISD::VQSHRNsIMM. 7551 7552unsigned fastEmit_ARMISD_VQSHRNsIMM_MVT_v2i64_ri_Predicate_shr_imm32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7553 if (RetVT.SimpleTy != MVT::v2i32) 7554 return 0; 7555 if ((Subtarget->hasNEON())) { 7556 return fastEmitInst_ri(ARM::VQSHRNsv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 7557 } 7558 return 0; 7559} 7560 7561unsigned fastEmit_ARMISD_VQSHRNsIMM_ri_Predicate_shr_imm32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7562 switch (VT.SimpleTy) { 7563 case MVT::v2i64: return fastEmit_ARMISD_VQSHRNsIMM_MVT_v2i64_ri_Predicate_shr_imm32(RetVT, Op0, Op0IsKill, imm1); 7564 default: return 0; 7565 } 7566} 7567 7568// FastEmit functions for ARMISD::VQSHRNsuIMM. 7569 7570unsigned fastEmit_ARMISD_VQSHRNsuIMM_MVT_v2i64_ri_Predicate_shr_imm32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7571 if (RetVT.SimpleTy != MVT::v2i32) 7572 return 0; 7573 if ((Subtarget->hasNEON())) { 7574 return fastEmitInst_ri(ARM::VQSHRUNv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 7575 } 7576 return 0; 7577} 7578 7579unsigned fastEmit_ARMISD_VQSHRNsuIMM_ri_Predicate_shr_imm32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7580 switch (VT.SimpleTy) { 7581 case MVT::v2i64: return fastEmit_ARMISD_VQSHRNsuIMM_MVT_v2i64_ri_Predicate_shr_imm32(RetVT, Op0, Op0IsKill, imm1); 7582 default: return 0; 7583 } 7584} 7585 7586// FastEmit functions for ARMISD::VQSHRNuIMM. 7587 7588unsigned fastEmit_ARMISD_VQSHRNuIMM_MVT_v2i64_ri_Predicate_shr_imm32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7589 if (RetVT.SimpleTy != MVT::v2i32) 7590 return 0; 7591 if ((Subtarget->hasNEON())) { 7592 return fastEmitInst_ri(ARM::VQSHRNuv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 7593 } 7594 return 0; 7595} 7596 7597unsigned fastEmit_ARMISD_VQSHRNuIMM_ri_Predicate_shr_imm32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7598 switch (VT.SimpleTy) { 7599 case MVT::v2i64: return fastEmit_ARMISD_VQSHRNuIMM_MVT_v2i64_ri_Predicate_shr_imm32(RetVT, Op0, Op0IsKill, imm1); 7600 default: return 0; 7601 } 7602} 7603 7604// FastEmit functions for ARMISD::VRSHRNIMM. 7605 7606unsigned fastEmit_ARMISD_VRSHRNIMM_MVT_v2i64_ri_Predicate_shr_imm32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7607 if (RetVT.SimpleTy != MVT::v2i32) 7608 return 0; 7609 if ((Subtarget->hasNEON())) { 7610 return fastEmitInst_ri(ARM::VRSHRNv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1); 7611 } 7612 return 0; 7613} 7614 7615unsigned fastEmit_ARMISD_VRSHRNIMM_ri_Predicate_shr_imm32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7616 switch (VT.SimpleTy) { 7617 case MVT::v2i64: return fastEmit_ARMISD_VRSHRNIMM_MVT_v2i64_ri_Predicate_shr_imm32(RetVT, Op0, Op0IsKill, imm1); 7618 default: return 0; 7619 } 7620} 7621 7622// Top-level FastEmit function. 7623 7624unsigned fastEmit_ri_Predicate_shr_imm32(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7625 switch (Opcode) { 7626 case ARMISD::VQRSHRNsIMM: return fastEmit_ARMISD_VQRSHRNsIMM_ri_Predicate_shr_imm32(VT, RetVT, Op0, Op0IsKill, imm1); 7627 case ARMISD::VQRSHRNsuIMM: return fastEmit_ARMISD_VQRSHRNsuIMM_ri_Predicate_shr_imm32(VT, RetVT, Op0, Op0IsKill, imm1); 7628 case ARMISD::VQRSHRNuIMM: return fastEmit_ARMISD_VQRSHRNuIMM_ri_Predicate_shr_imm32(VT, RetVT, Op0, Op0IsKill, imm1); 7629 case ARMISD::VQSHRNsIMM: return fastEmit_ARMISD_VQSHRNsIMM_ri_Predicate_shr_imm32(VT, RetVT, Op0, Op0IsKill, imm1); 7630 case ARMISD::VQSHRNsuIMM: return fastEmit_ARMISD_VQSHRNsuIMM_ri_Predicate_shr_imm32(VT, RetVT, Op0, Op0IsKill, imm1); 7631 case ARMISD::VQSHRNuIMM: return fastEmit_ARMISD_VQSHRNuIMM_ri_Predicate_shr_imm32(VT, RetVT, Op0, Op0IsKill, imm1); 7632 case ARMISD::VRSHRNIMM: return fastEmit_ARMISD_VRSHRNIMM_ri_Predicate_shr_imm32(VT, RetVT, Op0, Op0IsKill, imm1); 7633 default: return 0; 7634 } 7635} 7636 7637// FastEmit functions for ARMISD::VDUPLANE. 7638 7639unsigned fastEmit_ARMISD_VDUPLANE_MVT_v8i8_ri_Predicate_VectorIndex32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7640 if (RetVT.SimpleTy != MVT::v16i8) 7641 return 0; 7642 if ((Subtarget->hasNEON())) { 7643 return fastEmitInst_ri(ARM::VDUPLN8q, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 7644 } 7645 return 0; 7646} 7647 7648unsigned fastEmit_ARMISD_VDUPLANE_MVT_v4i16_ri_Predicate_VectorIndex32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7649 if (RetVT.SimpleTy != MVT::v8i16) 7650 return 0; 7651 if ((Subtarget->hasNEON())) { 7652 return fastEmitInst_ri(ARM::VDUPLN16q, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 7653 } 7654 return 0; 7655} 7656 7657unsigned fastEmit_ARMISD_VDUPLANE_MVT_v2i32_ri_Predicate_VectorIndex32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7658 if (RetVT.SimpleTy != MVT::v4i32) 7659 return 0; 7660 if ((Subtarget->hasNEON())) { 7661 return fastEmitInst_ri(ARM::VDUPLN32q, &ARM::QPRRegClass, Op0, Op0IsKill, imm1); 7662 } 7663 return 0; 7664} 7665 7666unsigned fastEmit_ARMISD_VDUPLANE_ri_Predicate_VectorIndex32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7667 switch (VT.SimpleTy) { 7668 case MVT::v8i8: return fastEmit_ARMISD_VDUPLANE_MVT_v8i8_ri_Predicate_VectorIndex32(RetVT, Op0, Op0IsKill, imm1); 7669 case MVT::v4i16: return fastEmit_ARMISD_VDUPLANE_MVT_v4i16_ri_Predicate_VectorIndex32(RetVT, Op0, Op0IsKill, imm1); 7670 case MVT::v2i32: return fastEmit_ARMISD_VDUPLANE_MVT_v2i32_ri_Predicate_VectorIndex32(RetVT, Op0, Op0IsKill, imm1); 7671 default: return 0; 7672 } 7673} 7674 7675// Top-level FastEmit function. 7676 7677unsigned fastEmit_ri_Predicate_VectorIndex32(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7678 switch (Opcode) { 7679 case ARMISD::VDUPLANE: return fastEmit_ARMISD_VDUPLANE_ri_Predicate_VectorIndex32(VT, RetVT, Op0, Op0IsKill, imm1); 7680 default: return 0; 7681 } 7682} 7683 7684// FastEmit functions for ARMISD::VSHLIMM. 7685 7686unsigned fastEmit_ARMISD_VSHLIMM_MVT_v8i16_ri_Predicate_imm0_15(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7687 if (RetVT.SimpleTy != MVT::v8i16) 7688 return 0; 7689 if ((Subtarget->hasMVEIntegerOps())) { 7690 return fastEmitInst_ri(ARM::MVE_VSHL_immi16, &ARM::MQPRRegClass, Op0, Op0IsKill, imm1); 7691 } 7692 return 0; 7693} 7694 7695unsigned fastEmit_ARMISD_VSHLIMM_ri_Predicate_imm0_15(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7696 switch (VT.SimpleTy) { 7697 case MVT::v8i16: return fastEmit_ARMISD_VSHLIMM_MVT_v8i16_ri_Predicate_imm0_15(RetVT, Op0, Op0IsKill, imm1); 7698 default: return 0; 7699 } 7700} 7701 7702// FastEmit functions for ARMISD::VSHRsIMM. 7703 7704unsigned fastEmit_ARMISD_VSHRsIMM_MVT_v8i16_ri_Predicate_imm0_15(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7705 if (RetVT.SimpleTy != MVT::v8i16) 7706 return 0; 7707 if ((Subtarget->hasMVEIntegerOps())) { 7708 return fastEmitInst_ri(ARM::MVE_VSHR_imms16, &ARM::MQPRRegClass, Op0, Op0IsKill, imm1); 7709 } 7710 return 0; 7711} 7712 7713unsigned fastEmit_ARMISD_VSHRsIMM_ri_Predicate_imm0_15(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7714 switch (VT.SimpleTy) { 7715 case MVT::v8i16: return fastEmit_ARMISD_VSHRsIMM_MVT_v8i16_ri_Predicate_imm0_15(RetVT, Op0, Op0IsKill, imm1); 7716 default: return 0; 7717 } 7718} 7719 7720// FastEmit functions for ARMISD::VSHRuIMM. 7721 7722unsigned fastEmit_ARMISD_VSHRuIMM_MVT_v8i16_ri_Predicate_imm0_15(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7723 if (RetVT.SimpleTy != MVT::v8i16) 7724 return 0; 7725 if ((Subtarget->hasMVEIntegerOps())) { 7726 return fastEmitInst_ri(ARM::MVE_VSHR_immu16, &ARM::MQPRRegClass, Op0, Op0IsKill, imm1); 7727 } 7728 return 0; 7729} 7730 7731unsigned fastEmit_ARMISD_VSHRuIMM_ri_Predicate_imm0_15(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7732 switch (VT.SimpleTy) { 7733 case MVT::v8i16: return fastEmit_ARMISD_VSHRuIMM_MVT_v8i16_ri_Predicate_imm0_15(RetVT, Op0, Op0IsKill, imm1); 7734 default: return 0; 7735 } 7736} 7737 7738// Top-level FastEmit function. 7739 7740unsigned fastEmit_ri_Predicate_imm0_15(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 7741 switch (Opcode) { 7742 case ARMISD::VSHLIMM: return fastEmit_ARMISD_VSHLIMM_ri_Predicate_imm0_15(VT, RetVT, Op0, Op0IsKill, imm1); 7743 case ARMISD::VSHRsIMM: return fastEmit_ARMISD_VSHRsIMM_ri_Predicate_imm0_15(VT, RetVT, Op0, Op0IsKill, imm1); 7744 case ARMISD::VSHRuIMM: return fastEmit_ARMISD_VSHRuIMM_ri_Predicate_imm0_15(VT, RetVT, Op0, Op0IsKill, imm1); 7745 default: return 0; 7746 } 7747} 7748 7749// FastEmit functions for ISD::Constant. 7750 7751unsigned fastEmit_ISD_Constant_MVT_i32_i(MVT RetVT, uint64_t imm0) { 7752 if (RetVT.SimpleTy != MVT::i32) 7753 return 0; 7754 if ((Subtarget->isThumb()) && (Subtarget->useMovt())) { 7755 return fastEmitInst_i(ARM::t2MOVi32imm, &ARM::rGPRRegClass, imm0); 7756 } 7757 return 0; 7758} 7759 7760unsigned fastEmit_ISD_Constant_i(MVT VT, MVT RetVT, uint64_t imm0) { 7761 switch (VT.SimpleTy) { 7762 case MVT::i32: return fastEmit_ISD_Constant_MVT_i32_i(RetVT, imm0); 7763 default: return 0; 7764 } 7765} 7766 7767// Top-level FastEmit function. 7768 7769unsigned fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t imm0) override { 7770 switch (Opcode) { 7771 case ISD::Constant: return fastEmit_ISD_Constant_i(VT, RetVT, imm0); 7772 default: return 0; 7773 } 7774} 7775 7776