1 /**************************************************************************//**
2 * @file cmsis_iccarm.h
3 * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
4 * @version V5.2.0
5 * @date 28. January 2020
6 ******************************************************************************/
7
8 //------------------------------------------------------------------------------
9 //
10 // Copyright (c) 2017-2019 IAR Systems
11 // Copyright (c) 2017-2019 Arm Limited. All rights reserved.
12 //
13 // SPDX-License-Identifier: Apache-2.0
14 //
15 // Licensed under the Apache License, Version 2.0 (the "License")
16 // you may not use this file except in compliance with the License.
17 // You may obtain a copy of the License at
18 // http://www.apache.org/licenses/LICENSE-2.0
19 //
20 // Unless required by applicable law or agreed to in writing, software
21 // distributed under the License is distributed on an "AS IS" BASIS,
22 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 // See the License for the specific language governing permissions and
24 // limitations under the License.
25 //
26 //------------------------------------------------------------------------------
27
28
29 #ifndef __CMSIS_ICCARM_H__
30 #define __CMSIS_ICCARM_H__
31
32 #ifndef __ICCARM__
33 #error This file should only be compiled by ICCARM
34 #endif
35
36 #pragma system_include
37
38 #define __IAR_FT _Pragma("inline=forced") __intrinsic
39
40 #if (__VER__ >= 8000000)
41 #define __ICCARM_V8 1
42 #else
43 #define __ICCARM_V8 0
44 #endif
45
46 #ifndef __ALIGNED
47 #if __ICCARM_V8
48 #define __ALIGNED(x) __attribute__((aligned(x)))
49 #elif (__VER__ >= 7080000)
50 /* Needs IAR language extensions */
51 #define __ALIGNED(x) __attribute__((aligned(x)))
52 #else
53 #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
54 #define __ALIGNED(x)
55 #endif
56 #endif
57
58
59 /* Define compiler macros for CPU architecture, used in CMSIS 5.
60 */
61 #if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
62 /* Macros already defined */
63 #else
64 #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
65 #define __ARM_ARCH_8M_MAIN__ 1
66 #elif defined(__ARM8M_BASELINE__)
67 #define __ARM_ARCH_8M_BASE__ 1
68 #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
69 #if __ARM_ARCH == 6
70 #define __ARM_ARCH_6M__ 1
71 #elif __ARM_ARCH == 7
72 #if __ARM_FEATURE_DSP
73 #define __ARM_ARCH_7EM__ 1
74 #else
75 #define __ARM_ARCH_7M__ 1
76 #endif
77 #endif /* __ARM_ARCH */
78 #endif /* __ARM_ARCH_PROFILE == 'M' */
79 #endif
80
81 /* Alternativ core deduction for older ICCARM's */
82 #if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
83 !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
84 #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
85 #define __ARM_ARCH_6M__ 1
86 #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
87 #define __ARM_ARCH_7M__ 1
88 #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
89 #define __ARM_ARCH_7EM__ 1
90 #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
91 #define __ARM_ARCH_8M_BASE__ 1
92 #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
93 #define __ARM_ARCH_8M_MAIN__ 1
94 #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
95 #define __ARM_ARCH_8M_MAIN__ 1
96 #else
97 #error "Unknown target."
98 #endif
99 #endif
100
101
102
103 #if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
104 #define __IAR_M0_FAMILY 1
105 #elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
106 #define __IAR_M0_FAMILY 1
107 #else
108 #define __IAR_M0_FAMILY 0
109 #endif
110
111
112 #ifndef __ASM
113 #define __ASM __asm
114 #endif
115
116 #ifndef __COMPILER_BARRIER
117 #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
118 #endif
119
120 #ifndef __INLINE
121 #define __INLINE inline
122 #endif
123
124 #ifndef __NO_RETURN
125 #if __ICCARM_V8
126 #define __NO_RETURN __attribute__((__noreturn__))
127 #else
128 #define __NO_RETURN _Pragma("object_attribute=__noreturn")
129 #endif
130 #endif
131
132 #ifndef __PACKED
133 #if __ICCARM_V8
134 #define __PACKED __attribute__((packed, aligned(1)))
135 #else
136 /* Needs IAR language extensions */
137 #define __PACKED __packed
138 #endif
139 #endif
140
141 #ifndef __PACKED_STRUCT
142 #if __ICCARM_V8
143 #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
144 #else
145 /* Needs IAR language extensions */
146 #define __PACKED_STRUCT __packed struct
147 #endif
148 #endif
149
150 #ifndef __PACKED_UNION
151 #if __ICCARM_V8
152 #define __PACKED_UNION union __attribute__((packed, aligned(1)))
153 #else
154 /* Needs IAR language extensions */
155 #define __PACKED_UNION __packed union
156 #endif
157 #endif
158
159 #ifndef __RESTRICT
160 #if __ICCARM_V8
161 #define __RESTRICT __restrict
162 #else
163 /* Needs IAR language extensions */
164 #define __RESTRICT restrict
165 #endif
166 #endif
167
168 #ifndef __STATIC_INLINE
169 #define __STATIC_INLINE static inline
170 #endif
171
172 #ifndef __FORCEINLINE
173 #define __FORCEINLINE _Pragma("inline=forced")
174 #endif
175
176 #ifndef __STATIC_FORCEINLINE
177 #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
178 #endif
179
180 #ifndef __UNALIGNED_UINT16_READ
181 #pragma language=save
182 #pragma language=extended
__iar_uint16_read(void const * ptr)183 __IAR_FT uint16_t __iar_uint16_read(void const *ptr)
184 {
185 return *(__packed uint16_t*)(ptr);
186 }
187 #pragma language=restore
188 #define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
189 #endif
190
191
192 #ifndef __UNALIGNED_UINT16_WRITE
193 #pragma language=save
194 #pragma language=extended
__iar_uint16_write(void const * ptr,uint16_t val)195 __IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
196 {
197 *(__packed uint16_t*)(ptr) = val;;
198 }
199 #pragma language=restore
200 #define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
201 #endif
202
203 #ifndef __UNALIGNED_UINT32_READ
204 #pragma language=save
205 #pragma language=extended
__iar_uint32_read(void const * ptr)206 __IAR_FT uint32_t __iar_uint32_read(void const *ptr)
207 {
208 return *(__packed uint32_t*)(ptr);
209 }
210 #pragma language=restore
211 #define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
212 #endif
213
214 #ifndef __UNALIGNED_UINT32_WRITE
215 #pragma language=save
216 #pragma language=extended
__iar_uint32_write(void const * ptr,uint32_t val)217 __IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
218 {
219 *(__packed uint32_t*)(ptr) = val;;
220 }
221 #pragma language=restore
222 #define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
223 #endif
224
225 #ifndef __UNALIGNED_UINT32 /* deprecated */
226 #pragma language=save
227 #pragma language=extended
228 __packed struct __iar_u32 { uint32_t v; };
229 #pragma language=restore
230 #define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
231 #endif
232
233 #ifndef __USED
234 #if __ICCARM_V8
235 #define __USED __attribute__((used))
236 #else
237 #define __USED _Pragma("__root")
238 #endif
239 #endif
240
241 #ifndef __WEAK
242 #if __ICCARM_V8
243 #define __WEAK __attribute__((weak))
244 #else
245 #define __WEAK _Pragma("__weak")
246 #endif
247 #endif
248
249 #ifndef __PROGRAM_START
250 #define __PROGRAM_START __iar_program_start
251 #endif
252
253 #ifndef __INITIAL_SP
254 #define __INITIAL_SP CSTACK$$Limit
255 #endif
256
257 #ifndef __STACK_LIMIT
258 #define __STACK_LIMIT CSTACK$$Base
259 #endif
260
261 #ifndef __VECTOR_TABLE
262 #define __VECTOR_TABLE __vector_table
263 #endif
264
265 #ifndef __VECTOR_TABLE_ATTRIBUTE
266 #define __VECTOR_TABLE_ATTRIBUTE @".intvec"
267 #endif
268
269 #ifndef __ICCARM_INTRINSICS_VERSION__
270 #define __ICCARM_INTRINSICS_VERSION__ 0
271 #endif
272
273 #if __ICCARM_INTRINSICS_VERSION__ == 2
274
275 #if defined(__CLZ)
276 #undef __CLZ
277 #endif
278 #if defined(__REVSH)
279 #undef __REVSH
280 #endif
281 #if defined(__RBIT)
282 #undef __RBIT
283 #endif
284 #if defined(__SSAT)
285 #undef __SSAT
286 #endif
287 #if defined(__USAT)
288 #undef __USAT
289 #endif
290
291 #include "iccarm_builtin.h"
292
293 #define __disable_fault_irq __iar_builtin_disable_fiq
294 #define __disable_irq __iar_builtin_disable_interrupt
295 #define __enable_fault_irq __iar_builtin_enable_fiq
296 #define __enable_irq __iar_builtin_enable_interrupt
297 #define __arm_rsr __iar_builtin_rsr
298 #define __arm_wsr __iar_builtin_wsr
299
300
301 #define __get_APSR() (__arm_rsr("APSR"))
302 #define __get_BASEPRI() (__arm_rsr("BASEPRI"))
303 #define __get_CONTROL() (__arm_rsr("CONTROL"))
304 #define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
305
306 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
307 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
308 #define __get_FPSCR() (__arm_rsr("FPSCR"))
309 #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
310 #else
311 #define __get_FPSCR() ( 0 )
312 #define __set_FPSCR(VALUE) ((void)VALUE)
313 #endif
314
315 #define __get_IPSR() (__arm_rsr("IPSR"))
316 #define __get_MSP() (__arm_rsr("MSP"))
317 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
318 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
319 // without main extensions, the non-secure MSPLIM is RAZ/WI
320 #define __get_MSPLIM() (0U)
321 #else
322 #define __get_MSPLIM() (__arm_rsr("MSPLIM"))
323 #endif
324 #define __get_PRIMASK() (__arm_rsr("PRIMASK"))
325 #define __get_PSP() (__arm_rsr("PSP"))
326
327 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
328 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
329 // without main extensions, the non-secure PSPLIM is RAZ/WI
330 #define __get_PSPLIM() (0U)
331 #else
332 #define __get_PSPLIM() (__arm_rsr("PSPLIM"))
333 #endif
334
335 #define __get_xPSR() (__arm_rsr("xPSR"))
336
337 #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
338 #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
339 #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
340 #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
341 #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
342
343 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
344 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
345 // without main extensions, the non-secure MSPLIM is RAZ/WI
346 #define __set_MSPLIM(VALUE) ((void)(VALUE))
347 #else
348 #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
349 #endif
350 #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
351 #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
352 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
353 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
354 // without main extensions, the non-secure PSPLIM is RAZ/WI
355 #define __set_PSPLIM(VALUE) ((void)(VALUE))
356 #else
357 #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
358 #endif
359
360 #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
361 #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
362 #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
363 #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
364 #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
365 #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
366 #define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
367 #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
368 #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
369 #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
370 #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
371 #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
372 #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
373 #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
374
375 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
376 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
377 // without main extensions, the non-secure PSPLIM is RAZ/WI
378 #define __TZ_get_PSPLIM_NS() (0U)
379 #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
380 #else
381 #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
382 #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
383 #endif
384
385 #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
386 #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
387
388 #define __NOP __iar_builtin_no_operation
389
390 #define __CLZ __iar_builtin_CLZ
391 #define __CLREX __iar_builtin_CLREX
392
393 #define __DMB __iar_builtin_DMB
394 #define __DSB __iar_builtin_DSB
395 #define __ISB __iar_builtin_ISB
396
397 #define __LDREXB __iar_builtin_LDREXB
398 #define __LDREXH __iar_builtin_LDREXH
399 #define __LDREXW __iar_builtin_LDREX
400
401 #define __RBIT __iar_builtin_RBIT
402 #define __REV __iar_builtin_REV
403 #define __REV16 __iar_builtin_REV16
404
__REVSH(int16_t val)405 __IAR_FT int16_t __REVSH(int16_t val)
406 {
407 return (int16_t) __iar_builtin_REVSH(val);
408 }
409
410 #define __ROR __iar_builtin_ROR
411 #define __RRX __iar_builtin_RRX
412
413 #define __SEV __iar_builtin_SEV
414
415 #if !__IAR_M0_FAMILY
416 #define __SSAT __iar_builtin_SSAT
417 #endif
418
419 #define __STREXB __iar_builtin_STREXB
420 #define __STREXH __iar_builtin_STREXH
421 #define __STREXW __iar_builtin_STREX
422
423 #if !__IAR_M0_FAMILY
424 #define __USAT __iar_builtin_USAT
425 #endif
426
427 #define __WFE __iar_builtin_WFE
428 #define __WFI __iar_builtin_WFI
429
430 #if __ARM_MEDIA__
431 #define __SADD8 __iar_builtin_SADD8
432 #define __QADD8 __iar_builtin_QADD8
433 #define __SHADD8 __iar_builtin_SHADD8
434 #define __UADD8 __iar_builtin_UADD8
435 #define __UQADD8 __iar_builtin_UQADD8
436 #define __UHADD8 __iar_builtin_UHADD8
437 #define __SSUB8 __iar_builtin_SSUB8
438 #define __QSUB8 __iar_builtin_QSUB8
439 #define __SHSUB8 __iar_builtin_SHSUB8
440 #define __USUB8 __iar_builtin_USUB8
441 #define __UQSUB8 __iar_builtin_UQSUB8
442 #define __UHSUB8 __iar_builtin_UHSUB8
443 #define __SADD16 __iar_builtin_SADD16
444 #define __QADD16 __iar_builtin_QADD16
445 #define __SHADD16 __iar_builtin_SHADD16
446 #define __UADD16 __iar_builtin_UADD16
447 #define __UQADD16 __iar_builtin_UQADD16
448 #define __UHADD16 __iar_builtin_UHADD16
449 #define __SSUB16 __iar_builtin_SSUB16
450 #define __QSUB16 __iar_builtin_QSUB16
451 #define __SHSUB16 __iar_builtin_SHSUB16
452 #define __USUB16 __iar_builtin_USUB16
453 #define __UQSUB16 __iar_builtin_UQSUB16
454 #define __UHSUB16 __iar_builtin_UHSUB16
455 #define __SASX __iar_builtin_SASX
456 #define __QASX __iar_builtin_QASX
457 #define __SHASX __iar_builtin_SHASX
458 #define __UASX __iar_builtin_UASX
459 #define __UQASX __iar_builtin_UQASX
460 #define __UHASX __iar_builtin_UHASX
461 #define __SSAX __iar_builtin_SSAX
462 #define __QSAX __iar_builtin_QSAX
463 #define __SHSAX __iar_builtin_SHSAX
464 #define __USAX __iar_builtin_USAX
465 #define __UQSAX __iar_builtin_UQSAX
466 #define __UHSAX __iar_builtin_UHSAX
467 #define __USAD8 __iar_builtin_USAD8
468 #define __USADA8 __iar_builtin_USADA8
469 #define __SSAT16 __iar_builtin_SSAT16
470 #define __USAT16 __iar_builtin_USAT16
471 #define __UXTB16 __iar_builtin_UXTB16
472 #define __UXTAB16 __iar_builtin_UXTAB16
473 #define __SXTB16 __iar_builtin_SXTB16
474 #define __SXTAB16 __iar_builtin_SXTAB16
475 #define __SMUAD __iar_builtin_SMUAD
476 #define __SMUADX __iar_builtin_SMUADX
477 #define __SMMLA __iar_builtin_SMMLA
478 #define __SMLAD __iar_builtin_SMLAD
479 #define __SMLADX __iar_builtin_SMLADX
480 #define __SMLALD __iar_builtin_SMLALD
481 #define __SMLALDX __iar_builtin_SMLALDX
482 #define __SMUSD __iar_builtin_SMUSD
483 #define __SMUSDX __iar_builtin_SMUSDX
484 #define __SMLSD __iar_builtin_SMLSD
485 #define __SMLSDX __iar_builtin_SMLSDX
486 #define __SMLSLD __iar_builtin_SMLSLD
487 #define __SMLSLDX __iar_builtin_SMLSLDX
488 #define __SEL __iar_builtin_SEL
489 #define __QADD __iar_builtin_QADD
490 #define __QSUB __iar_builtin_QSUB
491 #define __PKHBT __iar_builtin_PKHBT
492 #define __PKHTB __iar_builtin_PKHTB
493 #endif
494
495 #else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
496
497 #if __IAR_M0_FAMILY
498 /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
499 #define __CLZ __cmsis_iar_clz_not_active
500 #define __SSAT __cmsis_iar_ssat_not_active
501 #define __USAT __cmsis_iar_usat_not_active
502 #define __RBIT __cmsis_iar_rbit_not_active
503 #define __get_APSR __cmsis_iar_get_APSR_not_active
504 #endif
505
506
507 #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
508 (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
509 #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
510 #define __set_FPSCR __cmsis_iar_set_FPSR_not_active
511 #endif
512
513 #ifdef __INTRINSICS_INCLUDED
514 #error intrinsics.h is already included previously!
515 #endif
516
517 #include <intrinsics.h>
518
519 #if __IAR_M0_FAMILY
520 /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
521 #undef __CLZ
522 #undef __SSAT
523 #undef __USAT
524 #undef __RBIT
525 #undef __get_APSR
526
__CLZ(uint32_t data)527 __STATIC_INLINE uint8_t __CLZ(uint32_t data)
528 {
529 if (data == 0U) { return 32U; }
530
531 uint32_t count = 0U;
532 uint32_t mask = 0x80000000U;
533
534 while ((data & mask) == 0U)
535 {
536 count += 1U;
537 mask = mask >> 1U;
538 }
539 return count;
540 }
541
__RBIT(uint32_t v)542 __STATIC_INLINE uint32_t __RBIT(uint32_t v)
543 {
544 uint8_t sc = 31U;
545 uint32_t r = v;
546 for (v >>= 1U; v; v >>= 1U)
547 {
548 r <<= 1U;
549 r |= v & 1U;
550 sc--;
551 }
552 return (r << sc);
553 }
554
__get_APSR(void)555 __STATIC_INLINE uint32_t __get_APSR(void)
556 {
557 uint32_t res;
558 __asm("MRS %0,APSR" : "=r" (res));
559 return res;
560 }
561
562 #endif
563
564 #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
565 (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
566 #undef __get_FPSCR
567 #undef __set_FPSCR
568 #define __get_FPSCR() (0)
569 #define __set_FPSCR(VALUE) ((void)VALUE)
570 #endif
571
572 #pragma diag_suppress=Pe940
573 #pragma diag_suppress=Pe177
574
575 #define __enable_irq __enable_interrupt
576 #define __disable_irq __disable_interrupt
577 #define __NOP __no_operation
578
579 #define __get_xPSR __get_PSR
580
581 #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
582
__LDREXW(uint32_t volatile * ptr)583 __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
584 {
585 return __LDREX((unsigned long *)ptr);
586 }
587
__STREXW(uint32_t value,uint32_t volatile * ptr)588 __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
589 {
590 return __STREX(value, (unsigned long *)ptr);
591 }
592 #endif
593
594
595 /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
596 #if (__CORTEX_M >= 0x03)
597
__RRX(uint32_t value)598 __IAR_FT uint32_t __RRX(uint32_t value)
599 {
600 uint32_t result;
601 __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value));
602 return(result);
603 }
604
__set_BASEPRI_MAX(uint32_t value)605 __IAR_FT void __set_BASEPRI_MAX(uint32_t value)
606 {
607 __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
608 }
609
610
611 #define __enable_fault_irq __enable_fiq
612 #define __disable_fault_irq __disable_fiq
613
614
615 #endif /* (__CORTEX_M >= 0x03) */
616
__ROR(uint32_t op1,uint32_t op2)617 __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
618 {
619 return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
620 }
621
622 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
623 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
624
__get_MSPLIM(void)625 __IAR_FT uint32_t __get_MSPLIM(void)
626 {
627 uint32_t res;
628 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
629 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
630 // without main extensions, the non-secure MSPLIM is RAZ/WI
631 res = 0U;
632 #else
633 __asm volatile("MRS %0,MSPLIM" : "=r" (res));
634 #endif
635 return res;
636 }
637
__set_MSPLIM(uint32_t value)638 __IAR_FT void __set_MSPLIM(uint32_t value)
639 {
640 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
641 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
642 // without main extensions, the non-secure MSPLIM is RAZ/WI
643 (void)value;
644 #else
645 __asm volatile("MSR MSPLIM,%0" :: "r" (value));
646 #endif
647 }
648
__get_PSPLIM(void)649 __IAR_FT uint32_t __get_PSPLIM(void)
650 {
651 uint32_t res;
652 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
653 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
654 // without main extensions, the non-secure PSPLIM is RAZ/WI
655 res = 0U;
656 #else
657 __asm volatile("MRS %0,PSPLIM" : "=r" (res));
658 #endif
659 return res;
660 }
661
__set_PSPLIM(uint32_t value)662 __IAR_FT void __set_PSPLIM(uint32_t value)
663 {
664 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
665 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
666 // without main extensions, the non-secure PSPLIM is RAZ/WI
667 (void)value;
668 #else
669 __asm volatile("MSR PSPLIM,%0" :: "r" (value));
670 #endif
671 }
672
__TZ_get_CONTROL_NS(void)673 __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
674 {
675 uint32_t res;
676 __asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
677 return res;
678 }
679
__TZ_set_CONTROL_NS(uint32_t value)680 __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
681 {
682 __asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
683 }
684
__TZ_get_PSP_NS(void)685 __IAR_FT uint32_t __TZ_get_PSP_NS(void)
686 {
687 uint32_t res;
688 __asm volatile("MRS %0,PSP_NS" : "=r" (res));
689 return res;
690 }
691
__TZ_set_PSP_NS(uint32_t value)692 __IAR_FT void __TZ_set_PSP_NS(uint32_t value)
693 {
694 __asm volatile("MSR PSP_NS,%0" :: "r" (value));
695 }
696
__TZ_get_MSP_NS(void)697 __IAR_FT uint32_t __TZ_get_MSP_NS(void)
698 {
699 uint32_t res;
700 __asm volatile("MRS %0,MSP_NS" : "=r" (res));
701 return res;
702 }
703
__TZ_set_MSP_NS(uint32_t value)704 __IAR_FT void __TZ_set_MSP_NS(uint32_t value)
705 {
706 __asm volatile("MSR MSP_NS,%0" :: "r" (value));
707 }
708
__TZ_get_SP_NS(void)709 __IAR_FT uint32_t __TZ_get_SP_NS(void)
710 {
711 uint32_t res;
712 __asm volatile("MRS %0,SP_NS" : "=r" (res));
713 return res;
714 }
__TZ_set_SP_NS(uint32_t value)715 __IAR_FT void __TZ_set_SP_NS(uint32_t value)
716 {
717 __asm volatile("MSR SP_NS,%0" :: "r" (value));
718 }
719
__TZ_get_PRIMASK_NS(void)720 __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
721 {
722 uint32_t res;
723 __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
724 return res;
725 }
726
__TZ_set_PRIMASK_NS(uint32_t value)727 __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
728 {
729 __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
730 }
731
__TZ_get_BASEPRI_NS(void)732 __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
733 {
734 uint32_t res;
735 __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
736 return res;
737 }
738
__TZ_set_BASEPRI_NS(uint32_t value)739 __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
740 {
741 __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
742 }
743
__TZ_get_FAULTMASK_NS(void)744 __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
745 {
746 uint32_t res;
747 __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
748 return res;
749 }
750
__TZ_set_FAULTMASK_NS(uint32_t value)751 __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
752 {
753 __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
754 }
755
__TZ_get_PSPLIM_NS(void)756 __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
757 {
758 uint32_t res;
759 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
760 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
761 // without main extensions, the non-secure PSPLIM is RAZ/WI
762 res = 0U;
763 #else
764 __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
765 #endif
766 return res;
767 }
768
__TZ_set_PSPLIM_NS(uint32_t value)769 __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
770 {
771 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
772 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
773 // without main extensions, the non-secure PSPLIM is RAZ/WI
774 (void)value;
775 #else
776 __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
777 #endif
778 }
779
__TZ_get_MSPLIM_NS(void)780 __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
781 {
782 uint32_t res;
783 __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
784 return res;
785 }
786
__TZ_set_MSPLIM_NS(uint32_t value)787 __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
788 {
789 __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
790 }
791
792 #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
793
794 #endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
795
796 #define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
797
798 #if __IAR_M0_FAMILY
__SSAT(int32_t val,uint32_t sat)799 __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
800 {
801 if ((sat >= 1U) && (sat <= 32U))
802 {
803 const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
804 const int32_t min = -1 - max ;
805 if (val > max)
806 {
807 return max;
808 }
809 else if (val < min)
810 {
811 return min;
812 }
813 }
814 return val;
815 }
816
__USAT(int32_t val,uint32_t sat)817 __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
818 {
819 if (sat <= 31U)
820 {
821 const uint32_t max = ((1U << sat) - 1U);
822 if (val > (int32_t)max)
823 {
824 return max;
825 }
826 else if (val < 0)
827 {
828 return 0U;
829 }
830 }
831 return (uint32_t)val;
832 }
833 #endif
834
835 #if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
836
__LDRBT(volatile uint8_t * addr)837 __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
838 {
839 uint32_t res;
840 __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
841 return ((uint8_t)res);
842 }
843
__LDRHT(volatile uint16_t * addr)844 __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
845 {
846 uint32_t res;
847 __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
848 return ((uint16_t)res);
849 }
850
__LDRT(volatile uint32_t * addr)851 __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
852 {
853 uint32_t res;
854 __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
855 return res;
856 }
857
__STRBT(uint8_t value,volatile uint8_t * addr)858 __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
859 {
860 __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
861 }
862
__STRHT(uint16_t value,volatile uint16_t * addr)863 __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
864 {
865 __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
866 }
867
__STRT(uint32_t value,volatile uint32_t * addr)868 __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
869 {
870 __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
871 }
872
873 #endif /* (__CORTEX_M >= 0x03) */
874
875 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
876 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
877
878
__LDAB(volatile uint8_t * ptr)879 __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
880 {
881 uint32_t res;
882 __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
883 return ((uint8_t)res);
884 }
885
__LDAH(volatile uint16_t * ptr)886 __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
887 {
888 uint32_t res;
889 __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
890 return ((uint16_t)res);
891 }
892
__LDA(volatile uint32_t * ptr)893 __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
894 {
895 uint32_t res;
896 __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
897 return res;
898 }
899
__STLB(uint8_t value,volatile uint8_t * ptr)900 __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
901 {
902 __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
903 }
904
__STLH(uint16_t value,volatile uint16_t * ptr)905 __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
906 {
907 __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
908 }
909
__STL(uint32_t value,volatile uint32_t * ptr)910 __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
911 {
912 __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
913 }
914
__LDAEXB(volatile uint8_t * ptr)915 __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
916 {
917 uint32_t res;
918 __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
919 return ((uint8_t)res);
920 }
921
__LDAEXH(volatile uint16_t * ptr)922 __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
923 {
924 uint32_t res;
925 __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
926 return ((uint16_t)res);
927 }
928
__LDAEX(volatile uint32_t * ptr)929 __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
930 {
931 uint32_t res;
932 __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
933 return res;
934 }
935
__STLEXB(uint8_t value,volatile uint8_t * ptr)936 __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
937 {
938 uint32_t res;
939 __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
940 return res;
941 }
942
__STLEXH(uint16_t value,volatile uint16_t * ptr)943 __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
944 {
945 uint32_t res;
946 __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
947 return res;
948 }
949
__STLEX(uint32_t value,volatile uint32_t * ptr)950 __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
951 {
952 uint32_t res;
953 __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
954 return res;
955 }
956
957 #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
958
959 #undef __IAR_FT
960 #undef __IAR_M0_FAMILY
961 #undef __ICCARM_V8
962
963 #pragma diag_default=Pe940
964 #pragma diag_default=Pe177
965
966 #define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
967
968 #endif /* __CMSIS_ICCARM_H__ */
969