1 /**************************************************************************//**
2 * @file core_cm4.h
3 * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
4 * @version V5.1.1
5 * @date 27. March 2020
6 ******************************************************************************/
7 /*
8 * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25 #if defined ( __ICCARM__ )
26 #pragma system_include /* treat file as system include file for MISRA check */
27 #elif defined (__clang__)
28 #pragma clang system_header /* treat file as system include file */
29 #endif
30
31 #ifndef __CORE_CM4_H_GENERIC
32 #define __CORE_CM4_H_GENERIC
33
34 #ifndef __ASSEMBLER__
35 #include <stdint.h>
36 #endif
37
38 #ifdef __cplusplus
39 extern "C" {
40 #endif
41
42 /**
43 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
44 CMSIS violates the following MISRA-C:2004 rules:
45
46 \li Required Rule 8.5, object/function definition in header file.<br>
47 Function definitions in header files are used to allow 'inlining'.
48
49 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
50 Unions are used for effective representation of core registers.
51
52 \li Advisory Rule 19.7, Function-like macro defined.<br>
53 Function-like macros are used to allow more efficient code.
54 */
55
56
57 /*******************************************************************************
58 * CMSIS definitions
59 ******************************************************************************/
60 /**
61 \ingroup Cortex_M4
62 @{
63 */
64
65 #include "cmsis_version.h"
66
67 /* CMSIS CM4 definitions */
68 #define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
69 #define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
70 #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
71 __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
72
73 #define __CORTEX_M (4U) /*!< Cortex-M Core */
74
75 /** __FPU_USED indicates whether an FPU is used or not.
76 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
77 */
78 #if defined ( __CC_ARM )
79 #if defined __TARGET_FPU_VFP
80 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
81 #define __FPU_USED 1U
82 #else
83 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
84 #define __FPU_USED 0U
85 #endif
86 #else
87 #define __FPU_USED 0U
88 #endif
89
90 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
91 #if defined __ARM_FP
92 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
93 #define __FPU_USED 1U
94 #else
95 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
96 #define __FPU_USED 0U
97 #endif
98 #else
99 #define __FPU_USED 0U
100 #endif
101
102 #elif defined ( __GNUC__ )
103 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
104 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
105 #define __FPU_USED 1U
106 #else
107 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
108 #define __FPU_USED 0U
109 #endif
110 #else
111 #define __FPU_USED 0U
112 #endif
113
114 #elif defined ( __ICCARM__ )
115 #if defined __ARMVFP__
116 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
117 #define __FPU_USED 1U
118 #else
119 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
120 #define __FPU_USED 0U
121 #endif
122 #else
123 #define __FPU_USED 0U
124 #endif
125
126 #elif defined ( __TI_ARM__ )
127 #if defined __TI_VFP_SUPPORT__
128 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
129 #define __FPU_USED 1U
130 #else
131 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
132 #define __FPU_USED 0U
133 #endif
134 #else
135 #define __FPU_USED 0U
136 #endif
137
138 #elif defined ( __TASKING__ )
139 #if defined __FPU_VFP__
140 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
141 #define __FPU_USED 1U
142 #else
143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
144 #define __FPU_USED 0U
145 #endif
146 #else
147 #define __FPU_USED 0U
148 #endif
149
150 #elif defined ( __CSMC__ )
151 #if ( __CSMC__ & 0x400U)
152 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
153 #define __FPU_USED 1U
154 #else
155 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
156 #define __FPU_USED 0U
157 #endif
158 #else
159 #define __FPU_USED 0U
160 #endif
161
162 #endif
163
164 #ifndef __ASSEMBLER__
165 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
166 #endif
167
168 #ifdef __cplusplus
169 }
170 #endif
171
172 #endif /* __CORE_CM4_H_GENERIC */
173
174 #ifndef __CMSIS_GENERIC
175
176 #ifndef __CORE_CM4_H_DEPENDANT
177 #define __CORE_CM4_H_DEPENDANT
178
179 #ifdef __cplusplus
180 extern "C" {
181 #endif
182
183 /* check device defines and use defaults */
184 #if defined __CHECK_DEVICE_DEFINES
185 #ifndef __CM4_REV
186 #define __CM4_REV 0x0000U
187 #warning "__CM4_REV not defined in device header file; using default!"
188 #endif
189
190 #ifndef __FPU_PRESENT
191 #define __FPU_PRESENT 0U
192 #warning "__FPU_PRESENT not defined in device header file; using default!"
193 #endif
194
195 #ifndef __MPU_PRESENT
196 #define __MPU_PRESENT 0U
197 #warning "__MPU_PRESENT not defined in device header file; using default!"
198 #endif
199
200 #ifndef __VTOR_PRESENT
201 #define __VTOR_PRESENT 1U
202 #warning "__VTOR_PRESENT not defined in device header file; using default!"
203 #endif
204
205 #ifndef __NVIC_PRIO_BITS
206 #define __NVIC_PRIO_BITS 3U
207 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
208 #endif
209
210 #ifndef __Vendor_SysTickConfig
211 #define __Vendor_SysTickConfig 0U
212 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
213 #endif
214 #endif
215
216 /* IO definitions (access restrictions to peripheral registers) */
217 /**
218 \defgroup CMSIS_glob_defs CMSIS Global Defines
219
220 <strong>IO Type Qualifiers</strong> are used
221 \li to specify the access to peripheral variables.
222 \li for automatic generation of peripheral register debug information.
223 */
224 #ifdef __cplusplus
225 #define __I volatile /*!< Defines 'read only' permissions */
226 #else
227 #define __I volatile const /*!< Defines 'read only' permissions */
228 #endif
229 #define __O volatile /*!< Defines 'write only' permissions */
230 #define __IO volatile /*!< Defines 'read / write' permissions */
231
232 /* following defines should be used for structure members */
233 #define __IM volatile const /*! Defines 'read only' structure member permissions */
234 #define __OM volatile /*! Defines 'write only' structure member permissions */
235 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
236
237 /*@} end of group Cortex_M4 */
238
239
240 #ifndef __ASSEMBLER__
241
242 /*******************************************************************************
243 * Register Abstraction
244 Core Register contain:
245 - Core Register
246 - Core NVIC Register
247 - Core SCB Register
248 - Core SysTick Register
249 - Core Debug Register
250 - Core MPU Register
251 - Core FPU Register
252 ******************************************************************************/
253 /**
254 \defgroup CMSIS_core_register Defines and Type Definitions
255 \brief Type definitions and defines for Cortex-M processor based devices.
256 */
257
258 /**
259 \ingroup CMSIS_core_register
260 \defgroup CMSIS_CORE Status and Control Registers
261 \brief Core Register type definitions.
262 @{
263 */
264
265 /**
266 \brief Union type to access the Application Program Status Register (APSR).
267 */
268 typedef union
269 {
270 struct
271 {
272 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
273 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
274 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
275 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
276 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
277 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
278 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
279 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
280 } b; /*!< Structure used for bit access */
281 uint32_t w; /*!< Type used for word access */
282 } APSR_Type;
283
284 /* APSR Register Definitions */
285 #define APSR_N_Pos 31U /*!< APSR: N Position */
286 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
287
288 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
289 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
290
291 #define APSR_C_Pos 29U /*!< APSR: C Position */
292 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
293
294 #define APSR_V_Pos 28U /*!< APSR: V Position */
295 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
296
297 #define APSR_Q_Pos 27U /*!< APSR: Q Position */
298 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
299
300 #define APSR_GE_Pos 16U /*!< APSR: GE Position */
301 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
302
303
304 /**
305 \brief Union type to access the Interrupt Program Status Register (IPSR).
306 */
307 typedef union
308 {
309 struct
310 {
311 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
312 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
313 } b; /*!< Structure used for bit access */
314 uint32_t w; /*!< Type used for word access */
315 } IPSR_Type;
316
317 /* IPSR Register Definitions */
318 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
319 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
320
321
322 /**
323 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
324 */
325 typedef union
326 {
327 struct
328 {
329 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
330 uint32_t _reserved0:1; /*!< bit: 9 Reserved */
331 uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
332 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
333 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
334 uint32_t T:1; /*!< bit: 24 Thumb bit */
335 uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
336 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
337 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
338 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
339 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
340 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
341 } b; /*!< Structure used for bit access */
342 uint32_t w; /*!< Type used for word access */
343 } xPSR_Type;
344
345 /* xPSR Register Definitions */
346 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
347 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
348
349 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
350 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
351
352 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
353 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
354
355 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
356 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
357
358 #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
359 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
360
361 #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
362 #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
363
364 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
365 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
366
367 #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
368 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
369
370 #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
371 #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
372
373 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
374 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
375
376
377 /**
378 \brief Union type to access the Control Registers (CONTROL).
379 */
380 typedef union
381 {
382 struct
383 {
384 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
385 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
386 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
387 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
388 } b; /*!< Structure used for bit access */
389 uint32_t w; /*!< Type used for word access */
390 } CONTROL_Type;
391
392 /* CONTROL Register Definitions */
393 #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
394 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
395
396 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
397 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
398
399 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
400 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
401
402 /*@} end of group CMSIS_CORE */
403
404
405 /**
406 \ingroup CMSIS_core_register
407 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
408 \brief Type definitions for the NVIC Registers
409 @{
410 */
411
412 /**
413 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
414 */
415 typedef struct
416 {
417 __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
418 uint32_t RESERVED0[24U];
419 __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
420 uint32_t RESERVED1[24U];
421 __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
422 uint32_t RESERVED2[24U];
423 __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
424 uint32_t RESERVED3[24U];
425 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
426 uint32_t RESERVED4[56U];
427 __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
428 uint32_t RESERVED5[644U];
429 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
430 } NVIC_Type;
431
432 /* Software Triggered Interrupt Register Definitions */
433 #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
434 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
435
436 /*@} end of group CMSIS_NVIC */
437
438
439 /**
440 \ingroup CMSIS_core_register
441 \defgroup CMSIS_SCB System Control Block (SCB)
442 \brief Type definitions for the System Control Block Registers
443 @{
444 */
445
446 /**
447 \brief Structure type to access the System Control Block (SCB).
448 */
449 typedef struct
450 {
451 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
452 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
453 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
454 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
455 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
456 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
457 __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
458 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
459 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
460 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
461 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
462 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
463 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
464 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
465 __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
466 __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
467 __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
468 __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
469 __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
470 uint32_t RESERVED0[5U];
471 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
472 } SCB_Type;
473
474 /* SCB CPUID Register Definitions */
475 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
476 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
477
478 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
479 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
480
481 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
482 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
483
484 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
485 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
486
487 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
488 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
489
490 /* SCB Interrupt Control State Register Definitions */
491 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
492 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
493
494 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
495 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
496
497 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
498 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
499
500 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
501 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
502
503 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
504 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
505
506 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
507 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
508
509 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
510 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
511
512 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
513 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
514
515 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
516 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
517
518 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
519 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
520
521 /* SCB Vector Table Offset Register Definitions */
522 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
523 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
524
525 /* SCB Application Interrupt and Reset Control Register Definitions */
526 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
527 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
528
529 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
530 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
531
532 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
533 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
534
535 #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
536 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
537
538 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
539 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
540
541 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
542 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
543
544 #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
545 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
546
547 /* SCB System Control Register Definitions */
548 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
549 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
550
551 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
552 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
553
554 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
555 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
556
557 /* SCB Configuration Control Register Definitions */
558 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
559 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
560
561 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
562 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
563
564 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
565 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
566
567 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
568 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
569
570 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
571 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
572
573 #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
574 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
575
576 /* SCB System Handler Control and State Register Definitions */
577 #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
578 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
579
580 #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
581 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
582
583 #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
584 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
585
586 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
587 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
588
589 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
590 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
591
592 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
593 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
594
595 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
596 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
597
598 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
599 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
600
601 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
602 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
603
604 #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
605 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
606
607 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
608 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
609
610 #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
611 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
612
613 #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
614 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
615
616 #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
617 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
618
619 /* SCB Configurable Fault Status Register Definitions */
620 #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
621 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
622
623 #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
624 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
625
626 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
627 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
628
629 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
630 #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
631 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
632
633 #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
634 #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
635
636 #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
637 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
638
639 #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
640 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
641
642 #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
643 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
644
645 #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
646 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
647
648 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */
649 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
650 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
651
652 #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
653 #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
654
655 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
656 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
657
658 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
659 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
660
661 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
662 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
663
664 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
665 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
666
667 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
668 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
669
670 /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
671 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
672 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
673
674 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
675 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
676
677 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
678 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
679
680 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
681 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
682
683 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
684 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
685
686 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
687 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
688
689 /* SCB Hard Fault Status Register Definitions */
690 #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
691 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
692
693 #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
694 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
695
696 #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
697 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
698
699 /* SCB Debug Fault Status Register Definitions */
700 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
701 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
702
703 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
704 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
705
706 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
707 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
708
709 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
710 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
711
712 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
713 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
714
715 /*@} end of group CMSIS_SCB */
716
717
718 /**
719 \ingroup CMSIS_core_register
720 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
721 \brief Type definitions for the System Control and ID Register not in the SCB
722 @{
723 */
724
725 /**
726 \brief Structure type to access the System Control and ID Register not in the SCB.
727 */
728 typedef struct
729 {
730 uint32_t RESERVED0[1U];
731 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
732 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
733 } SCnSCB_Type;
734
735 /* Interrupt Controller Type Register Definitions */
736 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
737 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
738
739 /* Auxiliary Control Register Definitions */
740 #define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */
741 #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
742
743 #define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */
744 #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
745
746 #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
747 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
748
749 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
750 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
751
752 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
753 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
754
755 /*@} end of group CMSIS_SCnotSCB */
756
757
758 /**
759 \ingroup CMSIS_core_register
760 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
761 \brief Type definitions for the System Timer Registers.
762 @{
763 */
764
765 /**
766 \brief Structure type to access the System Timer (SysTick).
767 */
768 typedef struct
769 {
770 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
771 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
772 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
773 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
774 } SysTick_Type;
775
776 /* SysTick Control / Status Register Definitions */
777 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
778 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
779
780 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
781 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
782
783 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
784 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
785
786 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
787 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
788
789 /* SysTick Reload Register Definitions */
790 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
791 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
792
793 /* SysTick Current Register Definitions */
794 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
795 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
796
797 /* SysTick Calibration Register Definitions */
798 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
799 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
800
801 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
802 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
803
804 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
805 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
806
807 /*@} end of group CMSIS_SysTick */
808
809
810 /**
811 \ingroup CMSIS_core_register
812 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
813 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
814 @{
815 */
816
817 /**
818 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
819 */
820 typedef struct
821 {
822 __OM union
823 {
824 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
825 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
826 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
827 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
828 uint32_t RESERVED0[864U];
829 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
830 uint32_t RESERVED1[15U];
831 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
832 uint32_t RESERVED2[15U];
833 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
834 uint32_t RESERVED3[32U];
835 uint32_t RESERVED4[43U];
836 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
837 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
838 uint32_t RESERVED5[6U];
839 __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
840 __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
841 __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
842 __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
843 __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
844 __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
845 __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
846 __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
847 __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
848 __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
849 __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
850 __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
851 } ITM_Type;
852
853 /* ITM Trace Privilege Register Definitions */
854 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
855 #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
856
857 /* ITM Trace Control Register Definitions */
858 #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
859 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
860
861 #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
862 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
863
864 #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
865 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
866
867 #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
868 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
869
870 #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
871 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
872
873 #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
874 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
875
876 #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
877 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
878
879 #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
880 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
881
882 #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
883 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
884
885 /* ITM Lock Status Register Definitions */
886 #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
887 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
888
889 #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
890 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
891
892 #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
893 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
894
895 /*@}*/ /* end of group CMSIS_ITM */
896
897
898 /**
899 \ingroup CMSIS_core_register
900 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
901 \brief Type definitions for the Data Watchpoint and Trace (DWT)
902 @{
903 */
904
905 /**
906 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
907 */
908 typedef struct
909 {
910 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
911 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
912 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
913 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
914 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
915 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
916 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
917 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
918 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
919 __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
920 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
921 uint32_t RESERVED0[1U];
922 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
923 __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
924 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
925 uint32_t RESERVED1[1U];
926 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
927 __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
928 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
929 uint32_t RESERVED2[1U];
930 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
931 __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
932 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
933 } DWT_Type;
934
935 /* DWT Control Register Definitions */
936 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
937 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
938
939 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
940 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
941
942 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
943 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
944
945 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
946 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
947
948 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
949 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
950
951 #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
952 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
953
954 #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
955 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
956
957 #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
958 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
959
960 #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
961 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
962
963 #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
964 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
965
966 #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
967 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
968
969 #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
970 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
971
972 #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
973 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
974
975 #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
976 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
977
978 #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
979 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
980
981 #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
982 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
983
984 #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
985 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
986
987 #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
988 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
989
990 /* DWT CPI Count Register Definitions */
991 #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
992 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
993
994 /* DWT Exception Overhead Count Register Definitions */
995 #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
996 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
997
998 /* DWT Sleep Count Register Definitions */
999 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
1000 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
1001
1002 /* DWT LSU Count Register Definitions */
1003 #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
1004 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
1005
1006 /* DWT Folded-instruction Count Register Definitions */
1007 #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
1008 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
1009
1010 /* DWT Comparator Mask Register Definitions */
1011 #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
1012 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
1013
1014 /* DWT Comparator Function Register Definitions */
1015 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
1016 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
1017
1018 #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
1019 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
1020
1021 #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
1022 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
1023
1024 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
1025 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
1026
1027 #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
1028 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
1029
1030 #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
1031 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
1032
1033 #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
1034 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
1035
1036 #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
1037 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
1038
1039 #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
1040 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
1041
1042 /*@}*/ /* end of group CMSIS_DWT */
1043
1044
1045 /**
1046 \ingroup CMSIS_core_register
1047 \defgroup CMSIS_TPI Trace Port Interface (TPI)
1048 \brief Type definitions for the Trace Port Interface (TPI)
1049 @{
1050 */
1051
1052 /**
1053 \brief Structure type to access the Trace Port Interface Register (TPI).
1054 */
1055 typedef struct
1056 {
1057 __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
1058 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
1059 uint32_t RESERVED0[2U];
1060 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
1061 uint32_t RESERVED1[55U];
1062 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
1063 uint32_t RESERVED2[131U];
1064 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
1065 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
1066 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
1067 uint32_t RESERVED3[759U];
1068 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
1069 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
1070 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
1071 uint32_t RESERVED4[1U];
1072 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
1073 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
1074 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
1075 uint32_t RESERVED5[39U];
1076 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
1077 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
1078 uint32_t RESERVED7[8U];
1079 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
1080 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
1081 } TPI_Type;
1082
1083 /* TPI Asynchronous Clock Prescaler Register Definitions */
1084 #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
1085 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
1086
1087 /* TPI Selected Pin Protocol Register Definitions */
1088 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
1089 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
1090
1091 /* TPI Formatter and Flush Status Register Definitions */
1092 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
1093 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
1094
1095 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
1096 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
1097
1098 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
1099 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
1100
1101 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
1102 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
1103
1104 /* TPI Formatter and Flush Control Register Definitions */
1105 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
1106 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
1107
1108 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
1109 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
1110
1111 /* TPI TRIGGER Register Definitions */
1112 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
1113 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
1114
1115 /* TPI Integration ETM Data Register Definitions (FIFO0) */
1116 #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
1117 #define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
1118
1119 #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
1120 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
1121
1122 #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
1123 #define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
1124
1125 #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
1126 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
1127
1128 #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
1129 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
1130
1131 #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
1132 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
1133
1134 #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
1135 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
1136
1137 /* TPI ITATBCTR2 Register Definitions */
1138 #define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
1139 #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
1140
1141 #define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
1142 #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
1143
1144 /* TPI Integration ITM Data Register Definitions (FIFO1) */
1145 #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
1146 #define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
1147
1148 #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
1149 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
1150
1151 #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
1152 #define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
1153
1154 #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
1155 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
1156
1157 #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
1158 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
1159
1160 #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
1161 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
1162
1163 #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
1164 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
1165
1166 /* TPI ITATBCTR0 Register Definitions */
1167 #define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
1168 #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
1169
1170 #define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
1171 #define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
1172
1173 /* TPI Integration Mode Control Register Definitions */
1174 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
1175 #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
1176
1177 /* TPI DEVID Register Definitions */
1178 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
1179 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
1180
1181 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
1182 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
1183
1184 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
1185 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
1186
1187 #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
1188 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
1189
1190 #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
1191 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
1192
1193 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
1194 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
1195
1196 /* TPI DEVTYPE Register Definitions */
1197 #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
1198 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
1199
1200 #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
1201 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
1202
1203 /*@}*/ /* end of group CMSIS_TPI */
1204
1205
1206 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1207 /**
1208 \ingroup CMSIS_core_register
1209 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
1210 \brief Type definitions for the Memory Protection Unit (MPU)
1211 @{
1212 */
1213
1214 /**
1215 \brief Structure type to access the Memory Protection Unit (MPU).
1216 */
1217 typedef struct
1218 {
1219 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
1220 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
1221 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
1222 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
1223 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
1224 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
1225 __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
1226 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
1227 __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
1228 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
1229 __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
1230 } MPU_Type;
1231
1232 #define MPU_TYPE_RALIASES 4U
1233
1234 /* MPU Type Register Definitions */
1235 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
1236 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
1237
1238 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
1239 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
1240
1241 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
1242 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
1243
1244 /* MPU Control Register Definitions */
1245 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
1246 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
1247
1248 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
1249 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
1250
1251 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
1252 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
1253
1254 /* MPU Region Number Register Definitions */
1255 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
1256 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
1257
1258 /* MPU Region Base Address Register Definitions */
1259 #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
1260 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
1261
1262 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
1263 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
1264
1265 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
1266 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
1267
1268 /* MPU Region Attribute and Size Register Definitions */
1269 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
1270 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
1271
1272 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
1273 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
1274
1275 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
1276 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
1277
1278 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
1279 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
1280
1281 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
1282 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
1283
1284 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
1285 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
1286
1287 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
1288 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
1289
1290 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
1291 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
1292
1293 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
1294 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
1295
1296 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
1297 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
1298
1299 /*@} end of group CMSIS_MPU */
1300 #endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
1301
1302
1303 /**
1304 \ingroup CMSIS_core_register
1305 \defgroup CMSIS_FPU Floating Point Unit (FPU)
1306 \brief Type definitions for the Floating Point Unit (FPU)
1307 @{
1308 */
1309
1310 /**
1311 \brief Structure type to access the Floating Point Unit (FPU).
1312 */
1313 typedef struct
1314 {
1315 uint32_t RESERVED0[1U];
1316 __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
1317 __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
1318 __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
1319 __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
1320 __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
1321 __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */
1322 } FPU_Type;
1323
1324 /* Floating-Point Context Control Register Definitions */
1325 #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
1326 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
1327
1328 #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
1329 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
1330
1331 #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
1332 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
1333
1334 #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
1335 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
1336
1337 #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
1338 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
1339
1340 #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
1341 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
1342
1343 #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
1344 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
1345
1346 #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
1347 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
1348
1349 #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
1350 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
1351
1352 /* Floating-Point Context Address Register Definitions */
1353 #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
1354 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
1355
1356 /* Floating-Point Default Status Control Register Definitions */
1357 #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
1358 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
1359
1360 #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
1361 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
1362
1363 #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
1364 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
1365
1366 #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
1367 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
1368
1369 /* Media and FP Feature Register 0 Definitions */
1370 #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
1371 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
1372
1373 #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
1374 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
1375
1376 #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
1377 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
1378
1379 #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
1380 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
1381
1382 #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
1383 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
1384
1385 #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
1386 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
1387
1388 #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
1389 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
1390
1391 #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
1392 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
1393
1394 /* Media and FP Feature Register 1 Definitions */
1395 #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
1396 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
1397
1398 #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
1399 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
1400
1401 #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
1402 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
1403
1404 #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
1405 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
1406
1407 /* Media and FP Feature Register 2 Definitions */
1408
1409 #define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */
1410 #define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */
1411
1412 /*@} end of group CMSIS_FPU */
1413
1414
1415 /**
1416 \ingroup CMSIS_core_register
1417 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
1418 \brief Type definitions for the Core Debug Registers
1419 @{
1420 */
1421
1422 /**
1423 \brief Structure type to access the Core Debug Register (CoreDebug).
1424 */
1425 typedef struct
1426 {
1427 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
1428 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
1429 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
1430 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
1431 } CoreDebug_Type;
1432
1433 /* Debug Halting Control and Status Register Definitions */
1434 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
1435 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
1436
1437 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
1438 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
1439
1440 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
1441 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
1442
1443 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
1444 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
1445
1446 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
1447 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
1448
1449 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
1450 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
1451
1452 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
1453 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
1454
1455 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
1456 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
1457
1458 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
1459 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
1460
1461 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
1462 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
1463
1464 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
1465 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
1466
1467 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
1468 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
1469
1470 /* Debug Core Register Selector Register Definitions */
1471 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
1472 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
1473
1474 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
1475 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
1476
1477 /* Debug Exception and Monitor Control Register Definitions */
1478 #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
1479 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
1480
1481 #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
1482 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
1483
1484 #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
1485 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
1486
1487 #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
1488 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
1489
1490 #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
1491 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
1492
1493 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
1494 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
1495
1496 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
1497 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
1498
1499 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
1500 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
1501
1502 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
1503 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
1504
1505 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
1506 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
1507
1508 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
1509 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
1510
1511 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
1512 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
1513
1514 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
1515 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
1516
1517 /*@} end of group CMSIS_CoreDebug */
1518
1519
1520 /**
1521 \ingroup CMSIS_core_register
1522 \defgroup CMSIS_core_bitfield Core register bit field macros
1523 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
1524 @{
1525 */
1526
1527 /**
1528 \brief Mask and shift a bit field value for use in a register bit range.
1529 \param[in] field Name of the register bit field.
1530 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
1531 \return Masked and shifted value.
1532 */
1533 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
1534
1535 /**
1536 \brief Mask and shift a register value to extract a bit filed value.
1537 \param[in] field Name of the register bit field.
1538 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
1539 \return Masked and shifted bit field value.
1540 */
1541 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
1542
1543 /*@} end of group CMSIS_core_bitfield */
1544
1545
1546 /**
1547 \ingroup CMSIS_core_register
1548 \defgroup CMSIS_core_base Core Definitions
1549 \brief Definitions for base addresses, unions, and structures.
1550 @{
1551 */
1552
1553 /* Memory mapping of Core Hardware */
1554 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
1555 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
1556 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
1557 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
1558 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
1559 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
1560 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
1561 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
1562
1563 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
1564 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
1565 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
1566 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
1567 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
1568 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
1569 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
1570 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
1571
1572 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1573 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
1574 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
1575 #endif
1576
1577 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
1578 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
1579
1580 /*@} */
1581
1582
1583
1584 /*******************************************************************************
1585 * Hardware Abstraction Layer
1586 Core Function Interface contains:
1587 - Core NVIC Functions
1588 - Core SysTick Functions
1589 - Core Debug Functions
1590 - Core Register Access Functions
1591 ******************************************************************************/
1592 /**
1593 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
1594 */
1595
1596
1597
1598 /* ########################## NVIC functions #################################### */
1599 /**
1600 \ingroup CMSIS_Core_FunctionInterface
1601 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
1602 \brief Functions that manage interrupts and exceptions via the NVIC.
1603 @{
1604 */
1605
1606 #ifdef CMSIS_NVIC_VIRTUAL
1607 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
1608 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
1609 #endif
1610 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
1611 #else
1612 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
1613 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
1614 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
1615 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
1616 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
1617 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
1618 #define NVIC_GetActive __NVIC_GetActive
1619 #ifdef KERNEL_NUTTX
1620 #define NVIC_SetPriority(a,b) __NVIC_SetPriority(a,5)
1621 #else
1622 #define NVIC_SetPriority __NVIC_SetPriority
1623 #endif
1624 #define NVIC_GetPriority __NVIC_GetPriority
1625 #define NVIC_SystemReset __NVIC_SystemReset
1626 #endif /* CMSIS_NVIC_VIRTUAL */
1627
1628 #ifdef CMSIS_VECTAB_VIRTUAL
1629 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1630 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
1631 #endif
1632 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1633 #else
1634 #ifdef KERNEL_NUTTX
1635 typedef int (*xcpt_t)(int irq, void *context, void *arg);
1636 void nuttx_irq_attach(IRQn_Type IRQn, xcpt_t isr, uint32_t arg);
1637 int up_irq_handler(int irq, FAR void *context, FAR void *arg);
1638 bool nuttx_irq_check(IRQn_Type IRQn, bool isEnable);
1639 #define NVIC_SetVector(a,b) nuttx_irq_attach(a,up_irq_handler,b)
1640 #define NVIC_EnableIRQ(a) do { if (nuttx_irq_check(a,true)) __NVIC_EnableIRQ(a);}while (0)
1641 #define NVIC_DisableIRQ(a) do { if (nuttx_irq_check(a,false)) __NVIC_DisableIRQ(a);}while (0)
1642 #else
1643 #define NVIC_SetVector __NVIC_SetVector
1644 #define NVIC_EnableIRQ __NVIC_EnableIRQ
1645 #define NVIC_DisableIRQ __NVIC_DisableIRQ
1646 #endif
1647 #define NVIC_GetVector __NVIC_GetVector
1648 #endif /* (CMSIS_VECTAB_VIRTUAL) */
1649
1650 #define NVIC_USER_IRQ_OFFSET 16
1651
1652
1653 /* The following EXC_RETURN values are saved the LR on exception entry */
1654 #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
1655 #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
1656 #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
1657 #define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */
1658 #define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */
1659 #define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */
1660
1661
1662 /**
1663 \brief Set Priority Grouping
1664 \details Sets the priority grouping field using the required unlock sequence.
1665 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
1666 Only values from 0..7 are used.
1667 In case of a conflict between priority grouping and available
1668 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1669 \param [in] PriorityGroup Priority grouping field.
1670 */
__NVIC_SetPriorityGrouping(uint32_t PriorityGroup)1671 __STATIC_FORCEINLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
1672 {
1673 uint32_t reg_value;
1674 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1675
1676 reg_value = SCB->AIRCR; /* read old register configuration */
1677 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
1678 reg_value = (reg_value |
1679 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1680 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
1681 SCB->AIRCR = reg_value;
1682 }
1683
1684
1685 /**
1686 \brief Get Priority Grouping
1687 \details Reads the priority grouping field from the NVIC Interrupt Controller.
1688 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
1689 */
__NVIC_GetPriorityGrouping(void)1690 __STATIC_FORCEINLINE uint32_t __NVIC_GetPriorityGrouping(void)
1691 {
1692 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
1693 }
1694
1695
1696 /**
1697 \brief Enable Interrupt
1698 \details Enables a device specific interrupt in the NVIC interrupt controller.
1699 \param [in] IRQn Device specific interrupt number.
1700 \note IRQn must not be negative.
1701 */
__NVIC_EnableIRQ(IRQn_Type IRQn)1702 __STATIC_FORCEINLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
1703 {
1704 if ((int32_t)(IRQn) >= 0)
1705 {
1706 __COMPILER_BARRIER();
1707 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1708 __COMPILER_BARRIER();
1709 }
1710 }
1711
1712
1713 /**
1714 \brief Get Interrupt Enable status
1715 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
1716 \param [in] IRQn Device specific interrupt number.
1717 \return 0 Interrupt is not enabled.
1718 \return 1 Interrupt is enabled.
1719 \note IRQn must not be negative.
1720 */
__NVIC_GetEnableIRQ(IRQn_Type IRQn)1721 __STATIC_FORCEINLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
1722 {
1723 if ((int32_t)(IRQn) >= 0)
1724 {
1725 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1726 }
1727 else
1728 {
1729 return(0U);
1730 }
1731 }
1732
1733
1734 /**
1735 \brief Disable Interrupt
1736 \details Disables a device specific interrupt in the NVIC interrupt controller.
1737 \param [in] IRQn Device specific interrupt number.
1738 \note IRQn must not be negative.
1739 */
__NVIC_DisableIRQ(IRQn_Type IRQn)1740 __STATIC_FORCEINLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
1741 {
1742 if ((int32_t)(IRQn) >= 0)
1743 {
1744 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1745 __DSB();
1746 __ISB();
1747 }
1748 }
1749
1750
1751 /**
1752 \brief Get Pending Interrupt
1753 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
1754 \param [in] IRQn Device specific interrupt number.
1755 \return 0 Interrupt status is not pending.
1756 \return 1 Interrupt status is pending.
1757 \note IRQn must not be negative.
1758 */
__NVIC_GetPendingIRQ(IRQn_Type IRQn)1759 __STATIC_FORCEINLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
1760 {
1761 if ((int32_t)(IRQn) >= 0)
1762 {
1763 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1764 }
1765 else
1766 {
1767 return(0U);
1768 }
1769 }
1770
1771
1772 /**
1773 \brief Set Pending Interrupt
1774 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
1775 \param [in] IRQn Device specific interrupt number.
1776 \note IRQn must not be negative.
1777 */
__NVIC_SetPendingIRQ(IRQn_Type IRQn)1778 __STATIC_FORCEINLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
1779 {
1780 if ((int32_t)(IRQn) >= 0)
1781 {
1782 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1783 }
1784 }
1785
1786
1787 /**
1788 \brief Clear Pending Interrupt
1789 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
1790 \param [in] IRQn Device specific interrupt number.
1791 \note IRQn must not be negative.
1792 */
__NVIC_ClearPendingIRQ(IRQn_Type IRQn)1793 __STATIC_FORCEINLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1794 {
1795 if ((int32_t)(IRQn) >= 0)
1796 {
1797 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1798 }
1799 }
1800
1801
1802 /**
1803 \brief Get Active Interrupt
1804 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
1805 \param [in] IRQn Device specific interrupt number.
1806 \return 0 Interrupt status is not active.
1807 \return 1 Interrupt status is active.
1808 \note IRQn must not be negative.
1809 */
__NVIC_GetActive(IRQn_Type IRQn)1810 __STATIC_FORCEINLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
1811 {
1812 if ((int32_t)(IRQn) >= 0)
1813 {
1814 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1815 }
1816 else
1817 {
1818 return(0U);
1819 }
1820 }
1821
1822
1823 /**
1824 \brief Set Interrupt Priority
1825 \details Sets the priority of a device specific interrupt or a processor exception.
1826 The interrupt number can be positive to specify a device specific interrupt,
1827 or negative to specify a processor exception.
1828 \param [in] IRQn Interrupt number.
1829 \param [in] priority Priority to set.
1830 \note The priority cannot be set for every processor exception.
1831 */
__NVIC_SetPriority(IRQn_Type IRQn,uint32_t priority)1832 __STATIC_FORCEINLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1833 {
1834 if ((int32_t)(IRQn) >= 0)
1835 {
1836 NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
1837 }
1838 else
1839 {
1840 SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
1841 }
1842 }
1843
1844
1845 /**
1846 \brief Get Interrupt Priority
1847 \details Reads the priority of a device specific interrupt or a processor exception.
1848 The interrupt number can be positive to specify a device specific interrupt,
1849 or negative to specify a processor exception.
1850 \param [in] IRQn Interrupt number.
1851 \return Interrupt Priority.
1852 Value is aligned automatically to the implemented priority bits of the microcontroller.
1853 */
__NVIC_GetPriority(IRQn_Type IRQn)1854 __STATIC_FORCEINLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
1855 {
1856
1857 if ((int32_t)(IRQn) >= 0)
1858 {
1859 return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
1860 }
1861 else
1862 {
1863 return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
1864 }
1865 }
1866
1867
1868 /**
1869 \brief Encode Priority
1870 \details Encodes the priority for an interrupt with the given priority group,
1871 preemptive priority value, and subpriority value.
1872 In case of a conflict between priority grouping and available
1873 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1874 \param [in] PriorityGroup Used priority group.
1875 \param [in] PreemptPriority Preemptive priority value (starting from 0).
1876 \param [in] SubPriority Subpriority value (starting from 0).
1877 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
1878 */
NVIC_EncodePriority(uint32_t PriorityGroup,uint32_t PreemptPriority,uint32_t SubPriority)1879 __STATIC_FORCEINLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
1880 {
1881 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1882 uint32_t PreemptPriorityBits;
1883 uint32_t SubPriorityBits;
1884
1885 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1886 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1887
1888 return (
1889 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
1890 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
1891 );
1892 }
1893
1894
1895 /**
1896 \brief Decode Priority
1897 \details Decodes an interrupt priority value with a given priority group to
1898 preemptive priority value and subpriority value.
1899 In case of a conflict between priority grouping and available
1900 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
1901 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
1902 \param [in] PriorityGroup Used priority group.
1903 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
1904 \param [out] pSubPriority Subpriority value (starting from 0).
1905 */
NVIC_DecodePriority(uint32_t Priority,uint32_t PriorityGroup,uint32_t * const pPreemptPriority,uint32_t * const pSubPriority)1906 __STATIC_FORCEINLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
1907 {
1908 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1909 uint32_t PreemptPriorityBits;
1910 uint32_t SubPriorityBits;
1911
1912 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1913 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1914
1915 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
1916 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
1917 }
1918
1919
1920 /**
1921 \brief Set Interrupt Vector
1922 \details Sets an interrupt vector in SRAM based interrupt vector table.
1923 The interrupt number can be positive to specify a device specific interrupt,
1924 or negative to specify a processor exception.
1925 VTOR must been relocated to SRAM before.
1926 \param [in] IRQn Interrupt number
1927 \param [in] vector Address of interrupt handler function
1928 */
__NVIC_SetVector(IRQn_Type IRQn,uint32_t vector)1929 __STATIC_FORCEINLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
1930 {
1931 uint32_t *vectors = (uint32_t *)SCB->VTOR;
1932 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
1933 /* ARM Application Note 321 states that the M4 does not require the architectural barrier */
1934 }
1935
1936
1937 /**
1938 \brief Get Interrupt Vector
1939 \details Reads an interrupt vector from interrupt vector table.
1940 The interrupt number can be positive to specify a device specific interrupt,
1941 or negative to specify a processor exception.
1942 \param [in] IRQn Interrupt number.
1943 \return Address of interrupt handler function
1944 */
__NVIC_GetVector(IRQn_Type IRQn)1945 __STATIC_FORCEINLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
1946 {
1947 uint32_t *vectors = (uint32_t *)SCB->VTOR;
1948 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
1949 }
1950
1951
1952 /**
1953 \brief System Reset
1954 \details Initiates a system reset request to reset the MCU.
1955 */
__NVIC_SystemReset(void)1956 __NO_RETURN __STATIC_FORCEINLINE void __NVIC_SystemReset(void)
1957 {
1958 __DSB(); /* Ensure all outstanding memory accesses included
1959 buffered write are completed before reset */
1960 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1961 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
1962 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
1963 __DSB(); /* Ensure completion of memory access */
1964
1965 for(;;) /* wait until reset */
1966 {
1967 __NOP();
1968 }
1969 }
1970
1971 /*@} end of CMSIS_Core_NVICFunctions */
1972
1973
1974 /* ########################## MPU functions #################################### */
1975
1976 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1977
1978 #include "mpu_armv7.h"
1979
1980 #endif
1981
1982
1983 /* ########################## FPU functions #################################### */
1984 /**
1985 \ingroup CMSIS_Core_FunctionInterface
1986 \defgroup CMSIS_Core_FpuFunctions FPU Functions
1987 \brief Function that provides FPU type.
1988 @{
1989 */
1990
1991 /**
1992 \brief get FPU type
1993 \details returns the FPU type
1994 \returns
1995 - \b 0: No FPU
1996 - \b 1: Single precision FPU
1997 - \b 2: Double + Single precision FPU
1998 */
SCB_GetFPUType(void)1999 __STATIC_FORCEINLINE uint32_t SCB_GetFPUType(void)
2000 {
2001 uint32_t mvfr0;
2002
2003 mvfr0 = FPU->MVFR0;
2004 if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
2005 {
2006 return 1U; /* Single precision FPU */
2007 }
2008 else
2009 {
2010 return 0U; /* No FPU */
2011 }
2012 }
2013
2014
2015 /*@} end of CMSIS_Core_FpuFunctions */
2016
2017
2018
2019 /* ################################## SysTick function ############################################ */
2020 /**
2021 \ingroup CMSIS_Core_FunctionInterface
2022 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
2023 \brief Functions that configure the System.
2024 @{
2025 */
2026
2027 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
2028
2029 /**
2030 \brief System Tick Configuration
2031 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
2032 Counter is in free running mode to generate periodic interrupts.
2033 \param [in] ticks Number of ticks between two interrupts.
2034 \return 0 Function succeeded.
2035 \return 1 Function failed.
2036 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
2037 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
2038 must contain a vendor-specific implementation of this function.
2039 */
SysTick_Config(uint32_t ticks)2040 __STATIC_FORCEINLINE uint32_t SysTick_Config(uint32_t ticks)
2041 {
2042 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
2043 {
2044 return (1UL); /* Reload value impossible */
2045 }
2046
2047 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
2048 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
2049 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
2050 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
2051 SysTick_CTRL_TICKINT_Msk |
2052 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
2053 return (0UL); /* Function successful */
2054 }
2055
2056 #endif
2057
2058 /*@} end of CMSIS_Core_SysTickFunctions */
2059
2060
2061
2062 /* ##################################### Debug In/Output function ########################################### */
2063 /**
2064 \ingroup CMSIS_Core_FunctionInterface
2065 \defgroup CMSIS_core_DebugFunctions ITM Functions
2066 \brief Functions that access the ITM debug interface.
2067 @{
2068 */
2069
2070 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
2071 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
2072
2073
2074 /**
2075 \brief ITM Send Character
2076 \details Transmits a character via the ITM channel 0, and
2077 \li Just returns when no debugger is connected that has booked the output.
2078 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
2079 \param [in] ch Character to transmit.
2080 \returns Character to transmit.
2081 */
ITM_SendChar(uint32_t ch)2082 __STATIC_FORCEINLINE uint32_t ITM_SendChar (uint32_t ch)
2083 {
2084 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
2085 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
2086 {
2087 while (ITM->PORT[0U].u32 == 0UL)
2088 {
2089 __NOP();
2090 }
2091 ITM->PORT[0U].u8 = (uint8_t)ch;
2092 }
2093 return (ch);
2094 }
2095
2096
2097 /**
2098 \brief ITM Receive Character
2099 \details Inputs a character via the external variable \ref ITM_RxBuffer.
2100 \return Received character.
2101 \return -1 No character pending.
2102 */
ITM_ReceiveChar(void)2103 __STATIC_FORCEINLINE int32_t ITM_ReceiveChar (void)
2104 {
2105 int32_t ch = -1; /* no character available */
2106
2107 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
2108 {
2109 ch = ITM_RxBuffer;
2110 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
2111 }
2112
2113 return (ch);
2114 }
2115
2116
2117 /**
2118 \brief ITM Check Character
2119 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
2120 \return 0 No character available.
2121 \return 1 Character available.
2122 */
ITM_CheckChar(void)2123 __STATIC_FORCEINLINE int32_t ITM_CheckChar (void)
2124 {
2125
2126 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
2127 {
2128 return (0); /* no character available */
2129 }
2130 else
2131 {
2132 return (1); /* character available */
2133 }
2134 }
2135
2136 /*@} end of CMSIS_core_DebugFunctions */
2137
2138 #endif // !__ASSEMBLER__
2139
2140
2141 #ifdef __cplusplus
2142 }
2143 #endif
2144
2145 #endif /* __CORE_CM4_H_DEPENDANT */
2146
2147 #endif /* __CMSIS_GENERIC */
2148