1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
4 *
5 * Based on da830evm.c. Original Copyrights follow:
6 *
7 * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
8 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
9 */
10
11 #include <common.h>
12 #include <dm.h>
13 #include <env.h>
14 #include <i2c.h>
15 #include <net.h>
16 #include <spi.h>
17 #include <spi_flash.h>
18 #include <asm/arch/hardware.h>
19 #include <asm/ti-common/davinci_nand.h>
20 #include <asm/arch/emac_defs.h>
21 #include <asm/arch/pinmux_defs.h>
22 #include <asm/io.h>
23 #include <asm/arch/davinci_misc.h>
24 #include <linux/errno.h>
25 #include <hwconfig.h>
26 #include <asm/mach-types.h>
27 #include <asm/gpio.h>
28
29 #ifdef CONFIG_MMC_DAVINCI
30 #include <mmc.h>
31 #include <asm/arch/sdmmc_defs.h>
32 #endif
33
34 DECLARE_GLOBAL_DATA_PTR;
35
36 #ifdef CONFIG_DRIVER_TI_EMAC
37 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
38 #define HAS_RMII 1
39 #else
40 #define HAS_RMII 0
41 #endif
42 #endif /* CONFIG_DRIVER_TI_EMAC */
43
44 #define CFG_MAC_ADDR_SPI_BUS 0
45 #define CFG_MAC_ADDR_SPI_CS 0
46 #define CFG_MAC_ADDR_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
47 #define CFG_MAC_ADDR_SPI_MODE SPI_MODE_3
48
49 #define CFG_MAC_ADDR_OFFSET (flash->size - SZ_64K)
50
51 #ifdef CONFIG_MAC_ADDR_IN_SPIFLASH
get_mac_addr(u8 * addr)52 static int get_mac_addr(u8 *addr)
53 {
54 struct spi_flash *flash;
55 int ret;
56
57 flash = spi_flash_probe(CFG_MAC_ADDR_SPI_BUS, CFG_MAC_ADDR_SPI_CS,
58 CFG_MAC_ADDR_SPI_MAX_HZ, CFG_MAC_ADDR_SPI_MODE);
59 if (!flash) {
60 printf("Error - unable to probe SPI flash.\n");
61 return -1;
62 }
63
64 ret = spi_flash_read(flash, (CFG_MAC_ADDR_OFFSET), 6, addr);
65 if (ret) {
66 printf("Error - unable to read MAC address from SPI flash.\n");
67 return -1;
68 }
69
70 return ret;
71 }
72 #endif
73
dsp_lpsc_on(unsigned domain,unsigned int id)74 void dsp_lpsc_on(unsigned domain, unsigned int id)
75 {
76 dv_reg_p mdstat, mdctl, ptstat, ptcmd;
77 struct davinci_psc_regs *psc_regs;
78
79 psc_regs = davinci_psc0_regs;
80 mdstat = &psc_regs->psc0.mdstat[id];
81 mdctl = &psc_regs->psc0.mdctl[id];
82 ptstat = &psc_regs->ptstat;
83 ptcmd = &psc_regs->ptcmd;
84
85 while (*ptstat & (0x1 << domain))
86 ;
87
88 if ((*mdstat & 0x1f) == 0x03)
89 return; /* Already on and enabled */
90
91 *mdctl |= 0x03;
92
93 *ptcmd = 0x1 << domain;
94
95 while (*ptstat & (0x1 << domain))
96 ;
97 while ((*mdstat & 0x1f) != 0x03)
98 ; /* Probably an overkill... */
99 }
100
dspwake(void)101 static void dspwake(void)
102 {
103 unsigned *resetvect = (unsigned *)DAVINCI_L3CBARAM_BASE;
104 u32 val;
105
106 /* if the device is ARM only, return */
107 if ((readl(CHIP_REV_ID_REG) & 0x3f) == 0x10)
108 return;
109
110 if (hwconfig_subarg_cmp_f("dsp", "wake", "no", NULL))
111 return;
112
113 *resetvect++ = 0x1E000; /* DSP Idle */
114 /* clear out the next 10 words as NOP */
115 memset(resetvect, 0, sizeof(unsigned) *10);
116
117 /* setup the DSP reset vector */
118 writel(DAVINCI_L3CBARAM_BASE, HOST1CFG);
119
120 dsp_lpsc_on(1, DAVINCI_LPSC_GEM);
121 val = readl(PSC0_MDCTL + (15 * 4));
122 val |= 0x100;
123 writel(val, (PSC0_MDCTL + (15 * 4)));
124 }
125
misc_init_r(void)126 int misc_init_r(void)
127 {
128 dspwake();
129
130 #if defined(CONFIG_MAC_ADDR_IN_SPIFLASH) || defined(CONFIG_MAC_ADDR_IN_EEPROM)
131
132 uchar env_enetaddr[6];
133 int enetaddr_found;
134
135 enetaddr_found = eth_env_get_enetaddr("ethaddr", env_enetaddr);
136
137 #endif
138
139 #ifdef CONFIG_MAC_ADDR_IN_SPIFLASH
140 int spi_mac_read;
141 uchar buff[6];
142
143 spi_mac_read = get_mac_addr(buff);
144 buff[0] = 0;
145
146 /*
147 * MAC address not present in the environment
148 * try and read the MAC address from SPI flash
149 * and set it.
150 */
151 if (!enetaddr_found) {
152 if (!spi_mac_read) {
153 if (is_valid_ethaddr(buff)) {
154 if (eth_env_set_enetaddr("ethaddr", buff)) {
155 printf("Warning: Failed to "
156 "set MAC address from SPI flash\n");
157 }
158 } else {
159 printf("Warning: Invalid "
160 "MAC address read from SPI flash\n");
161 }
162 }
163 } else {
164 /*
165 * MAC address present in environment compare it with
166 * the MAC address in SPI flash and warn on mismatch
167 */
168 if (!spi_mac_read && is_valid_ethaddr(buff) &&
169 memcmp(env_enetaddr, buff, 6))
170 printf("Warning: MAC address in SPI flash don't match "
171 "with the MAC address in the environment\n");
172 printf("Default using MAC address from environment\n");
173 }
174
175 #elif defined(CONFIG_MAC_ADDR_IN_EEPROM)
176 uint8_t enetaddr[8];
177 int eeprom_mac_read;
178
179 /* Read Ethernet MAC address from EEPROM */
180 eeprom_mac_read = dvevm_read_mac_address(enetaddr);
181
182 /*
183 * MAC address not present in the environment
184 * try and read the MAC address from EEPROM flash
185 * and set it.
186 */
187 if (!enetaddr_found) {
188 if (eeprom_mac_read)
189 /* Set Ethernet MAC address from EEPROM */
190 davinci_sync_env_enetaddr(enetaddr);
191 } else {
192 /*
193 * MAC address present in environment compare it with
194 * the MAC address in EEPROM and warn on mismatch
195 */
196 if (eeprom_mac_read && memcmp(enetaddr, env_enetaddr, 6))
197 printf("Warning: MAC address in EEPROM don't match "
198 "with the MAC address in the environment\n");
199 printf("Default using MAC address from environment\n");
200 }
201
202 #endif
203 return 0;
204 }
205
206 static const struct pinmux_config gpio_pins[] = {
207 #ifdef CONFIG_USE_NOR
208 /* GP0[11] is required for NOR to work on Rev 3 EVMs */
209 { pinmux(0), 8, 4 }, /* GP0[11] */
210 #endif
211 #ifdef CONFIG_MMC_DAVINCI
212 /* GP0[11] is required for SD to work on Rev 3 EVMs */
213 { pinmux(0), 8, 4 }, /* GP0[11] */
214 #endif
215 };
216
217 const struct pinmux_resource pinmuxes[] = {
218 #ifdef CONFIG_DRIVER_TI_EMAC
219 PINMUX_ITEM(emac_pins_mdio),
220 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
221 PINMUX_ITEM(emac_pins_rmii),
222 #else
223 PINMUX_ITEM(emac_pins_mii),
224 #endif
225 #endif
226 #ifdef CONFIG_SPI_FLASH
227 PINMUX_ITEM(spi1_pins_base),
228 PINMUX_ITEM(spi1_pins_scs0),
229 #endif
230 PINMUX_ITEM(uart2_pins_txrx),
231 PINMUX_ITEM(uart2_pins_rtscts),
232 PINMUX_ITEM(i2c0_pins),
233 #ifdef CONFIG_NAND_DAVINCI
234 PINMUX_ITEM(emifa_pins_cs3),
235 PINMUX_ITEM(emifa_pins_cs4),
236 PINMUX_ITEM(emifa_pins_nand),
237 #elif defined(CONFIG_USE_NOR)
238 PINMUX_ITEM(emifa_pins_cs2),
239 PINMUX_ITEM(emifa_pins_nor),
240 #endif
241 PINMUX_ITEM(gpio_pins),
242 #ifdef CONFIG_MMC_DAVINCI
243 PINMUX_ITEM(mmc0_pins),
244 #endif
245 };
246
247 const int pinmuxes_size = ARRAY_SIZE(pinmuxes);
248
249 const struct lpsc_resource lpsc[] = {
250 { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */
251 { DAVINCI_LPSC_SPI1 }, /* Serial Flash */
252 { DAVINCI_LPSC_EMAC }, /* image download */
253 { DAVINCI_LPSC_UART2 }, /* console */
254 { DAVINCI_LPSC_GPIO },
255 #ifdef CONFIG_MMC_DAVINCI
256 { DAVINCI_LPSC_MMC_SD },
257 #endif
258 };
259
260 const int lpsc_size = ARRAY_SIZE(lpsc);
261
262 #ifndef CONFIG_DA850_EVM_MAX_CPU_CLK
263 #define CONFIG_DA850_EVM_MAX_CPU_CLK 300000000
264 #endif
265
266 #define REV_AM18X_EVM 0x100
267
268 /*
269 * get_board_rev() - setup to pass kernel board revision information
270 * Returns:
271 * bit[0-3] Maximum cpu clock rate supported by onboard SoC
272 * 0000b - 300 MHz
273 * 0001b - 372 MHz
274 * 0010b - 408 MHz
275 * 0011b - 456 MHz
276 */
get_board_rev(void)277 u32 get_board_rev(void)
278 {
279 char *s;
280 u32 maxcpuclk = CONFIG_DA850_EVM_MAX_CPU_CLK;
281 u32 rev = 0;
282
283 s = env_get("maxcpuclk");
284 if (s)
285 maxcpuclk = simple_strtoul(s, NULL, 10);
286
287 if (maxcpuclk >= 456000000)
288 rev = 3;
289 else if (maxcpuclk >= 408000000)
290 rev = 2;
291 else if (maxcpuclk >= 372000000)
292 rev = 1;
293 return rev;
294 }
295
board_early_init_f(void)296 int board_early_init_f(void)
297 {
298 /*
299 * Power on required peripherals
300 * ARM does not have access by default to PSC0 and PSC1
301 * assuming here that the DSP bootloader has set the IOPU
302 * such that PSC access is available to ARM
303 */
304 if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
305 return 1;
306
307 return 0;
308 }
309
board_init(void)310 int board_init(void)
311 {
312 irq_init();
313
314 #ifdef CONFIG_NAND_DAVINCI
315 /*
316 * NAND CS setup - cycle counts based on da850evm NAND timings in the
317 * Linux kernel @ 25MHz EMIFA
318 */
319 writel((DAVINCI_ABCR_WSETUP(2) |
320 DAVINCI_ABCR_WSTROBE(2) |
321 DAVINCI_ABCR_WHOLD(1) |
322 DAVINCI_ABCR_RSETUP(1) |
323 DAVINCI_ABCR_RSTROBE(4) |
324 DAVINCI_ABCR_RHOLD(0) |
325 DAVINCI_ABCR_TA(1) |
326 DAVINCI_ABCR_ASIZE_8BIT),
327 &davinci_emif_regs->ab2cr); /* CS3 */
328 #endif
329
330 /* arch number of the board */
331 gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA850_EVM;
332
333 /* address of boot parameters */
334 gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
335
336 /* setup the SUSPSRC for ARM to control emulation suspend */
337 writel(readl(&davinci_syscfg_regs->suspsrc) &
338 ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
339 DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
340 DAVINCI_SYSCFG_SUSPSRC_UART2),
341 &davinci_syscfg_regs->suspsrc);
342
343 #ifdef CONFIG_USE_NOR
344 /* Set the GPIO direction as output */
345 clrbits_le32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11));
346
347 /* Set the output as low */
348 writel(0x01 << 11, GPIO_BANK0_REG_CLR_ADDR);
349 #endif
350
351 #ifdef CONFIG_MMC_DAVINCI
352 /* Set the GPIO direction as output */
353 clrbits_le32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11));
354
355 /* Set the output as high */
356 writel(0x01 << 11, GPIO_BANK0_REG_SET_ADDR);
357 #endif
358
359 #ifdef CONFIG_DRIVER_TI_EMAC
360 davinci_emac_mii_mode_sel(HAS_RMII);
361 #endif /* CONFIG_DRIVER_TI_EMAC */
362
363 return 0;
364 }
365
366 #ifdef CONFIG_DRIVER_TI_EMAC
367
368 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
369 /**
370 * rmii_hw_init
371 *
372 * DA850/OMAP-L138 EVM can interface to a daughter card for
373 * additional features. This card has an I2C GPIO Expander TCA6416
374 * to select the required functions like camera, RMII Ethernet,
375 * character LCD, video.
376 *
377 * Initialization of the expander involves configuring the
378 * polarity and direction of the ports. P07-P05 are used here.
379 * These ports are connected to a Mux chip which enables only one
380 * functionality at a time.
381 *
382 * For RMII phy to respond, the MII MDIO clock has to be disabled
383 * since both the PHY devices have address as zero. The MII MDIO
384 * clock is controlled via GPIO2[6].
385 *
386 * This code is valid for Beta version of the hardware
387 */
rmii_hw_init(void)388 int rmii_hw_init(void)
389 {
390 const struct pinmux_config gpio_pins[] = {
391 { pinmux(6), 8, 1 }
392 };
393 u_int8_t buf[2];
394 unsigned int temp;
395 int ret;
396
397 /* PinMux for GPIO */
398 if (davinci_configure_pin_mux(gpio_pins, ARRAY_SIZE(gpio_pins)) != 0)
399 return 1;
400
401 /* I2C Exapnder configuration */
402 /* Set polarity to non-inverted */
403 buf[0] = 0x0;
404 buf[1] = 0x0;
405 ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 4, 1, buf, 2);
406 if (ret) {
407 printf("\nExpander @ 0x%02x write FAILED!!!\n",
408 CONFIG_SYS_I2C_EXPANDER_ADDR);
409 return ret;
410 }
411
412 /* Configure P07-P05 as outputs */
413 buf[0] = 0x1f;
414 buf[1] = 0xff;
415 ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 6, 1, buf, 2);
416 if (ret) {
417 printf("\nExpander @ 0x%02x write FAILED!!!\n",
418 CONFIG_SYS_I2C_EXPANDER_ADDR);
419 }
420
421 /* For Ethernet RMII selection
422 * P07(SelA)=0
423 * P06(SelB)=1
424 * P05(SelC)=1
425 */
426 if (i2c_read(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) {
427 printf("\nExpander @ 0x%02x read FAILED!!!\n",
428 CONFIG_SYS_I2C_EXPANDER_ADDR);
429 }
430
431 buf[0] &= 0x1f;
432 buf[0] |= (0 << 7) | (1 << 6) | (1 << 5);
433 if (i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) {
434 printf("\nExpander @ 0x%02x write FAILED!!!\n",
435 CONFIG_SYS_I2C_EXPANDER_ADDR);
436 }
437
438 /* Set the output as high */
439 temp = REG(GPIO_BANK2_REG_SET_ADDR);
440 temp |= (0x01 << 6);
441 REG(GPIO_BANK2_REG_SET_ADDR) = temp;
442
443 /* Set the GPIO direction as output */
444 temp = REG(GPIO_BANK2_REG_DIR_ADDR);
445 temp &= ~(0x01 << 6);
446 REG(GPIO_BANK2_REG_DIR_ADDR) = temp;
447
448 return 0;
449 }
450 #endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */
451
452 /*
453 * Initializes on-board ethernet controllers.
454 */
board_eth_init(bd_t * bis)455 int board_eth_init(bd_t *bis)
456 {
457 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
458 /* Select RMII fucntion through the expander */
459 if (rmii_hw_init())
460 printf("RMII hardware init failed!!!\n");
461 #endif
462 return 0;
463 }
464 #endif /* CONFIG_DRIVER_TI_EMAC */
465