1 /*
2 * Freescale QuadSPI driver.
3 *
4 * Copyright (C) 2013 Freescale Semiconductor, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/interrupt.h>
14 #include <linux/errno.h>
15 #include <linux/platform_device.h>
16 #include <linux/sched.h>
17 #include <linux/delay.h>
18 #include <linux/io.h>
19 #include <linux/clk.h>
20 #include <linux/err.h>
21 #include <linux/of.h>
22 #include <linux/of_device.h>
23 #include <linux/timer.h>
24 #include <linux/jiffies.h>
25 #include <linux/completion.h>
26 #include <linux/mtd/mtd.h>
27 #include <linux/mtd/partitions.h>
28 #include <linux/mtd/spi-nor.h>
29 #include <linux/mutex.h>
30 #include <linux/pm_qos.h>
31 #include <linux/sizes.h>
32
33 /* Controller needs driver to swap endian */
34 #define QUADSPI_QUIRK_SWAP_ENDIAN (1 << 0)
35 /* Controller needs 4x internal clock */
36 #define QUADSPI_QUIRK_4X_INT_CLK (1 << 1)
37 /*
38 * TKT253890, Controller needs driver to fill txfifo till 16 byte to
39 * trigger data transfer even though extern data will not transferred.
40 */
41 #define QUADSPI_QUIRK_TKT253890 (1 << 2)
42 /* Controller cannot wake up from wait mode, TKT245618 */
43 #define QUADSPI_QUIRK_TKT245618 (1 << 3)
44
45 /* The registers */
46 #define QUADSPI_MCR 0x00
47 #define QUADSPI_MCR_RESERVED_SHIFT 16
48 #define QUADSPI_MCR_RESERVED_MASK (0xF << QUADSPI_MCR_RESERVED_SHIFT)
49 #define QUADSPI_MCR_MDIS_SHIFT 14
50 #define QUADSPI_MCR_MDIS_MASK (1 << QUADSPI_MCR_MDIS_SHIFT)
51 #define QUADSPI_MCR_CLR_TXF_SHIFT 11
52 #define QUADSPI_MCR_CLR_TXF_MASK (1 << QUADSPI_MCR_CLR_TXF_SHIFT)
53 #define QUADSPI_MCR_CLR_RXF_SHIFT 10
54 #define QUADSPI_MCR_CLR_RXF_MASK (1 << QUADSPI_MCR_CLR_RXF_SHIFT)
55 #define QUADSPI_MCR_DDR_EN_SHIFT 7
56 #define QUADSPI_MCR_DDR_EN_MASK (1 << QUADSPI_MCR_DDR_EN_SHIFT)
57 #define QUADSPI_MCR_END_CFG_SHIFT 2
58 #define QUADSPI_MCR_END_CFG_MASK (3 << QUADSPI_MCR_END_CFG_SHIFT)
59 #define QUADSPI_MCR_SWRSTHD_SHIFT 1
60 #define QUADSPI_MCR_SWRSTHD_MASK (1 << QUADSPI_MCR_SWRSTHD_SHIFT)
61 #define QUADSPI_MCR_SWRSTSD_SHIFT 0
62 #define QUADSPI_MCR_SWRSTSD_MASK (1 << QUADSPI_MCR_SWRSTSD_SHIFT)
63
64 #define QUADSPI_IPCR 0x08
65 #define QUADSPI_IPCR_SEQID_SHIFT 24
66 #define QUADSPI_IPCR_SEQID_MASK (0xF << QUADSPI_IPCR_SEQID_SHIFT)
67
68 #define QUADSPI_BUF0CR 0x10
69 #define QUADSPI_BUF1CR 0x14
70 #define QUADSPI_BUF2CR 0x18
71 #define QUADSPI_BUFXCR_INVALID_MSTRID 0xe
72
73 #define QUADSPI_BUF3CR 0x1c
74 #define QUADSPI_BUF3CR_ALLMST_SHIFT 31
75 #define QUADSPI_BUF3CR_ALLMST_MASK (1 << QUADSPI_BUF3CR_ALLMST_SHIFT)
76 #define QUADSPI_BUF3CR_ADATSZ_SHIFT 8
77 #define QUADSPI_BUF3CR_ADATSZ_MASK (0xFF << QUADSPI_BUF3CR_ADATSZ_SHIFT)
78
79 #define QUADSPI_BFGENCR 0x20
80 #define QUADSPI_BFGENCR_PAR_EN_SHIFT 16
81 #define QUADSPI_BFGENCR_PAR_EN_MASK (1 << (QUADSPI_BFGENCR_PAR_EN_SHIFT))
82 #define QUADSPI_BFGENCR_SEQID_SHIFT 12
83 #define QUADSPI_BFGENCR_SEQID_MASK (0xF << QUADSPI_BFGENCR_SEQID_SHIFT)
84
85 #define QUADSPI_BUF0IND 0x30
86 #define QUADSPI_BUF1IND 0x34
87 #define QUADSPI_BUF2IND 0x38
88 #define QUADSPI_SFAR 0x100
89
90 #define QUADSPI_SMPR 0x108
91 #define QUADSPI_SMPR_DDRSMP_SHIFT 16
92 #define QUADSPI_SMPR_DDRSMP_MASK (7 << QUADSPI_SMPR_DDRSMP_SHIFT)
93 #define QUADSPI_SMPR_FSDLY_SHIFT 6
94 #define QUADSPI_SMPR_FSDLY_MASK (1 << QUADSPI_SMPR_FSDLY_SHIFT)
95 #define QUADSPI_SMPR_FSPHS_SHIFT 5
96 #define QUADSPI_SMPR_FSPHS_MASK (1 << QUADSPI_SMPR_FSPHS_SHIFT)
97 #define QUADSPI_SMPR_HSENA_SHIFT 0
98 #define QUADSPI_SMPR_HSENA_MASK (1 << QUADSPI_SMPR_HSENA_SHIFT)
99
100 #define QUADSPI_RBSR 0x10c
101 #define QUADSPI_RBSR_RDBFL_SHIFT 8
102 #define QUADSPI_RBSR_RDBFL_MASK (0x3F << QUADSPI_RBSR_RDBFL_SHIFT)
103
104 #define QUADSPI_RBCT 0x110
105 #define QUADSPI_RBCT_WMRK_MASK 0x1F
106 #define QUADSPI_RBCT_RXBRD_SHIFT 8
107 #define QUADSPI_RBCT_RXBRD_USEIPS (0x1 << QUADSPI_RBCT_RXBRD_SHIFT)
108
109 #define QUADSPI_TBSR 0x150
110 #define QUADSPI_TBDR 0x154
111 #define QUADSPI_SR 0x15c
112 #define QUADSPI_SR_IP_ACC_SHIFT 1
113 #define QUADSPI_SR_IP_ACC_MASK (0x1 << QUADSPI_SR_IP_ACC_SHIFT)
114 #define QUADSPI_SR_AHB_ACC_SHIFT 2
115 #define QUADSPI_SR_AHB_ACC_MASK (0x1 << QUADSPI_SR_AHB_ACC_SHIFT)
116
117 #define QUADSPI_FR 0x160
118 #define QUADSPI_FR_TFF_MASK 0x1
119
120 #define QUADSPI_SFA1AD 0x180
121 #define QUADSPI_SFA2AD 0x184
122 #define QUADSPI_SFB1AD 0x188
123 #define QUADSPI_SFB2AD 0x18c
124 #define QUADSPI_RBDR 0x200
125
126 #define QUADSPI_LUTKEY 0x300
127 #define QUADSPI_LUTKEY_VALUE 0x5AF05AF0
128
129 #define QUADSPI_LCKCR 0x304
130 #define QUADSPI_LCKER_LOCK 0x1
131 #define QUADSPI_LCKER_UNLOCK 0x2
132
133 #define QUADSPI_RSER 0x164
134 #define QUADSPI_RSER_TFIE (0x1 << 0)
135
136 #define QUADSPI_LUT_BASE 0x310
137
138 /*
139 * The definition of the LUT register shows below:
140 *
141 * ---------------------------------------------------
142 * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
143 * ---------------------------------------------------
144 */
145 #define OPRND0_SHIFT 0
146 #define PAD0_SHIFT 8
147 #define INSTR0_SHIFT 10
148 #define OPRND1_SHIFT 16
149
150 /* Instruction set for the LUT register. */
151 #define LUT_STOP 0
152 #define LUT_CMD 1
153 #define LUT_ADDR 2
154 #define LUT_DUMMY 3
155 #define LUT_MODE 4
156 #define LUT_MODE2 5
157 #define LUT_MODE4 6
158 #define LUT_FSL_READ 7
159 #define LUT_FSL_WRITE 8
160 #define LUT_JMP_ON_CS 9
161 #define LUT_ADDR_DDR 10
162 #define LUT_MODE_DDR 11
163 #define LUT_MODE2_DDR 12
164 #define LUT_MODE4_DDR 13
165 #define LUT_FSL_READ_DDR 14
166 #define LUT_FSL_WRITE_DDR 15
167 #define LUT_DATA_LEARN 16
168
169 /*
170 * The PAD definitions for LUT register.
171 *
172 * The pad stands for the lines number of IO[0:3].
173 * For example, the Quad read need four IO lines, so you should
174 * set LUT_PAD4 which means we use four IO lines.
175 */
176 #define LUT_PAD1 0
177 #define LUT_PAD2 1
178 #define LUT_PAD4 2
179
180 /* Oprands for the LUT register. */
181 #define ADDR24BIT 0x18
182 #define ADDR32BIT 0x20
183
184 /* Macros for constructing the LUT register. */
185 #define LUT0(ins, pad, opr) \
186 (((opr) << OPRND0_SHIFT) | ((LUT_##pad) << PAD0_SHIFT) | \
187 ((LUT_##ins) << INSTR0_SHIFT))
188
189 #define LUT1(ins, pad, opr) (LUT0(ins, pad, opr) << OPRND1_SHIFT)
190
191 /* other macros for LUT register. */
192 #define QUADSPI_LUT(x) (QUADSPI_LUT_BASE + (x) * 4)
193 #define QUADSPI_LUT_NUM 64
194
195 /* SEQID -- we can have 16 seqids at most. */
196 #define SEQID_READ 0
197 #define SEQID_WREN 1
198 #define SEQID_WRDI 2
199 #define SEQID_RDSR 3
200 #define SEQID_SE 4
201 #define SEQID_CHIP_ERASE 5
202 #define SEQID_PP 6
203 #define SEQID_RDID 7
204 #define SEQID_WRSR 8
205 #define SEQID_RDCR 9
206 #define SEQID_EN4B 10
207 #define SEQID_BRWR 11
208
209 #define QUADSPI_MIN_IOMAP SZ_4M
210
211 enum fsl_qspi_devtype {
212 FSL_QUADSPI_VYBRID,
213 FSL_QUADSPI_IMX6SX,
214 FSL_QUADSPI_IMX7D,
215 FSL_QUADSPI_IMX6UL,
216 FSL_QUADSPI_LS1021A,
217 FSL_QUADSPI_LS2080A,
218 };
219
220 struct fsl_qspi_devtype_data {
221 enum fsl_qspi_devtype devtype;
222 int rxfifo;
223 int txfifo;
224 int ahb_buf_size;
225 int driver_data;
226 };
227
228 static const struct fsl_qspi_devtype_data vybrid_data = {
229 .devtype = FSL_QUADSPI_VYBRID,
230 .rxfifo = 128,
231 .txfifo = 64,
232 .ahb_buf_size = 1024,
233 .driver_data = QUADSPI_QUIRK_SWAP_ENDIAN,
234 };
235
236 static const struct fsl_qspi_devtype_data imx6sx_data = {
237 .devtype = FSL_QUADSPI_IMX6SX,
238 .rxfifo = 128,
239 .txfifo = 512,
240 .ahb_buf_size = 1024,
241 .driver_data = QUADSPI_QUIRK_4X_INT_CLK
242 | QUADSPI_QUIRK_TKT245618,
243 };
244
245 static const struct fsl_qspi_devtype_data imx7d_data = {
246 .devtype = FSL_QUADSPI_IMX7D,
247 .rxfifo = 512,
248 .txfifo = 512,
249 .ahb_buf_size = 1024,
250 .driver_data = QUADSPI_QUIRK_TKT253890
251 | QUADSPI_QUIRK_4X_INT_CLK,
252 };
253
254 static const struct fsl_qspi_devtype_data imx6ul_data = {
255 .devtype = FSL_QUADSPI_IMX6UL,
256 .rxfifo = 128,
257 .txfifo = 512,
258 .ahb_buf_size = 1024,
259 .driver_data = QUADSPI_QUIRK_TKT253890
260 | QUADSPI_QUIRK_4X_INT_CLK,
261 };
262
263 static struct fsl_qspi_devtype_data ls1021a_data = {
264 .devtype = FSL_QUADSPI_LS1021A,
265 .rxfifo = 128,
266 .txfifo = 64,
267 .ahb_buf_size = 1024,
268 .driver_data = 0,
269 };
270
271 static const struct fsl_qspi_devtype_data ls2080a_data = {
272 .devtype = FSL_QUADSPI_LS2080A,
273 .rxfifo = 128,
274 .txfifo = 64,
275 .ahb_buf_size = 1024,
276 .driver_data = QUADSPI_QUIRK_TKT253890,
277 };
278
279
280 #define FSL_QSPI_MAX_CHIP 4
281 struct fsl_qspi {
282 struct spi_nor nor[FSL_QSPI_MAX_CHIP];
283 void __iomem *iobase;
284 void __iomem *ahb_addr;
285 u32 memmap_phy;
286 u32 memmap_offs;
287 u32 memmap_len;
288 struct clk *clk, *clk_en;
289 struct device *dev;
290 struct completion c;
291 const struct fsl_qspi_devtype_data *devtype_data;
292 u32 nor_size;
293 u32 nor_num;
294 u32 clk_rate;
295 unsigned int chip_base_addr; /* We may support two chips. */
296 bool has_second_chip;
297 bool big_endian;
298 struct mutex lock;
299 struct pm_qos_request pm_qos_req;
300 };
301
needs_swap_endian(struct fsl_qspi * q)302 static inline int needs_swap_endian(struct fsl_qspi *q)
303 {
304 return q->devtype_data->driver_data & QUADSPI_QUIRK_SWAP_ENDIAN;
305 }
306
needs_4x_clock(struct fsl_qspi * q)307 static inline int needs_4x_clock(struct fsl_qspi *q)
308 {
309 return q->devtype_data->driver_data & QUADSPI_QUIRK_4X_INT_CLK;
310 }
311
needs_fill_txfifo(struct fsl_qspi * q)312 static inline int needs_fill_txfifo(struct fsl_qspi *q)
313 {
314 return q->devtype_data->driver_data & QUADSPI_QUIRK_TKT253890;
315 }
316
needs_wakeup_wait_mode(struct fsl_qspi * q)317 static inline int needs_wakeup_wait_mode(struct fsl_qspi *q)
318 {
319 return q->devtype_data->driver_data & QUADSPI_QUIRK_TKT245618;
320 }
321
322 /*
323 * R/W functions for big- or little-endian registers:
324 * The qSPI controller's endian is independent of the CPU core's endian.
325 * So far, although the CPU core is little-endian but the qSPI have two
326 * versions for big-endian and little-endian.
327 */
qspi_writel(struct fsl_qspi * q,u32 val,void __iomem * addr)328 static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem *addr)
329 {
330 if (q->big_endian)
331 iowrite32be(val, addr);
332 else
333 iowrite32(val, addr);
334 }
335
qspi_readl(struct fsl_qspi * q,void __iomem * addr)336 static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr)
337 {
338 if (q->big_endian)
339 return ioread32be(addr);
340 else
341 return ioread32(addr);
342 }
343
344 /*
345 * An IC bug makes us to re-arrange the 32-bit data.
346 * The following chips, such as IMX6SLX, have fixed this bug.
347 */
fsl_qspi_endian_xchg(struct fsl_qspi * q,u32 a)348 static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a)
349 {
350 return needs_swap_endian(q) ? __swab32(a) : a;
351 }
352
fsl_qspi_unlock_lut(struct fsl_qspi * q)353 static inline void fsl_qspi_unlock_lut(struct fsl_qspi *q)
354 {
355 qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
356 qspi_writel(q, QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
357 }
358
fsl_qspi_lock_lut(struct fsl_qspi * q)359 static inline void fsl_qspi_lock_lut(struct fsl_qspi *q)
360 {
361 qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
362 qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
363 }
364
fsl_qspi_irq_handler(int irq,void * dev_id)365 static irqreturn_t fsl_qspi_irq_handler(int irq, void *dev_id)
366 {
367 struct fsl_qspi *q = dev_id;
368 u32 reg;
369
370 /* clear interrupt */
371 reg = qspi_readl(q, q->iobase + QUADSPI_FR);
372 qspi_writel(q, reg, q->iobase + QUADSPI_FR);
373
374 if (reg & QUADSPI_FR_TFF_MASK)
375 complete(&q->c);
376
377 dev_dbg(q->dev, "QUADSPI_FR : 0x%.8x:0x%.8x\n", q->chip_base_addr, reg);
378 return IRQ_HANDLED;
379 }
380
fsl_qspi_init_lut(struct fsl_qspi * q)381 static void fsl_qspi_init_lut(struct fsl_qspi *q)
382 {
383 void __iomem *base = q->iobase;
384 int rxfifo = q->devtype_data->rxfifo;
385 u32 lut_base;
386 int i;
387
388 struct spi_nor *nor = &q->nor[0];
389 u8 addrlen = (nor->addr_width == 3) ? ADDR24BIT : ADDR32BIT;
390 u8 read_op = nor->read_opcode;
391 u8 read_dm = nor->read_dummy;
392
393 fsl_qspi_unlock_lut(q);
394
395 /* Clear all the LUT table */
396 for (i = 0; i < QUADSPI_LUT_NUM; i++)
397 qspi_writel(q, 0, base + QUADSPI_LUT_BASE + i * 4);
398
399 /* Read */
400 lut_base = SEQID_READ * 4;
401
402 qspi_writel(q, LUT0(CMD, PAD1, read_op) | LUT1(ADDR, PAD1, addrlen),
403 base + QUADSPI_LUT(lut_base));
404 qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) |
405 LUT1(FSL_READ, PAD4, rxfifo),
406 base + QUADSPI_LUT(lut_base + 1));
407
408 /* Write enable */
409 lut_base = SEQID_WREN * 4;
410 qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WREN),
411 base + QUADSPI_LUT(lut_base));
412
413 /* Page Program */
414 lut_base = SEQID_PP * 4;
415
416 qspi_writel(q, LUT0(CMD, PAD1, nor->program_opcode) |
417 LUT1(ADDR, PAD1, addrlen),
418 base + QUADSPI_LUT(lut_base));
419 qspi_writel(q, LUT0(FSL_WRITE, PAD1, 0),
420 base + QUADSPI_LUT(lut_base + 1));
421
422 /* Read Status */
423 lut_base = SEQID_RDSR * 4;
424 qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RDSR) |
425 LUT1(FSL_READ, PAD1, 0x1),
426 base + QUADSPI_LUT(lut_base));
427
428 /* Erase a sector */
429 lut_base = SEQID_SE * 4;
430
431 qspi_writel(q, LUT0(CMD, PAD1, nor->erase_opcode) |
432 LUT1(ADDR, PAD1, addrlen),
433 base + QUADSPI_LUT(lut_base));
434
435 /* Erase the whole chip */
436 lut_base = SEQID_CHIP_ERASE * 4;
437 qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_CHIP_ERASE),
438 base + QUADSPI_LUT(lut_base));
439
440 /* READ ID */
441 lut_base = SEQID_RDID * 4;
442 qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RDID) |
443 LUT1(FSL_READ, PAD1, 0x8),
444 base + QUADSPI_LUT(lut_base));
445
446 /* Write Register */
447 lut_base = SEQID_WRSR * 4;
448 qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WRSR) |
449 LUT1(FSL_WRITE, PAD1, 0x2),
450 base + QUADSPI_LUT(lut_base));
451
452 /* Read Configuration Register */
453 lut_base = SEQID_RDCR * 4;
454 qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RDCR) |
455 LUT1(FSL_READ, PAD1, 0x1),
456 base + QUADSPI_LUT(lut_base));
457
458 /* Write disable */
459 lut_base = SEQID_WRDI * 4;
460 qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WRDI),
461 base + QUADSPI_LUT(lut_base));
462
463 /* Enter 4 Byte Mode (Micron) */
464 lut_base = SEQID_EN4B * 4;
465 qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_EN4B),
466 base + QUADSPI_LUT(lut_base));
467
468 /* Enter 4 Byte Mode (Spansion) */
469 lut_base = SEQID_BRWR * 4;
470 qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_BRWR),
471 base + QUADSPI_LUT(lut_base));
472
473 fsl_qspi_lock_lut(q);
474 }
475
476 /* Get the SEQID for the command */
fsl_qspi_get_seqid(struct fsl_qspi * q,u8 cmd)477 static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd)
478 {
479 switch (cmd) {
480 case SPINOR_OP_READ_1_1_4:
481 case SPINOR_OP_READ_1_1_4_4B:
482 return SEQID_READ;
483 case SPINOR_OP_WREN:
484 return SEQID_WREN;
485 case SPINOR_OP_WRDI:
486 return SEQID_WRDI;
487 case SPINOR_OP_RDSR:
488 return SEQID_RDSR;
489 case SPINOR_OP_SE:
490 return SEQID_SE;
491 case SPINOR_OP_CHIP_ERASE:
492 return SEQID_CHIP_ERASE;
493 case SPINOR_OP_PP:
494 return SEQID_PP;
495 case SPINOR_OP_RDID:
496 return SEQID_RDID;
497 case SPINOR_OP_WRSR:
498 return SEQID_WRSR;
499 case SPINOR_OP_RDCR:
500 return SEQID_RDCR;
501 case SPINOR_OP_EN4B:
502 return SEQID_EN4B;
503 case SPINOR_OP_BRWR:
504 return SEQID_BRWR;
505 default:
506 if (cmd == q->nor[0].erase_opcode)
507 return SEQID_SE;
508 dev_err(q->dev, "Unsupported cmd 0x%.2x\n", cmd);
509 break;
510 }
511 return -EINVAL;
512 }
513
514 static int
fsl_qspi_runcmd(struct fsl_qspi * q,u8 cmd,unsigned int addr,int len)515 fsl_qspi_runcmd(struct fsl_qspi *q, u8 cmd, unsigned int addr, int len)
516 {
517 void __iomem *base = q->iobase;
518 int seqid;
519 u32 reg, reg2;
520 int err;
521
522 init_completion(&q->c);
523 dev_dbg(q->dev, "to 0x%.8x:0x%.8x, len:%d, cmd:%.2x\n",
524 q->chip_base_addr, addr, len, cmd);
525
526 /* save the reg */
527 reg = qspi_readl(q, base + QUADSPI_MCR);
528
529 qspi_writel(q, q->memmap_phy + q->chip_base_addr + addr,
530 base + QUADSPI_SFAR);
531 qspi_writel(q, QUADSPI_RBCT_WMRK_MASK | QUADSPI_RBCT_RXBRD_USEIPS,
532 base + QUADSPI_RBCT);
533 qspi_writel(q, reg | QUADSPI_MCR_CLR_RXF_MASK, base + QUADSPI_MCR);
534
535 do {
536 reg2 = qspi_readl(q, base + QUADSPI_SR);
537 if (reg2 & (QUADSPI_SR_IP_ACC_MASK | QUADSPI_SR_AHB_ACC_MASK)) {
538 udelay(1);
539 dev_dbg(q->dev, "The controller is busy, 0x%x\n", reg2);
540 continue;
541 }
542 break;
543 } while (1);
544
545 /* trigger the LUT now */
546 seqid = fsl_qspi_get_seqid(q, cmd);
547 if (seqid < 0)
548 return seqid;
549
550 qspi_writel(q, (seqid << QUADSPI_IPCR_SEQID_SHIFT) | len,
551 base + QUADSPI_IPCR);
552
553 /* Wait for the interrupt. */
554 if (!wait_for_completion_timeout(&q->c, msecs_to_jiffies(1000))) {
555 dev_err(q->dev,
556 "cmd 0x%.2x timeout, addr@%.8x, FR:0x%.8x, SR:0x%.8x\n",
557 cmd, addr, qspi_readl(q, base + QUADSPI_FR),
558 qspi_readl(q, base + QUADSPI_SR));
559 err = -ETIMEDOUT;
560 } else {
561 err = 0;
562 }
563
564 /* restore the MCR */
565 qspi_writel(q, reg, base + QUADSPI_MCR);
566
567 return err;
568 }
569
570 /* Read out the data from the QUADSPI_RBDR buffer registers. */
fsl_qspi_read_data(struct fsl_qspi * q,int len,u8 * rxbuf)571 static void fsl_qspi_read_data(struct fsl_qspi *q, int len, u8 *rxbuf)
572 {
573 u32 tmp;
574 int i = 0;
575
576 while (len > 0) {
577 tmp = qspi_readl(q, q->iobase + QUADSPI_RBDR + i * 4);
578 tmp = fsl_qspi_endian_xchg(q, tmp);
579 dev_dbg(q->dev, "chip addr:0x%.8x, rcv:0x%.8x\n",
580 q->chip_base_addr, tmp);
581
582 if (len >= 4) {
583 *((u32 *)rxbuf) = tmp;
584 rxbuf += 4;
585 } else {
586 memcpy(rxbuf, &tmp, len);
587 break;
588 }
589
590 len -= 4;
591 i++;
592 }
593 }
594
595 /*
596 * If we have changed the content of the flash by writing or erasing,
597 * we need to invalidate the AHB buffer. If we do not do so, we may read out
598 * the wrong data. The spec tells us reset the AHB domain and Serial Flash
599 * domain at the same time.
600 */
fsl_qspi_invalid(struct fsl_qspi * q)601 static inline void fsl_qspi_invalid(struct fsl_qspi *q)
602 {
603 u32 reg;
604
605 reg = qspi_readl(q, q->iobase + QUADSPI_MCR);
606 reg |= QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK;
607 qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
608
609 /*
610 * The minimum delay : 1 AHB + 2 SFCK clocks.
611 * Delay 1 us is enough.
612 */
613 udelay(1);
614
615 reg &= ~(QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK);
616 qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
617 }
618
fsl_qspi_nor_write(struct fsl_qspi * q,struct spi_nor * nor,u8 opcode,unsigned int to,u32 * txbuf,unsigned count)619 static ssize_t fsl_qspi_nor_write(struct fsl_qspi *q, struct spi_nor *nor,
620 u8 opcode, unsigned int to, u32 *txbuf,
621 unsigned count)
622 {
623 int ret, i, j;
624 u32 tmp;
625
626 dev_dbg(q->dev, "to 0x%.8x:0x%.8x, len : %d\n",
627 q->chip_base_addr, to, count);
628
629 /* clear the TX FIFO. */
630 tmp = qspi_readl(q, q->iobase + QUADSPI_MCR);
631 qspi_writel(q, tmp | QUADSPI_MCR_CLR_TXF_MASK, q->iobase + QUADSPI_MCR);
632
633 /* fill the TX data to the FIFO */
634 for (j = 0, i = ((count + 3) / 4); j < i; j++) {
635 tmp = fsl_qspi_endian_xchg(q, *txbuf);
636 qspi_writel(q, tmp, q->iobase + QUADSPI_TBDR);
637 txbuf++;
638 }
639
640 /* fill the TXFIFO upto 16 bytes for i.MX7d */
641 if (needs_fill_txfifo(q))
642 for (; i < 4; i++)
643 qspi_writel(q, tmp, q->iobase + QUADSPI_TBDR);
644
645 /* Trigger it */
646 ret = fsl_qspi_runcmd(q, opcode, to, count);
647
648 if (ret == 0)
649 return count;
650
651 return ret;
652 }
653
fsl_qspi_set_map_addr(struct fsl_qspi * q)654 static void fsl_qspi_set_map_addr(struct fsl_qspi *q)
655 {
656 int nor_size = q->nor_size;
657 void __iomem *base = q->iobase;
658
659 qspi_writel(q, nor_size + q->memmap_phy, base + QUADSPI_SFA1AD);
660 qspi_writel(q, nor_size * 2 + q->memmap_phy, base + QUADSPI_SFA2AD);
661 qspi_writel(q, nor_size * 3 + q->memmap_phy, base + QUADSPI_SFB1AD);
662 qspi_writel(q, nor_size * 4 + q->memmap_phy, base + QUADSPI_SFB2AD);
663 }
664
665 /*
666 * There are two different ways to read out the data from the flash:
667 * the "IP Command Read" and the "AHB Command Read".
668 *
669 * The IC guy suggests we use the "AHB Command Read" which is faster
670 * then the "IP Command Read". (What's more is that there is a bug in
671 * the "IP Command Read" in the Vybrid.)
672 *
673 * After we set up the registers for the "AHB Command Read", we can use
674 * the memcpy to read the data directly. A "missed" access to the buffer
675 * causes the controller to clear the buffer, and use the sequence pointed
676 * by the QUADSPI_BFGENCR[SEQID] to initiate a read from the flash.
677 */
fsl_qspi_init_ahb_read(struct fsl_qspi * q)678 static int fsl_qspi_init_ahb_read(struct fsl_qspi *q)
679 {
680 void __iomem *base = q->iobase;
681 int seqid;
682
683 /* AHB configuration for access buffer 0/1/2 .*/
684 qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF0CR);
685 qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF1CR);
686 qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF2CR);
687 /*
688 * Set ADATSZ with the maximum AHB buffer size to improve the
689 * read performance.
690 */
691 qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
692 ((q->devtype_data->ahb_buf_size / 8)
693 << QUADSPI_BUF3CR_ADATSZ_SHIFT),
694 base + QUADSPI_BUF3CR);
695
696 /* We only use the buffer3 */
697 qspi_writel(q, 0, base + QUADSPI_BUF0IND);
698 qspi_writel(q, 0, base + QUADSPI_BUF1IND);
699 qspi_writel(q, 0, base + QUADSPI_BUF2IND);
700
701 /* Set the default lut sequence for AHB Read. */
702 seqid = fsl_qspi_get_seqid(q, q->nor[0].read_opcode);
703 if (seqid < 0)
704 return seqid;
705
706 qspi_writel(q, seqid << QUADSPI_BFGENCR_SEQID_SHIFT,
707 q->iobase + QUADSPI_BFGENCR);
708
709 return 0;
710 }
711
712 /* This function was used to prepare and enable QSPI clock */
fsl_qspi_clk_prep_enable(struct fsl_qspi * q)713 static int fsl_qspi_clk_prep_enable(struct fsl_qspi *q)
714 {
715 int ret;
716
717 ret = clk_prepare_enable(q->clk_en);
718 if (ret)
719 return ret;
720
721 ret = clk_prepare_enable(q->clk);
722 if (ret) {
723 clk_disable_unprepare(q->clk_en);
724 return ret;
725 }
726
727 if (needs_wakeup_wait_mode(q))
728 pm_qos_add_request(&q->pm_qos_req, PM_QOS_CPU_DMA_LATENCY, 0);
729
730 return 0;
731 }
732
733 /* This function was used to disable and unprepare QSPI clock */
fsl_qspi_clk_disable_unprep(struct fsl_qspi * q)734 static void fsl_qspi_clk_disable_unprep(struct fsl_qspi *q)
735 {
736 if (needs_wakeup_wait_mode(q))
737 pm_qos_remove_request(&q->pm_qos_req);
738
739 clk_disable_unprepare(q->clk);
740 clk_disable_unprepare(q->clk_en);
741
742 }
743
744 /* We use this function to do some basic init for spi_nor_scan(). */
fsl_qspi_nor_setup(struct fsl_qspi * q)745 static int fsl_qspi_nor_setup(struct fsl_qspi *q)
746 {
747 void __iomem *base = q->iobase;
748 u32 reg;
749 int ret;
750
751 /* disable and unprepare clock to avoid glitch pass to controller */
752 fsl_qspi_clk_disable_unprep(q);
753
754 /* the default frequency, we will change it in the future. */
755 ret = clk_set_rate(q->clk, 66000000);
756 if (ret)
757 return ret;
758
759 ret = fsl_qspi_clk_prep_enable(q);
760 if (ret)
761 return ret;
762
763 /* Reset the module */
764 qspi_writel(q, QUADSPI_MCR_SWRSTSD_MASK | QUADSPI_MCR_SWRSTHD_MASK,
765 base + QUADSPI_MCR);
766 udelay(1);
767
768 /* Init the LUT table. */
769 fsl_qspi_init_lut(q);
770
771 /* Disable the module */
772 qspi_writel(q, QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK,
773 base + QUADSPI_MCR);
774
775 reg = qspi_readl(q, base + QUADSPI_SMPR);
776 qspi_writel(q, reg & ~(QUADSPI_SMPR_FSDLY_MASK
777 | QUADSPI_SMPR_FSPHS_MASK
778 | QUADSPI_SMPR_HSENA_MASK
779 | QUADSPI_SMPR_DDRSMP_MASK), base + QUADSPI_SMPR);
780
781 /* Enable the module */
782 qspi_writel(q, QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK,
783 base + QUADSPI_MCR);
784
785 /* clear all interrupt status */
786 qspi_writel(q, 0xffffffff, q->iobase + QUADSPI_FR);
787
788 /* enable the interrupt */
789 qspi_writel(q, QUADSPI_RSER_TFIE, q->iobase + QUADSPI_RSER);
790
791 return 0;
792 }
793
fsl_qspi_nor_setup_last(struct fsl_qspi * q)794 static int fsl_qspi_nor_setup_last(struct fsl_qspi *q)
795 {
796 unsigned long rate = q->clk_rate;
797 int ret;
798
799 if (needs_4x_clock(q))
800 rate *= 4;
801
802 /* disable and unprepare clock to avoid glitch pass to controller */
803 fsl_qspi_clk_disable_unprep(q);
804
805 ret = clk_set_rate(q->clk, rate);
806 if (ret)
807 return ret;
808
809 ret = fsl_qspi_clk_prep_enable(q);
810 if (ret)
811 return ret;
812
813 /* Init the LUT table again. */
814 fsl_qspi_init_lut(q);
815
816 /* Init for AHB read */
817 return fsl_qspi_init_ahb_read(q);
818 }
819
820 static const struct of_device_id fsl_qspi_dt_ids[] = {
821 { .compatible = "fsl,vf610-qspi", .data = &vybrid_data, },
822 { .compatible = "fsl,imx6sx-qspi", .data = &imx6sx_data, },
823 { .compatible = "fsl,imx7d-qspi", .data = &imx7d_data, },
824 { .compatible = "fsl,imx6ul-qspi", .data = &imx6ul_data, },
825 { .compatible = "fsl,ls1021a-qspi", .data = (void *)&ls1021a_data, },
826 { .compatible = "fsl,ls2080a-qspi", .data = &ls2080a_data, },
827 { /* sentinel */ }
828 };
829 MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
830
fsl_qspi_set_base_addr(struct fsl_qspi * q,struct spi_nor * nor)831 static void fsl_qspi_set_base_addr(struct fsl_qspi *q, struct spi_nor *nor)
832 {
833 q->chip_base_addr = q->nor_size * (nor - q->nor);
834 }
835
fsl_qspi_read_reg(struct spi_nor * nor,u8 opcode,u8 * buf,int len)836 static int fsl_qspi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
837 {
838 int ret;
839 struct fsl_qspi *q = nor->priv;
840
841 ret = fsl_qspi_runcmd(q, opcode, 0, len);
842 if (ret)
843 return ret;
844
845 fsl_qspi_read_data(q, len, buf);
846 return 0;
847 }
848
fsl_qspi_write_reg(struct spi_nor * nor,u8 opcode,u8 * buf,int len)849 static int fsl_qspi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
850 {
851 struct fsl_qspi *q = nor->priv;
852 int ret;
853
854 if (!buf) {
855 ret = fsl_qspi_runcmd(q, opcode, 0, 1);
856 if (ret)
857 return ret;
858
859 if (opcode == SPINOR_OP_CHIP_ERASE)
860 fsl_qspi_invalid(q);
861
862 } else if (len > 0) {
863 ret = fsl_qspi_nor_write(q, nor, opcode, 0,
864 (u32 *)buf, len);
865 if (ret > 0)
866 return 0;
867 } else {
868 dev_err(q->dev, "invalid cmd %d\n", opcode);
869 ret = -EINVAL;
870 }
871
872 return ret;
873 }
874
fsl_qspi_write(struct spi_nor * nor,loff_t to,size_t len,const u_char * buf)875 static ssize_t fsl_qspi_write(struct spi_nor *nor, loff_t to,
876 size_t len, const u_char *buf)
877 {
878 struct fsl_qspi *q = nor->priv;
879 ssize_t ret = fsl_qspi_nor_write(q, nor, nor->program_opcode, to,
880 (u32 *)buf, len);
881
882 /* invalid the data in the AHB buffer. */
883 fsl_qspi_invalid(q);
884 return ret;
885 }
886
fsl_qspi_read(struct spi_nor * nor,loff_t from,size_t len,u_char * buf)887 static ssize_t fsl_qspi_read(struct spi_nor *nor, loff_t from,
888 size_t len, u_char *buf)
889 {
890 struct fsl_qspi *q = nor->priv;
891 u8 cmd = nor->read_opcode;
892
893 /* if necessary,ioremap buffer before AHB read, */
894 if (!q->ahb_addr) {
895 q->memmap_offs = q->chip_base_addr + from;
896 q->memmap_len = len > QUADSPI_MIN_IOMAP ? len : QUADSPI_MIN_IOMAP;
897
898 q->ahb_addr = ioremap_nocache(
899 q->memmap_phy + q->memmap_offs,
900 q->memmap_len);
901 if (!q->ahb_addr) {
902 dev_err(q->dev, "ioremap failed\n");
903 return -ENOMEM;
904 }
905 /* ioremap if the data requested is out of range */
906 } else if (q->chip_base_addr + from < q->memmap_offs
907 || q->chip_base_addr + from + len >
908 q->memmap_offs + q->memmap_len) {
909 iounmap(q->ahb_addr);
910
911 q->memmap_offs = q->chip_base_addr + from;
912 q->memmap_len = len > QUADSPI_MIN_IOMAP ? len : QUADSPI_MIN_IOMAP;
913 q->ahb_addr = ioremap_nocache(
914 q->memmap_phy + q->memmap_offs,
915 q->memmap_len);
916 if (!q->ahb_addr) {
917 dev_err(q->dev, "ioremap failed\n");
918 return -ENOMEM;
919 }
920 }
921
922 dev_dbg(q->dev, "cmd [%x],read from %p, len:%zd\n",
923 cmd, q->ahb_addr + q->chip_base_addr + from - q->memmap_offs,
924 len);
925
926 /* Read out the data directly from the AHB buffer.*/
927 memcpy(buf, q->ahb_addr + q->chip_base_addr + from - q->memmap_offs,
928 len);
929
930 return len;
931 }
932
fsl_qspi_erase(struct spi_nor * nor,loff_t offs)933 static int fsl_qspi_erase(struct spi_nor *nor, loff_t offs)
934 {
935 struct fsl_qspi *q = nor->priv;
936 int ret;
937
938 dev_dbg(nor->dev, "%dKiB at 0x%08x:0x%08x\n",
939 nor->mtd.erasesize / 1024, q->chip_base_addr, (u32)offs);
940
941 ret = fsl_qspi_runcmd(q, nor->erase_opcode, offs, 0);
942 if (ret)
943 return ret;
944
945 fsl_qspi_invalid(q);
946 return 0;
947 }
948
fsl_qspi_prep(struct spi_nor * nor,enum spi_nor_ops ops)949 static int fsl_qspi_prep(struct spi_nor *nor, enum spi_nor_ops ops)
950 {
951 struct fsl_qspi *q = nor->priv;
952 int ret;
953
954 mutex_lock(&q->lock);
955
956 ret = fsl_qspi_clk_prep_enable(q);
957 if (ret)
958 goto err_mutex;
959
960 fsl_qspi_set_base_addr(q, nor);
961 return 0;
962
963 err_mutex:
964 mutex_unlock(&q->lock);
965 return ret;
966 }
967
fsl_qspi_unprep(struct spi_nor * nor,enum spi_nor_ops ops)968 static void fsl_qspi_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
969 {
970 struct fsl_qspi *q = nor->priv;
971
972 fsl_qspi_clk_disable_unprep(q);
973 mutex_unlock(&q->lock);
974 }
975
fsl_qspi_probe(struct platform_device * pdev)976 static int fsl_qspi_probe(struct platform_device *pdev)
977 {
978 const struct spi_nor_hwcaps hwcaps = {
979 .mask = SNOR_HWCAPS_READ_1_1_4 |
980 SNOR_HWCAPS_PP,
981 };
982 struct device_node *np = pdev->dev.of_node;
983 struct device *dev = &pdev->dev;
984 struct fsl_qspi *q;
985 struct resource *res;
986 struct spi_nor *nor;
987 struct mtd_info *mtd;
988 int ret, i = 0;
989
990 q = devm_kzalloc(dev, sizeof(*q), GFP_KERNEL);
991 if (!q)
992 return -ENOMEM;
993
994 q->nor_num = of_get_child_count(dev->of_node);
995 if (!q->nor_num || q->nor_num > FSL_QSPI_MAX_CHIP)
996 return -ENODEV;
997
998 q->dev = dev;
999 q->devtype_data = of_device_get_match_data(dev);
1000 if (!q->devtype_data)
1001 return -ENODEV;
1002 platform_set_drvdata(pdev, q);
1003
1004 /* find the resources */
1005 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "QuadSPI");
1006 q->iobase = devm_ioremap_resource(dev, res);
1007 if (IS_ERR(q->iobase))
1008 return PTR_ERR(q->iobase);
1009
1010 q->big_endian = of_property_read_bool(np, "big-endian");
1011 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1012 "QuadSPI-memory");
1013 if (!devm_request_mem_region(dev, res->start, resource_size(res),
1014 res->name)) {
1015 dev_err(dev, "can't request region for resource %pR\n", res);
1016 return -EBUSY;
1017 }
1018
1019 q->memmap_phy = res->start;
1020
1021 /* find the clocks */
1022 q->clk_en = devm_clk_get(dev, "qspi_en");
1023 if (IS_ERR(q->clk_en))
1024 return PTR_ERR(q->clk_en);
1025
1026 q->clk = devm_clk_get(dev, "qspi");
1027 if (IS_ERR(q->clk))
1028 return PTR_ERR(q->clk);
1029
1030 ret = fsl_qspi_clk_prep_enable(q);
1031 if (ret) {
1032 dev_err(dev, "can not enable the clock\n");
1033 goto clk_failed;
1034 }
1035
1036 /* find the irq */
1037 ret = platform_get_irq(pdev, 0);
1038 if (ret < 0) {
1039 dev_err(dev, "failed to get the irq: %d\n", ret);
1040 goto irq_failed;
1041 }
1042
1043 ret = devm_request_irq(dev, ret,
1044 fsl_qspi_irq_handler, 0, pdev->name, q);
1045 if (ret) {
1046 dev_err(dev, "failed to request irq: %d\n", ret);
1047 goto irq_failed;
1048 }
1049
1050 ret = fsl_qspi_nor_setup(q);
1051 if (ret)
1052 goto irq_failed;
1053
1054 if (of_get_property(np, "fsl,qspi-has-second-chip", NULL))
1055 q->has_second_chip = true;
1056
1057 mutex_init(&q->lock);
1058
1059 /* iterate the subnodes. */
1060 for_each_available_child_of_node(dev->of_node, np) {
1061 /* skip the holes */
1062 if (!q->has_second_chip)
1063 i *= 2;
1064
1065 nor = &q->nor[i];
1066 mtd = &nor->mtd;
1067
1068 nor->dev = dev;
1069 spi_nor_set_flash_node(nor, np);
1070 nor->priv = q;
1071
1072 if (q->nor_num > 1 && !mtd->name) {
1073 int spiflash_idx;
1074
1075 ret = of_property_read_u32(np, "reg", &spiflash_idx);
1076 if (!ret) {
1077 mtd->name = devm_kasprintf(dev, GFP_KERNEL,
1078 "%s-%d",
1079 dev_name(dev),
1080 spiflash_idx);
1081 if (!mtd->name) {
1082 ret = -ENOMEM;
1083 goto mutex_failed;
1084 }
1085 } else {
1086 dev_warn(dev, "reg property is missing\n");
1087 }
1088 }
1089
1090 /* fill the hooks */
1091 nor->read_reg = fsl_qspi_read_reg;
1092 nor->write_reg = fsl_qspi_write_reg;
1093 nor->read = fsl_qspi_read;
1094 nor->write = fsl_qspi_write;
1095 nor->erase = fsl_qspi_erase;
1096
1097 nor->prepare = fsl_qspi_prep;
1098 nor->unprepare = fsl_qspi_unprep;
1099
1100 ret = of_property_read_u32(np, "spi-max-frequency",
1101 &q->clk_rate);
1102 if (ret < 0)
1103 goto mutex_failed;
1104
1105 /* set the chip address for READID */
1106 fsl_qspi_set_base_addr(q, nor);
1107
1108 ret = spi_nor_scan(nor, NULL, &hwcaps);
1109 if (ret)
1110 goto mutex_failed;
1111
1112 ret = mtd_device_register(mtd, NULL, 0);
1113 if (ret)
1114 goto mutex_failed;
1115
1116 /* Set the correct NOR size now. */
1117 if (q->nor_size == 0) {
1118 q->nor_size = mtd->size;
1119
1120 /* Map the SPI NOR to accessiable address */
1121 fsl_qspi_set_map_addr(q);
1122 }
1123
1124 /*
1125 * The TX FIFO is 64 bytes in the Vybrid, but the Page Program
1126 * may writes 265 bytes per time. The write is working in the
1127 * unit of the TX FIFO, not in the unit of the SPI NOR's page
1128 * size.
1129 *
1130 * So shrink the spi_nor->page_size if it is larger then the
1131 * TX FIFO.
1132 */
1133 if (nor->page_size > q->devtype_data->txfifo)
1134 nor->page_size = q->devtype_data->txfifo;
1135
1136 i++;
1137 }
1138
1139 /* finish the rest init. */
1140 ret = fsl_qspi_nor_setup_last(q);
1141 if (ret)
1142 goto last_init_failed;
1143
1144 fsl_qspi_clk_disable_unprep(q);
1145 return 0;
1146
1147 last_init_failed:
1148 for (i = 0; i < q->nor_num; i++) {
1149 /* skip the holes */
1150 if (!q->has_second_chip)
1151 i *= 2;
1152 mtd_device_unregister(&q->nor[i].mtd);
1153 }
1154 mutex_failed:
1155 mutex_destroy(&q->lock);
1156 irq_failed:
1157 fsl_qspi_clk_disable_unprep(q);
1158 clk_failed:
1159 dev_err(dev, "Freescale QuadSPI probe failed\n");
1160 return ret;
1161 }
1162
fsl_qspi_remove(struct platform_device * pdev)1163 static int fsl_qspi_remove(struct platform_device *pdev)
1164 {
1165 struct fsl_qspi *q = platform_get_drvdata(pdev);
1166 int i;
1167
1168 for (i = 0; i < q->nor_num; i++) {
1169 /* skip the holes */
1170 if (!q->has_second_chip)
1171 i *= 2;
1172 mtd_device_unregister(&q->nor[i].mtd);
1173 }
1174
1175 /* disable the hardware */
1176 qspi_writel(q, QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR);
1177 qspi_writel(q, 0x0, q->iobase + QUADSPI_RSER);
1178
1179 mutex_destroy(&q->lock);
1180
1181 if (q->ahb_addr)
1182 iounmap(q->ahb_addr);
1183
1184 return 0;
1185 }
1186
fsl_qspi_suspend(struct platform_device * pdev,pm_message_t state)1187 static int fsl_qspi_suspend(struct platform_device *pdev, pm_message_t state)
1188 {
1189 return 0;
1190 }
1191
fsl_qspi_resume(struct platform_device * pdev)1192 static int fsl_qspi_resume(struct platform_device *pdev)
1193 {
1194 int ret;
1195 struct fsl_qspi *q = platform_get_drvdata(pdev);
1196
1197 ret = fsl_qspi_clk_prep_enable(q);
1198 if (ret)
1199 return ret;
1200
1201 fsl_qspi_nor_setup(q);
1202 fsl_qspi_set_map_addr(q);
1203 fsl_qspi_nor_setup_last(q);
1204
1205 fsl_qspi_clk_disable_unprep(q);
1206
1207 return 0;
1208 }
1209
1210 static struct platform_driver fsl_qspi_driver = {
1211 .driver = {
1212 .name = "fsl-quadspi",
1213 .of_match_table = fsl_qspi_dt_ids,
1214 },
1215 .probe = fsl_qspi_probe,
1216 .remove = fsl_qspi_remove,
1217 .suspend = fsl_qspi_suspend,
1218 .resume = fsl_qspi_resume,
1219 };
1220 module_platform_driver(fsl_qspi_driver);
1221
1222 MODULE_DESCRIPTION("Freescale QuadSPI Controller Driver");
1223 MODULE_AUTHOR("Freescale Semiconductor Inc.");
1224 MODULE_LICENSE("GPL v2");
1225