1 /** 2 **************************************************************************************** 3 * 4 * @file gr55xx_hal_cortex.h 5 * @author BLE Driver Team 6 * @brief Header file of CORTEX HAL module. 7 * 8 **************************************************************************************** 9 * @attention 10 #####Copyright (c) 2019 GOODIX 11 All rights reserved. 12 13 Redistribution and use in source and binary forms, with or without 14 modification, are permitted provided that the following conditions are met: 15 * Redistributions of source code must retain the above copyright 16 notice, this list of conditions and the following disclaimer. 17 * Redistributions in binary form must reproduce the above copyright 18 notice, this list of conditions and the following disclaimer in the 19 documentation and/or other materials provided with the distribution. 20 * Neither the name of GOODIX nor the names of its contributors may be used 21 to endorse or promote products derived from this software without 22 specific prior written permission. 23 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 POSSIBILITY OF SUCH DAMAGE. 35 **************************************************************************************** 36 */ 37 38 /** @addtogroup PERIPHERAL Peripheral Driver 39 * @{ 40 */ 41 42 /** @addtogroup HAL_DRIVER HAL Driver 43 * @{ 44 */ 45 46 /** @defgroup HAL_CORTEX CORTEX 47 * @brief CORTEX HAL module driver. 48 * @{ 49 */ 50 51 /* Define to prevent recursive inclusion -------------------------------------*/ 52 #ifndef __GR55xx_HAL_CORTEX_H__ 53 #define __GR55xx_HAL_CORTEX_H__ 54 55 /* Includes ------------------------------------------------------------------*/ 56 #include "gr55xx_hal_def.h" 57 58 #ifdef __cplusplus 59 extern "C" { 60 #endif 61 62 /* Exported types ------------------------------------------------------------*/ 63 64 /** @addtogroup HAL_CORTEX_STRUCTURES Structures 65 * @{ 66 */ 67 68 #if (__MPU_PRESENT == 1U) 69 70 /** @defgroup CORTEX_MPU_Region_Configuration MPU Region Configuration 71 * @{ 72 */ 73 74 /** 75 * @brief MPU Region initialization structure 76 */ 77 typedef struct _mpu_region_init_t { 78 uint8_t enable; /**< Specifies the status of the region. 79 This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ 80 81 uint8_t number; /**< Specifies the number of the region to protect. 82 This parameter can be a value of @ref CORTEX_MPU_Region_Number */ 83 84 uint32_t base_address; /**< Specifies the base address of the region to protect. */ 85 86 uint8_t size; /**< Specifies the size of the region to protect. 87 This parameter can be a value of @ref CORTEX_MPU_Region_Size */ 88 89 uint8_t subregion_disable; /**< Specifies the number of the subregion protection to disable. 90 This parameter must be a number between Min_Data = 0x00 and 91 Max_Data = 0xFF */ 92 93 uint8_t type_tex_field; /**< Specifies the TEX field level. 94 This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ 95 96 uint8_t access_permission; /**< Specifies the region access permission type. 97 This parameter can be a value of 98 @ref CORTEX_MPU_Region_Permission_Attributes */ 99 100 uint8_t disable_exec; /**< Specifies the instruction access status. 101 This parameter can be a value of 102 @ref CORTEX_MPU_Instruction_Access */ 103 104 uint8_t is_shareable; /**< Specifies the shareability status of the protected region. 105 This parameter can be a value of 106 @ref CORTEX_MPU_Access_Shareable */ 107 108 uint8_t is_cacheable; /**< Specifies the cacheable status of the region protected. 109 This parameter can be a value of 110 @ref CORTEX_MPU_Access_Cacheable */ 111 112 uint8_t is_bufferable; /**< Specifies the bufferable status of the protected region. 113 This parameter can be a value of 114 @ref CORTEX_MPU_Access_Bufferable */ 115 } mpu_region_init_t; 116 117 /** @} */ 118 119 #endif /* __MPU_PRESENT */ 120 121 /** @} */ 122 123 124 /** 125 * @defgroup HAL_CORTEX_MACRO Defines 126 * @{ 127 */ 128 129 /* Exported constants --------------------------------------------------------*/ 130 131 /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants 132 * @{ 133 */ 134 135 /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group 136 * @{ 137 */ 138 #define NVIC_PRIORITYGROUP_0 (0x00000007U) /**< 0 bit for pre-emption priority, 139 8 bits for subpriority */ 140 #define NVIC_PRIORITYGROUP_1 (0x00000006U) /**< 1 bit for pre-emption priority, 141 7 bits for subpriority */ 142 #define NVIC_PRIORITYGROUP_2 (0x00000005U) /**< 2 bits for pre-emption priority, 143 6 bits for subpriority */ 144 #define NVIC_PRIORITYGROUP_3 (0x00000004U) /**< 3 bits for pre-emption priority, 145 5 bits for subpriority */ 146 #define NVIC_PRIORITYGROUP_4 (0x00000003U) /**< 4 bits for pre-emption priority, 147 4 bits for subpriority */ 148 #define NVIC_PRIORITYGROUP_5 (0x00000002U) /**< 5 bits for pre-emption priority, 149 3 bits for subpriority */ 150 #define NVIC_PRIORITYGROUP_6 (0x00000001U) /**< 6 bits for pre-emption priority, 151 2 bits for subpriority */ 152 #define NVIC_PRIORITYGROUP_7 (0x00000000U) /**< 7 bits for pre-emption priority, 153 1 bit for subpriority */ 154 /** @} */ 155 156 /** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source 157 * @{ 158 */ 159 #define SYSTICK_CLKSOURCE_REFCLK (0x00000000U) /**< SYSTICK clock source External Reference Clock */ 160 #define SYSTICK_CLKSOURCE_HCLK (0x00000004U) /**< SYSTICK clock source HCLK */ 161 /** @} */ 162 163 #if (__MPU_PRESENT == 1U) 164 /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control 165 * @{ 166 */ 167 #define MPU_HFNMI_PRIVDEF_NONE (0x00000000U) /**< HFNMIENA disable, PRIVDEFENA disable */ 168 #define MPU_HARDFAULT_NMI (0x00000002U) /**< HFNMIENA enable, PRIVDEFENA disable */ 169 #define MPU_PRIVILEGED_DEFAULT (0x00000004U) /**< HFNMIENA disable, PRIVDEFENA enable */ 170 #define MPU_HFNMI_PRIVDEF (0x00000006U) /**< HFNMIENA enable, PRIVDEFENA enable */ 171 /** @} */ 172 173 /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable 174 * @{ 175 */ 176 #define MPU_REGION_ENABLE ((uint8_t)0x01U) /**< MPU Region Enable */ 177 #define MPU_REGION_DISABLE ((uint8_t)0x00U) /**< MPU Region Disable */ 178 /** @} */ 179 180 /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access 181 * @{ 182 */ 183 #define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00U) /**< MPU Instruction Access Enable */ 184 #define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01U) /**< MPU Instruction Access Disable */ 185 /** @} */ 186 187 /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable 188 * @{ 189 */ 190 #define MPU_ACCESS_SHAREABLE ((uint8_t)0x01U) /**< MPU Instruction Access Shareable */ 191 #define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00U) /**< MPU Instruction Access Not Shareable */ 192 /** @} */ 193 194 /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable 195 * @{ 196 */ 197 #define MPU_ACCESS_CACHEABLE ((uint8_t)0x01U) /**< MPU Instruction Access Cacheable */ 198 #define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00U) /**< MPU Instruction Access Not Cacheable */ 199 /** @} */ 200 201 /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable 202 * @{ 203 */ 204 #define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01U) /**< MPU Instruction Access Bufferable */ 205 #define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00U) /**< MPU Instruction Access Not Bufferable */ 206 /** @} */ 207 208 /** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels 209 * @{ 210 */ 211 #define MPU_TEX_LEVEL0 ((uint8_t)0x00U) /**< MPU TEX Level 0 */ 212 #define MPU_TEX_LEVEL1 ((uint8_t)0x01U) /**< MPU TEX Level 1 */ 213 #define MPU_TEX_LEVEL2 ((uint8_t)0x02U) /**< MPU TEX Level 2 */ 214 /** @} */ 215 216 /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size 217 * @{ 218 */ 219 #define MPU_REGION_SIZE_32B ((uint8_t)0x04U) /**< MPU Region Size 32B */ 220 #define MPU_REGION_SIZE_64B ((uint8_t)0x05U) /**< MPU Region Size 64B */ 221 #define MPU_REGION_SIZE_128B ((uint8_t)0x06U) /**< MPU Region Size 128B */ 222 #define MPU_REGION_SIZE_256B ((uint8_t)0x07U) /**< MPU Region Size 256B */ 223 #define MPU_REGION_SIZE_512B ((uint8_t)0x08U) /**< MPU Region Size 512B */ 224 #define MPU_REGION_SIZE_1KB ((uint8_t)0x09U) /**< MPU Region Size 1KB */ 225 #define MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) /**< MPU Region Size 2KB */ 226 #define MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) /**< MPU Region Size 4KB */ 227 #define MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) /**< MPU Region Size 8KB */ 228 #define MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) /**< MPU Region Size 16KB */ 229 #define MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) /**< MPU Region Size 32KB */ 230 #define MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) /**< MPU Region Size 64KB */ 231 #define MPU_REGION_SIZE_128KB ((uint8_t)0x10U) /**< MPU Region Size 128KB */ 232 #define MPU_REGION_SIZE_256KB ((uint8_t)0x11U) /**< MPU Region Size 256KB */ 233 #define MPU_REGION_SIZE_512KB ((uint8_t)0x12U) /**< MPU Region Size 512KB */ 234 #define MPU_REGION_SIZE_1MB ((uint8_t)0x13U) /**< MPU Region Size 1MB */ 235 #define MPU_REGION_SIZE_2MB ((uint8_t)0x14U) /**< MPU Region Size 2MB */ 236 #define MPU_REGION_SIZE_4MB ((uint8_t)0x15U) /**< MPU Region Size 4MB */ 237 #define MPU_REGION_SIZE_8MB ((uint8_t)0x16U) /**< MPU Region Size 8MB */ 238 #define MPU_REGION_SIZE_16MB ((uint8_t)0x17U) /**< MPU Region Size 16MB */ 239 #define MPU_REGION_SIZE_32MB ((uint8_t)0x18U) /**< MPU Region Size 32MB */ 240 #define MPU_REGION_SIZE_64MB ((uint8_t)0x19U) /**< MPU Region Size 64MB */ 241 #define MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) /**< MPU Region Size 128MB */ 242 #define MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) /**< MPU Region Size 256MB */ 243 #define MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) /**< MPU Region Size 512MB */ 244 #define MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) /**< MPU Region Size 1GB */ 245 #define MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) /**< MPU Region Size 2GB */ 246 #define MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) /**< MPU Region Size 4GB */ 247 /** @} */ 248 249 /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes 250 * @{ 251 */ 252 #define MPU_REGION_NO_ACCESS ((uint8_t)0x00U) /**< All accesses generate a permission fault */ 253 #define MPU_REGION_PRIV_RW ((uint8_t)0x01U) /**< Access from privileged software only */ 254 #define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02U) /**< Write by unprivileged software generate a permission fault */ 255 #define MPU_REGION_FULL_ACCESS ((uint8_t)0x03U) /**< Full access */ 256 #define MPU_REGION_PRIV_RO ((uint8_t)0x05U) /**< Reads by privileged software only */ 257 #define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06U) /**< Read only, by privileged or unprivileged software */ 258 /** @} */ 259 260 /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number 261 * @{ 262 */ 263 #define MPU_REGION_NUMBER0 ((uint8_t)0x00U) /**< MPU Region Number 0 */ 264 #define MPU_REGION_NUMBER1 ((uint8_t)0x01U) /**< MPU Region Number 1 */ 265 #define MPU_REGION_NUMBER2 ((uint8_t)0x02U) /**< MPU Region Number 2 */ 266 #define MPU_REGION_NUMBER3 ((uint8_t)0x03U) /**< MPU Region Number 3 */ 267 #define MPU_REGION_NUMBER4 ((uint8_t)0x04U) /**< MPU Region Number 4 */ 268 #define MPU_REGION_NUMBER5 ((uint8_t)0x05U) /**< MPU Region Number 5 */ 269 #define MPU_REGION_NUMBER6 ((uint8_t)0x06U) /**< MPU Region Number 6 */ 270 #define MPU_REGION_NUMBER7 ((uint8_t)0x07U) /**< MPU Region Number 7 */ 271 /** @} */ 272 #endif /* __MPU_PRESENT */ 273 274 /** @} */ 275 276 /* Exported Macros -----------------------------------------------------------*/ 277 /* Private types -------------------------------------------------------------*/ 278 /* Private variables ---------------------------------------------------------*/ 279 /* Private constants ---------------------------------------------------------*/ 280 281 /* Private macros ------------------------------------------------------------*/ 282 /** @defgroup CORTEX_Private_Macros CORTEX Private Macros 283 * @{ 284 */ 285 286 /** 287 * @brief Check if NVIC priority group is valid. 288 * @param __GROUP__ NVIC priority group. 289 * @retval SET (__GROUP__ is valid) or RESET (__GROUP__ is invalid) 290 */ 291 #define IS_NVIC_PRIORITY_GROUP(__GROUP__) (((__GROUP__) == NVIC_PRIORITYGROUP_0) || \ 292 ((__GROUP__) == NVIC_PRIORITYGROUP_1) || \ 293 ((__GROUP__) == NVIC_PRIORITYGROUP_2) || \ 294 ((__GROUP__) == NVIC_PRIORITYGROUP_3) || \ 295 ((__GROUP__) == NVIC_PRIORITYGROUP_4) || \ 296 ((__GROUP__) == NVIC_PRIORITYGROUP_5) || \ 297 ((__GROUP__) == NVIC_PRIORITYGROUP_6) || \ 298 ((__GROUP__) == NVIC_PRIORITYGROUP_7)) 299 300 /** 301 * @brief Check if NVIC priority group is valid. 302 * @param __PRIORITY__ NVIC priority group. 303 * @retval SET (__PRIORITY__ is valid) or RESET (__PRIORITY__ is invalid) 304 */ 305 #define IS_NVIC_PREEMPTION_PRIORITY(__PRIORITY__) ((__PRIORITY__) < 0x80U) 306 307 /** 308 * @brief Check if NVIC sub priority is valid. 309 * @param __PRIORITY__ NVIC sub priority. 310 * @retval SET (__PRIORITY__ is valid) or RESET (__PRIORITY__ is invalid) 311 */ 312 #define IS_NVIC_SUB_PRIORITY(__PRIORITY__) ((__PRIORITY__) <= 0xFFU) 313 314 /** 315 * @brief Check if NVIC deivce IRQ is valid. 316 * @param __IRQ__ NVIC device IRQ. 317 * @retval SET (__IRQ__ is valid) or RESET (__IRQ__ is invalid) 318 */ 319 #define IS_NVIC_DEVICE_IRQ(__IRQ__) ((__IRQ__) >= 0x00) 320 321 /** 322 * @brief Check if SYSTICK clock source is valid. 323 * @param __SOURCE__ SYSTICK clock source. 324 * @retval SET (__SOURCE__ is valid) or RESET (__SOURCE__ is invalid) 325 */ 326 #define IS_SYSTICK_CLK_SOURCE(__SOURCE__) (((__SOURCE__) == SYSTICK_CLKSOURCE_HCLK) || \ 327 ((__SOURCE__) == SYSTICK_CLKSOURCE_REFCLK)) 328 329 #if (__MPU_PRESENT == 1U) 330 331 /** 332 * @brief Check if MPU enable state is valid. 333 * @param __STATE__ Enable state. 334 * @retval SET (__STATE__ is valid) or RESET (__STATE__ is not invalid) 335 */ 336 #define IS_MPU_REGION_ENABLE(__STATE__) (((__STATE__) == MPU_REGION_ENABLE) || \ 337 ((__STATE__) == MPU_REGION_DISABLE)) 338 339 /** 340 * @brief Check if MPU instruction access state is valid. 341 * @param __STATE__ MPU instruction access state. 342 * @retval SET (__STATE__ is valid) or RESET (__STATE__ is not invalid) 343 */ 344 #define IS_MPU_INSTRUCTION_ACCESS(__STATE__) (((__STATE__) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ 345 ((__STATE__) == MPU_INSTRUCTION_ACCESS_DISABLE)) 346 347 /** 348 * @brief Check if MPU access shareable state is valid. 349 * @param __STATE__ MPU access shareable state. 350 * @retval SET (__STATE__ is valid) or RESET (__STATE__ is not invalid) 351 */ 352 #define IS_MPU_ACCESS_SHAREABLE(__STATE__) (((__STATE__) == MPU_ACCESS_SHAREABLE) || \ 353 ((__STATE__) == MPU_ACCESS_NOT_SHAREABLE)) 354 355 /** 356 * @brief Check if MPU access cacheable state is valid. 357 * @param __STATE__ MPU access cacheable state. 358 * @retval SET (__STATE__ is valid) or RESET (__STATE__ is not invalid) 359 */ 360 #define IS_MPU_ACCESS_CACHEABLE(__STATE__) (((__STATE__) == MPU_ACCESS_CACHEABLE) || \ 361 ((__STATE__) == MPU_ACCESS_NOT_CACHEABLE)) 362 363 /** 364 * @brief Check if MPU access bufferable state is valid. 365 * @param __STATE__ MPU access bufferable state. 366 * @retval SET (__STATE__ is valid) or RESET (__STATE__ is not invalid) 367 */ 368 #define IS_MPU_ACCESS_BUFFERABLE(__STATE__) (((__STATE__) == MPU_ACCESS_BUFFERABLE) || \ 369 ((__STATE__) == MPU_ACCESS_NOT_BUFFERABLE)) 370 371 /** 372 * @brief Check if MPU Tex level is valid. 373 * @param __TYPE__ MPU Tex level. 374 * @retval SET (__TYPE__ is valid) or RESET (__TYPE__ is invalid) 375 */ 376 #define IS_MPU_TEX_LEVEL(__TYPE__) (((__TYPE__) == MPU_TEX_LEVEL0) || \ 377 ((__TYPE__) == MPU_TEX_LEVEL1) || \ 378 ((__TYPE__) == MPU_TEX_LEVEL2)) 379 380 /** 381 * @brief Check if MPU region permission attribute type is valid. 382 * @param __TYPE__ MPU region permission attribute type. 383 * @retval SET (__TYPE__ is valid) or RESET (__TYPE__ is invalid) 384 */ 385 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(__TYPE__) (((__TYPE__) == MPU_REGION_NO_ACCESS) || \ 386 ((__TYPE__) == MPU_REGION_PRIV_RW) || \ 387 ((__TYPE__) == MPU_REGION_PRIV_RW_URO) || \ 388 ((__TYPE__) == MPU_REGION_FULL_ACCESS) || \ 389 ((__TYPE__) == MPU_REGION_PRIV_RO) || \ 390 ((__TYPE__) == MPU_REGION_PRIV_RO_URO)) 391 392 /** 393 * @brief Check if MPU region number is valid. 394 * @param __NUMBER__ MPU region number. 395 * @retval SET (__NUMBER__ is valid) or RESET (__NUMBER__ is invalid) 396 */ 397 #define IS_MPU_REGION_NUMBER(__NUMBER__) (((__NUMBER__) == MPU_REGION_NUMBER0) || \ 398 ((__NUMBER__) == MPU_REGION_NUMBER1) || \ 399 ((__NUMBER__) == MPU_REGION_NUMBER2) || \ 400 ((__NUMBER__) == MPU_REGION_NUMBER3) || \ 401 ((__NUMBER__) == MPU_REGION_NUMBER4) || \ 402 ((__NUMBER__) == MPU_REGION_NUMBER5) || \ 403 ((__NUMBER__) == MPU_REGION_NUMBER6) || \ 404 ((__NUMBER__) == MPU_REGION_NUMBER7)) 405 406 /** 407 * @brief Check if MPU region size is valid. 408 * @param __SIZE__ MPU region size. 409 * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid) 410 */ 411 #define IS_MPU_REGION_SIZE(__SIZE__) (((__SIZE__) == MPU_REGION_SIZE_32B) || \ 412 ((__SIZE__) == MPU_REGION_SIZE_64B) || \ 413 ((__SIZE__) == MPU_REGION_SIZE_128B) || \ 414 ((__SIZE__) == MPU_REGION_SIZE_256B) || \ 415 ((__SIZE__) == MPU_REGION_SIZE_512B) || \ 416 ((__SIZE__) == MPU_REGION_SIZE_1KB) || \ 417 ((__SIZE__) == MPU_REGION_SIZE_2KB) || \ 418 ((__SIZE__) == MPU_REGION_SIZE_4KB) || \ 419 ((__SIZE__) == MPU_REGION_SIZE_8KB) || \ 420 ((__SIZE__) == MPU_REGION_SIZE_16KB) || \ 421 ((__SIZE__) == MPU_REGION_SIZE_32KB) || \ 422 ((__SIZE__) == MPU_REGION_SIZE_64KB) || \ 423 ((__SIZE__) == MPU_REGION_SIZE_128KB) || \ 424 ((__SIZE__) == MPU_REGION_SIZE_256KB) || \ 425 ((__SIZE__) == MPU_REGION_SIZE_512KB) || \ 426 ((__SIZE__) == MPU_REGION_SIZE_1MB) || \ 427 ((__SIZE__) == MPU_REGION_SIZE_2MB) || \ 428 ((__SIZE__) == MPU_REGION_SIZE_4MB) || \ 429 ((__SIZE__) == MPU_REGION_SIZE_8MB) || \ 430 ((__SIZE__) == MPU_REGION_SIZE_16MB) || \ 431 ((__SIZE__) == MPU_REGION_SIZE_32MB) || \ 432 ((__SIZE__) == MPU_REGION_SIZE_64MB) || \ 433 ((__SIZE__) == MPU_REGION_SIZE_128MB) || \ 434 ((__SIZE__) == MPU_REGION_SIZE_256MB) || \ 435 ((__SIZE__) == MPU_REGION_SIZE_512MB) || \ 436 ((__SIZE__) == MPU_REGION_SIZE_1GB) || \ 437 ((__SIZE__) == MPU_REGION_SIZE_2GB) || \ 438 ((__SIZE__) == MPU_REGION_SIZE_4GB)) 439 440 441 /** 442 * @brief Check if MPU sub region is valid. 443 * @param __SUBREGION__ MPU sub region. 444 * @retval SET (__SUBREGION__ is valid) or RESET (__SUBREGION__ is invalid) 445 */ 446 #define IS_MPU_SUB_REGION_DISABLE(__SUBREGION__) ((__SUBREGION__) < (uint16_t)0x00FFU) 447 #endif /* __MPU_PRESENT */ 448 449 /** @} */ 450 451 /** @} */ 452 453 /* Exported functions --------------------------------------------------------*/ 454 /** @addtogroup HAL_CORTEX_DRIVER_FUNCTIONS Functions 455 * @{ 456 */ 457 458 /** @addtogroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions 459 * @brief Initialization and Configuration functions. 460 * 461 @verbatim 462 ============================================================================== 463 ##### Initialization and de-initialization functions ##### 464 ============================================================================== 465 [..] 466 This section provides the CORTEX HAL driver functions allowing to configure Interrupts 467 Systick functionalities 468 469 @endverbatim 470 * @{ 471 */ 472 473 /** 474 **************************************************************************************** 475 * @brief Set the priority grouping field (pre-emption priority and subpriority) 476 * using the required unlock sequence. 477 * 478 * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. 479 * The pending IRQ priority will be managed only by the subpriority. 480 * 481 * @param[in] priority_group: The priority grouping bits length. 482 * This parameter can be one of the following values: 483 * @arg @ref NVIC_PRIORITYGROUP_0 0 bit for pre-emption priority, 484 * 8 bits for subpriority 485 * @arg @ref NVIC_PRIORITYGROUP_1 1 bit for pre-emption priority, 486 * 7 bits for subpriority 487 * @arg @ref NVIC_PRIORITYGROUP_2 2 bits for pre-emption priority, 488 * 6 bits for subpriority 489 * @arg @ref NVIC_PRIORITYGROUP_3 3 bits for pre-emption priority, 490 * 5 bits for subpriority 491 * @arg @ref NVIC_PRIORITYGROUP_4 4 bits for pre-emption priority, 492 * 4 bits for subpriority 493 * @arg @ref NVIC_PRIORITYGROUP_5 5 bits for pre-emption priority, 494 * 3 bits for subpriority 495 * @arg @ref NVIC_PRIORITYGROUP_6 6 bits for pre-emption priority, 496 * 2 bits for subpriority 497 * @arg @ref NVIC_PRIORITYGROUP_7 7 bits for pre-emption priority, 498 * 1 bit for subpriority 499 **************************************************************************************** 500 */ 501 void hal_nvic_set_priority_grouping(uint32_t priority_group); 502 503 /** 504 **************************************************************************************** 505 * @brief Set the priority of an interrupt. 506 * 507 * @param[in] IRQn: External interrupt number. 508 * This parameter can be an enumerator of IRQn_Type enumeration 509 * (For the complete GR55xx Devices IRQ Channels list, please refer to the 510 * appropriate CMSIS device file (gr55xxxx.h)) 511 * @param[in] preempt_priority: The pre-emption priority for the IRQn channel. 512 * This parameter can be a value between 0 and 127 as described in the table CORTEX_NVIC_Priority_Table. 513 * A lower priority value indicates a higher priority 514 * @param[in] sub_priority: The subpriority level for the IRQ channel. 515 * This parameter can be a value between 0 and 255 as described in the table CORTEX_NVIC_Priority_Table. 516 * A lower priority value indicates a higher priority. 517 **************************************************************************************** 518 */ 519 void hal_nvic_set_priority(IRQn_Type IRQn, uint32_t preempt_priority, uint32_t sub_priority); 520 521 /** 522 **************************************************************************************** 523 * @brief Enable a device specific interrupt in the NVIC interrupt controller. 524 * 525 * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() 526 * function should be called before. 527 * 528 * @param[in] IRQn: External interrupt number. 529 * This parameter can be an enumerator of IRQn_Type enumeration 530 * (For the complete GR55xx Devices IRQ Channels list, please refer to the 531 * appropriate CMSIS device file (gr55xxxx.h)) 532 **************************************************************************************** 533 */ 534 void hal_nvic_enable_irq(IRQn_Type IRQn); 535 536 /** 537 **************************************************************************************** 538 * @brief Disable a device specific interrupt in the NVIC interrupt controller. 539 * 540 * @param[in] IRQn: External interrupt number. 541 * This parameter can be an enumerator of IRQn_Type enumeration 542 * (For the complete GR55xx Devices IRQ Channels list, please refer to the 543 * appropriate CMSIS device file (gr55xxxx.h)) 544 **************************************************************************************** 545 */ 546 void hal_nvic_disable_irq(IRQn_Type IRQn); 547 548 /** 549 **************************************************************************************** 550 * @brief Initiate a system reset request to reset the MCU. 551 **************************************************************************************** 552 */ 553 void hal_nvic_system_reset(void); 554 555 556 /** 557 **************************************************************************************** 558 * @brief Initialize the System Timer and its interrupt, and start the System Tick Timer. 559 * Counter is in free running mode to generate periodic interrupts. 560 * 561 * @param[in] ticks_number: Specifies the number of ticks between two interrupts. 562 * 563 * @retval status 564 * - 0 Function succeeded. 565 * - 1 Function failed. 566 **************************************************************************************** 567 */ 568 uint32_t hal_systick_config(uint32_t ticks_number); 569 570 /** @} */ 571 572 /** @addtogroup CORTEX_Exported_Functions_Group2 Peripheral Control functions 573 * @brief Cortex control functions. 574 * 575 @verbatim 576 ============================================================================== 577 ##### Peripheral Control functions ##### 578 ============================================================================== 579 [..] 580 This subsection provides a set of functions allowing to control the CORTEX 581 (NVIC, SYSTICK, MPU) functionalities. 582 583 584 @endverbatim 585 * @{ 586 */ 587 588 #if (__MPU_PRESENT == 1U) 589 /** 590 **************************************************************************************** 591 * @brief Initialize and configures the Region and the memory to be protected. 592 * 593 * @param[in] p_mpu_init: Pointer to a mpu_region_init_t structure that contains 594 * the initialization and configuration information. 595 **************************************************************************************** 596 */ 597 void hal_mpu_config_region(mpu_region_init_t *p_mpu_init); 598 #endif /* __MPU_PRESENT */ 599 600 /** 601 **************************************************************************************** 602 * @brief Get the priority grouping field from the NVIC Interrupt Controller. 603 * 604 * @return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field) 605 **************************************************************************************** 606 */ 607 uint32_t hal_nvic_get_priority_grouping(void); 608 609 /** 610 **************************************************************************************** 611 * @brief Get the priority of an interrupt. 612 * 613 * @param[in] IRQn: External interrupt number. 614 * This parameter can be an enumerator of IRQn_Type enumeration. 615 * (For the complete GR55xx Devices IRQ Channels list, please refer to the 616 * appropriate CMSIS device file (gr55xxxx.h)) 617 * @param[in] priority_group: The priority grouping bits length. 618 * This parameter can be one of the following values: 619 * @arg @ref NVIC_PRIORITYGROUP_0 0 bit for pre-emption priority, 620 * 8 bits for subpriority 621 * @arg @ref NVIC_PRIORITYGROUP_1 1 bit for pre-emption priority, 622 * 7 bits for subpriority 623 * @arg @ref NVIC_PRIORITYGROUP_2 2 bits for pre-emption priority, 624 * 6 bits for subpriority 625 * @arg @ref NVIC_PRIORITYGROUP_3 3 bits for pre-emption priority, 626 * 5 bits for subpriority 627 * @arg @ref NVIC_PRIORITYGROUP_4 4 bits for pre-emption priority, 628 * 4 bits for subpriority 629 * @arg @ref NVIC_PRIORITYGROUP_5 5 bits for pre-emption priority, 630 * 3 bits for subpriority 631 * @arg @ref NVIC_PRIORITYGROUP_6 6 bits for pre-emption priority, 632 * 2 bits for subpriority 633 * @arg @ref NVIC_PRIORITYGROUP_7 7 bits for pre-emption priority, 634 * 1 bit for subpriority 635 * @param[in] p_preempt_priority: Pointer on the Preemptive priority value (starting from 0). 636 * @param[in] p_sub_priority: Pointer on the Subpriority value (starting from 0). 637 **************************************************************************************** 638 */ 639 void hal_nvic_get_priority(IRQn_Type IRQn, uint32_t priority_group, uint32_t *p_preempt_priority, 640 uint32_t *p_sub_priority); 641 642 /** 643 **************************************************************************************** 644 * @brief Set Pending bit of an external interrupt. 645 * 646 * @param[in] IRQn: External interrupt number. 647 * This parameter can be an enumerator of IRQn_Type enumeration 648 * (For the complete GR55xx Devices IRQ Channels list, please refer to the 649 * appropriate CMSIS device file (gr55xxxx.h)) 650 **************************************************************************************** 651 */ 652 void hal_nvic_set_pending_irq(IRQn_Type IRQn); 653 654 /** 655 **************************************************************************************** 656 * @brief Get Pending Interrupt (reads the pending register in the NVIC 657 * and returns the pending bit for the specified interrupt). 658 * 659 * @param[in] IRQn: External interrupt number. 660 * This parameter can be an enumerator of IRQn_Type enumeration 661 * (For the complete GR55xx Devices IRQ Channels list, please refer to the 662 * appropriate CMSIS device file (gr55xxxx.h)) 663 * 664 * @return status 665 * - 0 Interrupt status is not pending. 666 * - 1 Interrupt status is pending. 667 **************************************************************************************** 668 */ 669 uint32_t hal_nvic_get_pending_irq(IRQn_Type IRQn); 670 671 /** 672 **************************************************************************************** 673 * @brief Clear the pending bit of an external interrupt. 674 * 675 * @param[in] IRQn: External interrupt number. 676 * This parameter can be an enumerator of IRQn_Type enumeration 677 * (For the complete GR55xx Devices IRQ Channels list, please refer to the 678 * appropriate CMSIS device file (gr55xxxx.h)) 679 **************************************************************************************** 680 */ 681 void hal_nvic_clear_pending_irq(IRQn_Type IRQn); 682 683 /** 684 **************************************************************************************** 685 * @brief Get active interrupt (reads the active register in NVIC and returns the active bit). 686 * 687 * @param[in] IRQn: External interrupt number. 688 * This parameter can be an enumerator of IRQn_Type enumeration 689 * (For the complete GR55xx Devices IRQ Channels list, please refer to the 690 * appropriate CMSIS device file (gr55xxxx.h)) 691 * 692 * @return status 693 * - 0 Interrupt status is not pending. 694 * - 1 Interrupt status is pending. 695 **************************************************************************************** 696 */ 697 uint32_t hal_nvic_get_active(IRQn_Type IRQn); 698 699 /** 700 **************************************************************************************** 701 * @brief Configure the SysTick clock source. 702 * 703 * @param[in] clk_source: specifies the SysTick clock source. 704 * This parameter can be one of the following values: 705 * @arg @ref SYSTICK_CLKSOURCE_REFCLK External Reference Clock as SysTick clock source. 706 * @arg @ref SYSTICK_CLKSOURCE_HCLK AHB clock selected as SysTick clock source. 707 **************************************************************************************** 708 */ 709 void hal_systick_clk_source_config(uint32_t clk_source); 710 711 /** @} */ 712 713 /** @addtogroup CORTEX_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks 714 * @brief IRQ Handler and Callbacks functions. 715 * @{ 716 */ 717 718 /** 719 **************************************************************************************** 720 * @brief This function handles SYSTICK interrupt request. 721 **************************************************************************************** 722 */ 723 void hal_systick_irq_handler(void); 724 725 /** 726 **************************************************************************************** 727 * @brief SYSTICK callback. 728 * 729 * @note This function should not be modified. When the callback is needed, 730 * the hal_systick_callback can be implemented in the user file. 731 **************************************************************************************** 732 */ 733 void hal_systick_callback(void); 734 735 /** @} */ 736 737 /* Private functions ---------------------------------------------------------*/ 738 /** @defgroup CORTEX_Private_Functions CORTEX Private Functions 739 * @brief CORTEX private functions 740 * @{ 741 */ 742 743 #if (__MPU_PRESENT == 1U) 744 745 /** 746 **************************************************************************************** 747 * @brief Disables the MPU and clears the HFNMIENA bit (ARM recommendation) 748 **************************************************************************************** 749 */ 750 void hal_mpu_disable(void); 751 752 /** 753 **************************************************************************************** 754 * @brief Enable the MPU 755 * 756 * @param[in] mpu_control: Specifies the control mode of the MPU during hard fault, 757 * NMI, FAULTMASK and privileged access to the default memory. 758 * This parameter can be one of the following values: 759 * @arg @ref MPU_HFNMI_PRIVDEF_NONE 760 * @arg @ref MPU_HARDFAULT_NMI 761 * @arg @ref MPU_PRIVILEGED_DEFAULT 762 * @arg @ref MPU_HFNMI_PRIVDEF 763 **************************************************************************************** 764 */ 765 void hal_mpu_enable(uint32_t mpu_control); 766 767 #endif /* __MPU_PRESENT */ 768 769 /** @} */ 770 771 /** @} */ 772 773 #ifdef __cplusplus 774 } 775 #endif 776 777 #endif /* __GR55xx_HAL_CORTEX_H__ */ 778 779 /** @} */ 780 781 /** @} */ 782 783 /** @} */ 784