1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_aon_gpio.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of AON GPIO LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_AON_GPIO AON_GPIO
47 * @brief AON_GPIO LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55XX_LL_AON_GPIO_H__
53 #define __GR55XX_LL_AON_GPIO_H__
54
55 /* Includes ------------------------------------------------------------------*/
56 #include "gr55xx.h"
57
58 #ifdef __cplusplus
59 extern "C" {
60 #endif
61
62 #if defined(AON)
63
64 /** @defgroup AON_GPIO_LL_STRUCTURES Structures
65 * @{
66 */
67
68 /* Exported types ------------------------------------------------------------*/
69 /** @defgroup AON_GPIO_LL_ES_INIT AON_GPIO Exported init structures
70 * @{
71 */
72
73 /**
74 * @brief LL AON_GPIO init Structure definition
75 */
76 typedef struct _ll_aon_gpio_init {
77 uint32_t pin; /**< Specifies the AON_GPIO pins to be AON_GPIO_InitStructured.
78 This parameter can be any value of @ref AON_GPIO_LL_EC_PIN */
79
80 uint32_t mode; /**< Specifies the operating mode for the selected pins.
81 This parameter can be a value of @ref AON_GPIO_LL_EC_MODE.
82 AON_GPIO HW
83 AON_GPIO_InitStructuration can be
84 modified afterwards using unitary
85 function
86 @ref ll_aon_gpio_set_pin_mode(). */
87
88 uint32_t pull; /**< Specifies the operating Pull-up/Pull down for the selected pins.
89 This parameter can be a value of @ref AON_GPIO_LL_EC_PULL.
90 AON_GPIO HW configuration can be
91 modified afterwards using unitary
92 function
93 @ref ll_aon_gpio_set_pin_pull(). */
94
95 uint32_t mux; /*!< Specifies the Peripheral to be connected to the selected pins.
96 This parameter can be a value of @ref AON_GPIO_LL_EC_MUX.
97 GPIO HW AON_GPIO_InitStructuration
98 can be modified afterwards using
99 unitary function
100 @ref ll_aon_gpio_set_mux_pin_0_7(). */
101
102 uint32_t trigger; /**< Specifies the trigger signal active edge.
103 This parameter can be a value of @ref AON_GPIO_LL_EC_TRIGGER. */
104 } ll_aon_gpio_init_t;
105
106 /** @} */
107
108 /** @} */
109
110 /**
111 * @defgroup AON_GPIO_LL_MACRO Defines
112 * @{
113 */
114
115 /* Exported constants --------------------------------------------------------*/
116 /** @defgroup AON_GPIO_LL_Exported_Constants AON_GPIO Exported Constants
117 * @{
118 */
119
120 /** @defgroup AON_GPIO_LL_EC_PIN PIN
121 * @{
122 */
123 #define LL_AON_GPIO_PIN_0 ((uint32_t)0x01U) /**< Select pin 0 */
124 #define LL_AON_GPIO_PIN_1 ((uint32_t)0x02U) /**< Select pin 1 */
125 #define LL_AON_GPIO_PIN_2 ((uint32_t)0x04U) /**< Select pin 2 */
126 #define LL_AON_GPIO_PIN_3 ((uint32_t)0x08U) /**< Select pin 3 */
127 #define LL_AON_GPIO_PIN_4 ((uint32_t)0x10U) /**< Select pin 4 */
128 #define LL_AON_GPIO_PIN_5 ((uint32_t)0x20U) /**< Select pin 5 */
129 #define LL_AON_GPIO_PIN_6 ((uint32_t)0x40U) /**< Select pin 6 */
130 #define LL_AON_GPIO_PIN_7 ((uint32_t)0x80U) /**< Select pin 7 */
131 #define LL_AON_GPIO_PIN_ALL ((uint32_t)0xFFU) /**< Select all pins */
132 /** @} */
133
134 /** @defgroup AON_GPIO_LL_EC_MODE Mode
135 * @{
136 */
137 #define LL_AON_GPIO_MODE_INPUT ((uint32_t)0x0U) /**< Select input mode */
138 #define LL_AON_GPIO_MODE_OUTPUT ((uint32_t)0x1U) /**< Select output mode */
139 #define LL_AON_GPIO_MODE_MUX ((uint32_t)0x2U) /**< Select mux peripheral mode */
140 /** @} */
141
142 /** @defgroup AON_GPIO_LL_EC_PULL Pull Up Pull Down
143 * @{
144 */
145 #define LL_AON_GPIO_PULL_NO LL_AON_GPIO_RE_N /**< Select I/O no pull */
146 #define LL_AON_GPIO_PULL_UP LL_AON_GPIO_RTYP /**< Select I/O pull up */
147 #define LL_AON_GPIO_PULL_DOWN ((uint32_t)0x0U) /**< Select I/O pull down */
148 /** @} */
149
150 /** @defgroup AON_GPIO_LL_EC_MUX Alternate Function
151 * @{
152 */
153 #define LL_AON_GPIO_MUX_0 ((uint32_t)0x0U) /*!< Select alternate function 0 */
154 #define LL_AON_GPIO_MUX_1 ((uint32_t)0x1U) /*!< Select alternate function 1 */
155 #define LL_AON_GPIO_MUX_2 ((uint32_t)0x2U) /*!< Select alternate function 2 */
156 #define LL_AON_GPIO_MUX_3 ((uint32_t)0x3U) /*!< Select alternate function 3 */
157 #define LL_AON_GPIO_MUX_4 ((uint32_t)0x4U) /*!< Select alternate function 4 */
158 #define LL_AON_GPIO_MUX_5 ((uint32_t)0x5U) /*!< Select alternate function 5 */
159 #define LL_AON_GPIO_MUX_6 ((uint32_t)0x6U) /*!< Select alternate function 6 */
160 #define LL_AON_GPIO_MUX_7 ((uint32_t)0x7U) /*!< Select alternate function 7 */
161 #define LL_AON_GPIO_MUX_8 ((uint32_t)0x8U) /*!< Select alternate function 8 */
162 /** @} */
163
164
165 /** @defgroup AON_GPIO_LL_EC_TRIGGER Interrupt Trigger
166 * @{
167 */
168 #define LL_AON_GPIO_TRIGGER_NONE ((uint32_t)0x00U) /**< No Trigger Mode */
169 #define LL_AON_GPIO_TRIGGER_RISING ((uint32_t)0x01U) /**< Trigger Rising Mode */
170 #define LL_AON_GPIO_TRIGGER_FALLING ((uint32_t)0x02U) /**< Trigger Falling Mode */
171 #define LL_AON_GPIO_TRIGGER_HIGH ((uint32_t)0x03U) /**< Trigger High Mode */
172 #define LL_AON_GPIO_TRIGGER_LOW ((uint32_t)0x04U) /**< Trigger Low Mode */
173 /** @} */
174
175 /** @} */
176
177 /* Exported macro ------------------------------------------------------------*/
178 /** @defgroup AON_GPIO_LL_Exported_Macros AON_GPIO Exported Macros
179 * @{
180 */
181
182 /** @defgroup AON_GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
183 * @{
184 */
185
186 /**
187 * @brief Write a value in AON_GPIO register
188 * @param __instance__ AON_GPIO instance
189 * @param __REG__ Register to be written
190 * @param __VALUE__ Value to be written in the register
191 * @retval None
192 */
193 #define LL_AON_GPIO_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
194
195 /**
196 * @brief Read a value in AON_GPIO register
197 * @param __instance__ AON_GPIO instance
198 * @param __REG__ Register to be read
199 * @retval Register value
200 */
201 #define LL_AON_GPIO_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
202
203 /** @} */
204
205 /** @} */
206
207 /* Private types -------------------------------------------------------------*/
208 /* Private variables ---------------------------------------------------------*/
209 /* Private constants ---------------------------------------------------------*/
210 /* Private macros ------------------------------------------------------------*/
211 /** @defgroup AON_GPIO_LL_Private_Macros AON_GPIO Private Macros
212 * @{
213 */
214
215 /** @defgroup AON_GPIO_LL_PM_RESISTOR Resistor Enable
216 * @{
217 */
218 #define LL_AON_GPIO_RE_N_Pos AON_PAD_CTL0_GPO_RE_N_Pos /**< Resistor Enable bits position */
219 #define LL_AON_GPIO_RE_N_Msk (0x1U << LL_AON_GPIO_RE_N_Pos) /**< Resistor Enable bits mask */
220 #define LL_AON_GPIO_RE_N LL_AON_GPIO_RE_N_Msk /**< Resistor Enable bits */
221 /** @} */
222
223 /** @defgroup AON_GPIO_LL_PM_RESISTOR_TYPE Resistor Type
224 * @{
225 */
226 #define LL_AON_GPIO_RTYP_Pos AON_PAD_CTL0_GPO_RTYPE_Pos /**< Resistor Type bits position */
227 #define LL_AON_GPIO_RTYP_Msk (0x1U << LL_AON_GPIO_RTYP_Pos) /**< Resistor Type bits mask */
228 #define LL_AON_GPIO_RTYP LL_AON_GPIO_RTYP_Msk /**< Resistor Type bits */
229 /** @} */
230
231 /** @defgroup AON_GPIO_LL_EC_DEFAULT_CONFIG InitStruct default configuartion
232 * @{
233 */
234
235 /**
236 * @brief LL AON_GPIO InitStrcut default configuartion
237 */
238 #define LL_AON_GPIO_DEFAULT_CONFIG \
239 { \
240 .pin = LL_AON_GPIO_PIN_ALL, \
241 .mode = LL_AON_GPIO_MODE_INPUT, \
242 .pull = LL_AON_GPIO_PULL_DOWN, \
243 .mux = LL_AON_GPIO_MUX_7, \
244 .trigger = LL_AON_GPIO_TRIGGER_NONE, \
245 }
246 /** @} */
247
248 /** @} */
249
250 /** @} */
251
252 /* Exported functions --------------------------------------------------------*/
253 /** @defgroup AON_GPIO_LL_DRIVER_FUNCTIONS Functions
254 * @{
255 */
256
257 /** @defgroup AON_GPIO_LL_EF_Port_Configuration Port Configuration
258 * @{
259 */
260
261 /**
262 * @brief Set several AON_GPIO pins to input/output mode.
263 *
264 * Register|BitsName
265 * --------|--------
266 * AON_PAD_CTL1 | AON_GPO_OE_N
267 *
268 * @param pin_mask This parameter can be a combination of the following values:
269 * @arg @ref LL_AON_GPIO_PIN_0
270 * @arg @ref LL_AON_GPIO_PIN_1
271 * @arg @ref LL_AON_GPIO_PIN_2
272 * @arg @ref LL_AON_GPIO_PIN_3
273 * @arg @ref LL_AON_GPIO_PIN_4
274 * @arg @ref LL_AON_GPIO_PIN_5
275 * @arg @ref LL_AON_GPIO_PIN_6
276 * @arg @ref LL_AON_GPIO_PIN_7
277 * @arg @ref LL_AON_GPIO_PIN_ALL
278 * @param mode This parameter can be one of the following values:
279 * @arg @ref LL_AON_GPIO_MODE_INPUT
280 * @arg @ref LL_AON_GPIO_MODE_OUTPUT
281 * @retval None
282 */
ll_aon_gpio_set_pin_mode(uint32_t pin_mask,uint32_t mode)283 __STATIC_INLINE void ll_aon_gpio_set_pin_mode(uint32_t pin_mask, uint32_t mode)
284 {
285 pin_mask = (pin_mask << AON_PAD_CTL1_AON_GPO_OE_N_Pos) & AON_PAD_CTL1_AON_GPO_OE_N;
286 GLOBAL_EXCEPTION_DISABLE();
287 MODIFY_REG(AON->AON_PAD_CTL1, pin_mask, (mode == LL_AON_GPIO_MODE_INPUT) ? pin_mask : 0);
288 GLOBAL_EXCEPTION_ENABLE();
289 }
290
291 /**
292 * @brief Return gpio mode for a AON_GPIO pin.
293 * @note I/O mode can be Input mode. General purpose output.
294 * @note Warning: only one pin can be passed as parameter.
295 *
296 * Register|BitsName
297 * --------|--------
298 * AON_PAD_CTL1 | AON_GPO_OE_N
299 *
300 * @param pin This parameter can be one of the following values:
301 * @arg @ref LL_AON_GPIO_PIN_0
302 * @arg @ref LL_AON_GPIO_PIN_1
303 * @arg @ref LL_AON_GPIO_PIN_2
304 * @arg @ref LL_AON_GPIO_PIN_3
305 * @arg @ref LL_AON_GPIO_PIN_4
306 * @arg @ref LL_AON_GPIO_PIN_5
307 * @arg @ref LL_AON_GPIO_PIN_6
308 * @arg @ref LL_AON_GPIO_PIN_7
309 * @retval Returned value can be one of the following values:
310 * @arg @ref LL_AON_GPIO_MODE_INPUT
311 * @arg @ref LL_AON_GPIO_MODE_OUTPUT
312 */
ll_aon_gpio_get_pin_mode(uint32_t pin)313 __STATIC_INLINE uint32_t ll_aon_gpio_get_pin_mode(uint32_t pin)
314 {
315 pin = (pin << AON_PAD_CTL1_AON_GPO_OE_N_Pos) & AON_PAD_CTL1_AON_GPO_OE_N;
316 return ((uint32_t)(READ_BITS(AON->AON_PAD_CTL1, pin) == LL_AON_GPIO_MODE_INPUT) ?
317 LL_AON_GPIO_MODE_OUTPUT : LL_AON_GPIO_MODE_INPUT);
318 }
319
320 /**
321 * @brief Configure gpio pull-up or pull-down for a dedicated AON_GPIO pin.
322 * @note Warning: only one pin can be passed as parameter.
323 *
324 * Register|BitsName
325 * --------|--------
326 * AON_PAD_CTL0 | GPO_RE_N
327 * AON_PAD_CTL0 | GPO_RTYPE
328 *
329 * @param pin_mask This parameter can be a combination of the following values:
330 * @arg @ref LL_AON_GPIO_PIN_0
331 * @arg @ref LL_AON_GPIO_PIN_1
332 * @arg @ref LL_AON_GPIO_PIN_2
333 * @arg @ref LL_AON_GPIO_PIN_3
334 * @arg @ref LL_AON_GPIO_PIN_4
335 * @arg @ref LL_AON_GPIO_PIN_5
336 * @arg @ref LL_AON_GPIO_PIN_6
337 * @arg @ref LL_AON_GPIO_PIN_7
338 * @arg @ref LL_AON_GPIO_PIN_ALL
339 * @param pull This parameter can be one of the following values:
340 * @arg @ref LL_AON_GPIO_PULL_NO
341 * @arg @ref LL_AON_GPIO_PULL_UP
342 * @arg @ref LL_AON_GPIO_PULL_DOWN
343 * @retval None
344 */
ll_aon_gpio_set_pin_pull(uint32_t pin_mask,uint32_t pull)345 __STATIC_INLINE void ll_aon_gpio_set_pin_pull(uint32_t pin_mask, uint32_t pull)
346 {
347 uint32_t RTypeMask = (pin_mask << AON_PAD_CTL0_GPO_RTYPE_Pos) & AON_PAD_CTL0_GPO_RTYPE;
348 uint32_t REnMask = (pin_mask << AON_PAD_CTL0_GPO_RE_N_Pos) & AON_PAD_CTL0_GPO_RE_N;
349 uint32_t RType = (pull == LL_AON_GPIO_PULL_UP) ? RTypeMask : 0x0000U;
350 uint32_t REn = (pull == LL_AON_GPIO_PULL_NO) ? REnMask : 0x0000U;
351 MODIFY_REG(AON->AON_PAD_CTL0, REnMask | RTypeMask, REn | RType);
352 }
353
354 /**
355 * @brief Return gpio pull-up or pull-down for a dedicated AON_GPIO pin.
356 * @note Warning: only one pin can be passed as parameter.
357 *
358 * Register|BitsName
359 * --------|--------
360 * AON_PAD_CTL0 | GPO_RE_N
361 * AON_PAD_CTL0 | GPO_RTYPE
362 *
363 * @param pin This parameter can be one of the following values:
364 * @arg @ref LL_AON_GPIO_PIN_0
365 * @arg @ref LL_AON_GPIO_PIN_1
366 * @arg @ref LL_AON_GPIO_PIN_2
367 * @arg @ref LL_AON_GPIO_PIN_3
368 * @arg @ref LL_AON_GPIO_PIN_4
369 * @arg @ref LL_AON_GPIO_PIN_5
370 * @arg @ref LL_AON_GPIO_PIN_6
371 * @arg @ref LL_AON_GPIO_PIN_7
372 * @retval Returned value can be one of the following values:
373 * @arg @ref LL_AON_GPIO_PULL_NO
374 * @arg @ref LL_AON_GPIO_PULL_UP
375 * @arg @ref LL_AON_GPIO_PULL_DOWN
376 */
ll_aon_gpio_get_pin_pull(uint32_t pin)377 __STATIC_INLINE uint32_t ll_aon_gpio_get_pin_pull(uint32_t pin)
378 {
379 uint32_t RTypeMask = (pin << AON_PAD_CTL0_GPO_RTYPE_Pos) & AON_PAD_CTL0_GPO_RTYPE;
380 uint32_t REnMask = (pin << AON_PAD_CTL0_GPO_RE_N_Pos) & AON_PAD_CTL0_GPO_RE_N;
381 return ((READ_BITS(AON->AON_PAD_CTL0, REnMask) != RESET) ? LL_AON_GPIO_PULL_NO :
382 ((READ_BITS(AON->AON_PAD_CTL0, RTypeMask) != RESET) ? LL_AON_GPIO_PULL_UP : LL_AON_GPIO_PULL_DOWN));
383 }
384
385 /**
386 * @brief Configure gpio pinmux number of a dedicated pin from 0 to 7 for a dedicated port.
387 * @note Possible values are from AF0 to AF15 depending on target.
388 * @note Warning: only one pin can be passed as parameter.
389 *
390 * Register|BitsName
391 * --------|--------
392 * AON_PAD_MUX_CTRL | CTRL0_7
393 * AON_PAD_CTL_0 | MCU_OVR
394 *
395 * @param pin This parameter can be one of the following values:
396 * @arg @ref LL_AON_GPIO_PIN_0
397 * @arg @ref LL_AON_GPIO_PIN_1
398 * @arg @ref LL_AON_GPIO_PIN_2
399 * @arg @ref LL_AON_GPIO_PIN_3
400 * @arg @ref LL_AON_GPIO_PIN_4
401 * @arg @ref LL_AON_GPIO_PIN_5
402 * @arg @ref LL_AON_GPIO_PIN_6
403 * @arg @ref LL_AON_GPIO_PIN_7
404 * @param mux This parameter can be one of the following values:
405 * @arg @ref LL_AON_GPIO_MUX_0
406 * @arg @ref LL_AON_GPIO_MUX_1
407 * @arg @ref LL_AON_GPIO_MUX_2
408 * @arg @ref LL_AON_GPIO_MUX_3
409 * @arg @ref LL_AON_GPIO_MUX_4
410 * @arg @ref LL_AON_GPIO_MUX_5
411 * @arg @ref LL_AON_GPIO_MUX_6
412 * @arg @ref LL_AON_GPIO_MUX_7
413 * @arg @ref LL_AON_GPIO_MUX_8
414 * @retval None
415 */
ll_aon_gpio_set_mux_pin_0_7(uint32_t pin,uint32_t mux)416 __STATIC_INLINE void ll_aon_gpio_set_mux_pin_0_7(uint32_t pin, uint32_t mux)
417 {
418 uint32_t pos = POSITION_VAL(pin) << 2;
419 if (LL_AON_GPIO_MUX_7 == mux) {
420 CLEAR_BITS(AON->AON_PAD_CTL0, pin << AON_PAD_CTL0_MCU_OVR_Pos);
421 } else {
422 MODIFY_REG(MCU_SUB->AON_PAD_MUX_CTL, 0xF << pos, mux << pos);
423 SET_BITS(AON->AON_PAD_CTL0, pin << AON_PAD_CTL0_MCU_OVR_Pos);
424 }
425 }
426
427 /**
428 * @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
429 *
430 * Register|BitsName
431 * --------|--------
432 * AON_PAD_MUX_CTRL | CTRL0_7
433 * AON_PAD_CTL_0 | MCU_OVR
434 *
435 * @param pin This parameter can be one of the following values:
436 * @arg @ref LL_AON_GPIO_PIN_0
437 * @arg @ref LL_AON_GPIO_PIN_1
438 * @arg @ref LL_AON_GPIO_PIN_2
439 * @arg @ref LL_AON_GPIO_PIN_3
440 * @arg @ref LL_AON_GPIO_PIN_4
441 * @arg @ref LL_AON_GPIO_PIN_5
442 * @arg @ref LL_AON_GPIO_PIN_6
443 * @arg @ref LL_AON_GPIO_PIN_7
444 * @retval Returned value can be one of the following values:
445 * @arg @ref LL_AON_GPIO_MUX_0
446 * @arg @ref LL_AON_GPIO_MUX_1
447 * @arg @ref LL_AON_GPIO_MUX_2
448 * @arg @ref LL_AON_GPIO_MUX_3
449 * @arg @ref LL_AON_GPIO_MUX_4
450 * @arg @ref LL_AON_GPIO_MUX_5
451 * @arg @ref LL_AON_GPIO_MUX_6
452 * @arg @ref LL_AON_GPIO_MUX_7
453 * @arg @ref LL_AON_GPIO_MUX_8
454 */
ll_aon_gpio_get_mux_pin_0_7(uint32_t pin)455 __STATIC_INLINE uint32_t ll_aon_gpio_get_mux_pin_0_7(uint32_t pin)
456 {
457 if (READ_BITS(AON->AON_PAD_CTL0, pin << AON_PAD_CTL0_MCU_OVR_Pos)) {
458 uint32_t pos = POSITION_VAL(pin) << 2;
459 return (READ_BITS(MCU_SUB->AON_PAD_MUX_CTL, 0xF << pos) >> pos);
460 } else {
461 return LL_AON_GPIO_MUX_7;
462 }
463 }
464
465 /**
466 * @brief Enable Xo_2MHz output on AON_GPIO_PIN5.
467 *
468 * Register|BitsName
469 * --------|--------
470 * PWR_RET01 | XO_2MHZ_ENA
471 *
472 * @retval None
473 */
ll_aon_gpio_enable_xo_2mhz_output(void)474 __STATIC_INLINE void ll_aon_gpio_enable_xo_2mhz_output(void)
475 {
476 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_XO_2MHZ_ENA);
477 }
478
479 /**
480 * @brief Disable Xo_2MHz output on AON_GPIO_PIN5.
481 *
482 * Register|BitsName
483 * --------|--------
484 * PWR_RET01 | XO_2MHZ_ENA
485 *
486 * @retval None
487 */
ll_aon_gpio_disable_xo_2mhz_output(void)488 __STATIC_INLINE void ll_aon_gpio_disable_xo_2mhz_output(void)
489 {
490 CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_XO_2MHZ_ENA);
491 }
492
493 /**
494 * @brief Check if Xo_2MHz output on AON_GPIO_PIN5 is enabled or disabled.
495 *
496 * Register|BitsName
497 * --------|--------
498 * PWR_RET01 | XO_2MHZ_ENA
499 *
500 * @retval None
501 */
ll_aon_gpio_is_enabled_xo_2mhz_output(void)502 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_xo_2mhz_output(void)
503 {
504 return (uint32_t)(READ_BITS(AON->PWR_RET01, AON_PWR_REG01_XO_2MHZ_ENA) == AON_PWR_REG01_XO_2MHZ_ENA);
505 }
506
507 /** @} */
508
509 /** @defgroup AON_GPIO_LL_EF_Data_Access Data Access
510 * @{
511 */
512
513 /**
514 * @brief Return full input data register value of AON_GPIO.
515 *
516 * Register|BitsName
517 * --------|--------
518 * AON_PAD_CTL1 | O_AON_GPI
519 *
520 * @retval Input data register value of port
521 */
ll_aon_gpio_read_input_port(void)522 __STATIC_INLINE uint32_t ll_aon_gpio_read_input_port(void)
523 {
524 return (uint32_t)(READ_BITS(GPIO2->DATA, GPIO_DATA));
525 }
526
527 /**
528 * @brief Return if input data level of several AON_GPIO pins is high or low.
529 *
530 * Register|BitsName
531 * --------|--------
532 * AON_PAD_CTL1 | O_AON_GPI
533 *
534 * @param pin_mask This parameter can be a combination of the following values:
535 * @arg @ref LL_AON_GPIO_PIN_0
536 * @arg @ref LL_AON_GPIO_PIN_1
537 * @arg @ref LL_AON_GPIO_PIN_2
538 * @arg @ref LL_AON_GPIO_PIN_3
539 * @arg @ref LL_AON_GPIO_PIN_4
540 * @arg @ref LL_AON_GPIO_PIN_5
541 * @arg @ref LL_AON_GPIO_PIN_6
542 * @arg @ref LL_AON_GPIO_PIN_7
543 * @arg @ref LL_AON_GPIO_PIN_ALL
544 * @retval State of bit (1 or 0).
545 */
ll_aon_gpio_is_input_pin_set(uint32_t pin_mask)546 __STATIC_INLINE uint32_t ll_aon_gpio_is_input_pin_set(uint32_t pin_mask)
547 {
548 return (uint32_t)(READ_BITS(GPIO2->DATA, pin_mask) == pin_mask);
549 }
550
551 /**
552 * @brief Write output data register of AON_GPIO.
553 *
554 * Register|BitsName
555 * --------|--------
556 * AON_PAD_CTL1 | AON_GPO
557 *
558 * @param port_value Level value for each pin of the port
559 * @retval None
560 */
ll_aon_gpio_write_output_port(uint32_t port_value)561 __STATIC_INLINE void ll_aon_gpio_write_output_port(uint32_t port_value)
562 {
563 GLOBAL_EXCEPTION_DISABLE();
564 MODIFY_REG(AON->AON_PAD_CTL1, AON_PAD_CTL1_AON_GPO, \
565 (port_value << AON_PAD_CTL1_AON_GPO_Pos) & AON_PAD_CTL1_AON_GPO);
566 GLOBAL_EXCEPTION_ENABLE();
567 }
568
569 /**
570 * @brief Return full output data register value of AON_GPIO.
571 *
572 * Register|BitsName
573 * --------|--------
574 * AON_PAD_CTL1 | AON_GPO
575 *
576 * @retval Output data register value of port
577 */
ll_aon_gpio_read_output_port(void)578 __STATIC_INLINE uint32_t ll_aon_gpio_read_output_port(void)
579 {
580 return (uint32_t)(READ_BITS(AON->AON_PAD_CTL1, AON_PAD_CTL1_AON_GPO) >> AON_PAD_CTL1_AON_GPO_Pos);
581 }
582
583 /**
584 * @brief Return if input data level of several AON_GPIO pins is high or low.
585 *
586 * Register|BitsName
587 * --------|--------
588 * AON_PAD_CTL1 | AON_GPO
589 *
590 * @param pin_mask This parameter can be a combination of the following values:
591 * @arg @ref LL_AON_GPIO_PIN_0
592 * @arg @ref LL_AON_GPIO_PIN_1
593 * @arg @ref LL_AON_GPIO_PIN_2
594 * @arg @ref LL_AON_GPIO_PIN_3
595 * @arg @ref LL_AON_GPIO_PIN_4
596 * @arg @ref LL_AON_GPIO_PIN_5
597 * @arg @ref LL_AON_GPIO_PIN_6
598 * @arg @ref LL_AON_GPIO_PIN_7
599 * @arg @ref LL_AON_GPIO_PIN_ALL
600 * @retval State of bit (1 or 0).
601 */
ll_aon_gpio_is_output_pin_set(uint32_t pin_mask)602 __STATIC_INLINE uint32_t ll_aon_gpio_is_output_pin_set(uint32_t pin_mask)
603 {
604 pin_mask = (pin_mask << AON_PAD_CTL1_AON_GPO_Pos) & AON_PAD_CTL1_AON_GPO;
605 return (uint32_t)(READ_BITS(AON->AON_PAD_CTL1, pin_mask) == pin_mask);
606 }
607
608 /**
609 * @brief Set specified AON_GPIO pins to high level
610 *
611 * Register|BitsName
612 * --------|--------
613 * AON_PAD_CTL1 | AON_GPO
614 *
615 * @param pin_mask This parameter can be a combination of the following values:
616 * @arg @ref LL_AON_GPIO_PIN_0
617 * @arg @ref LL_AON_GPIO_PIN_1
618 * @arg @ref LL_AON_GPIO_PIN_2
619 * @arg @ref LL_AON_GPIO_PIN_3
620 * @arg @ref LL_AON_GPIO_PIN_4
621 * @arg @ref LL_AON_GPIO_PIN_5
622 * @arg @ref LL_AON_GPIO_PIN_6
623 * @arg @ref LL_AON_GPIO_PIN_7
624 * @arg @ref LL_AON_GPIO_PIN_ALL
625 * @retval None
626 */
ll_aon_gpio_set_output_pin(uint32_t pin_mask)627 __STATIC_INLINE void ll_aon_gpio_set_output_pin(uint32_t pin_mask)
628 {
629 GLOBAL_EXCEPTION_DISABLE();
630 SET_BITS(AON->AON_PAD_CTL1, (pin_mask << AON_PAD_CTL1_AON_GPO_Pos) & AON_PAD_CTL1_AON_GPO);
631 GLOBAL_EXCEPTION_ENABLE();
632 }
633
634 /**
635 * @brief Set specified AON_GPIO pins to low level.
636 *
637 * Register|BitsName
638 * --------|--------
639 * AON_PAD_CTL1 | AON_GPO
640 *
641 * @param pin_mask This parameter can be a combination of the following values:
642 * @arg @ref LL_AON_GPIO_PIN_0
643 * @arg @ref LL_AON_GPIO_PIN_1
644 * @arg @ref LL_AON_GPIO_PIN_2
645 * @arg @ref LL_AON_GPIO_PIN_3
646 * @arg @ref LL_AON_GPIO_PIN_4
647 * @arg @ref LL_AON_GPIO_PIN_5
648 * @arg @ref LL_AON_GPIO_PIN_6
649 * @arg @ref LL_AON_GPIO_PIN_7
650 * @arg @ref LL_AON_GPIO_PIN_ALL
651 * @retval None
652 */
ll_aon_gpio_reset_output_pin(uint32_t pin_mask)653 __STATIC_INLINE void ll_aon_gpio_reset_output_pin(uint32_t pin_mask)
654 {
655 GLOBAL_EXCEPTION_DISABLE();
656 CLEAR_BITS(AON->AON_PAD_CTL1, (pin_mask << AON_PAD_CTL1_AON_GPO_Pos) & AON_PAD_CTL1_AON_GPO);
657 GLOBAL_EXCEPTION_ENABLE();
658 }
659
660 /**
661 * @brief Toggle data value of specified AON_GPIO pins.
662 *
663 * Register|BitsName
664 * --------|--------
665 * AON_PAD_CTL1 | AON_GPO
666 *
667 * @param pin_mask This parameter can be a combination of the following values:
668 * @arg @ref LL_AON_GPIO_PIN_0
669 * @arg @ref LL_AON_GPIO_PIN_1
670 * @arg @ref LL_AON_GPIO_PIN_2
671 * @arg @ref LL_AON_GPIO_PIN_3
672 * @arg @ref LL_AON_GPIO_PIN_4
673 * @arg @ref LL_AON_GPIO_PIN_5
674 * @arg @ref LL_AON_GPIO_PIN_6
675 * @arg @ref LL_AON_GPIO_PIN_7
676 * @arg @ref LL_AON_GPIO_PIN_ALL
677 * @retval None
678 */
ll_aon_gpio_toggle_pin(uint32_t pin_mask)679 __STATIC_INLINE void ll_aon_gpio_toggle_pin(uint32_t pin_mask)
680 {
681 GLOBAL_EXCEPTION_DISABLE();
682 WRITE_REG(AON->AON_PAD_CTL1, \
683 (READ_REG(AON->AON_PAD_CTL1) ^ ((pin_mask << AON_PAD_CTL1_AON_GPO_Pos) & AON_PAD_CTL1_AON_GPO)));
684 GLOBAL_EXCEPTION_ENABLE();
685 }
686
687 /** @} */
688
689 /** @defgroup AON_GPIO_LL_EF_IT_Management IT_Management
690 * @{
691 */
692
693 /**
694 * @brief Enable AON_GPIO Falling Edge Trigger of specified AON_GPIO pins.
695 *
696 * Register|BitsName
697 * --------|--------
698 * INTPOLCLR | INTPOLCLR
699 * INTTYPESET | INTTYPESET
700 *
701 * @param pin_mask This parameter can be a combination of the following values:
702 * @arg @ref LL_AON_GPIO_PIN_0
703 * @arg @ref LL_AON_GPIO_PIN_1
704 * @arg @ref LL_AON_GPIO_PIN_2
705 * @arg @ref LL_AON_GPIO_PIN_3
706 * @arg @ref LL_AON_GPIO_PIN_4
707 * @arg @ref LL_AON_GPIO_PIN_5
708 * @arg @ref LL_AON_GPIO_PIN_6
709 * @arg @ref LL_AON_GPIO_PIN_7
710 * @arg @ref LL_AON_GPIO_PIN_ALL
711 * @retval None
712 */
ll_aon_gpio_enable_falling_trigger(uint32_t pin_mask)713 __STATIC_INLINE void ll_aon_gpio_enable_falling_trigger(uint32_t pin_mask)
714 {
715 WRITE_REG(GPIO2->INTPOLCLR, pin_mask);
716 WRITE_REG(GPIO2->INTTYPESET, pin_mask);
717 }
718
719 /**
720 * @brief Check if falling edge trigger is enabled of specified AON_GPIO pins.
721 *
722 * Register|BitsName
723 * --------|--------
724 * INTPOLCLR | INTPOLCLR
725 * INTTYPESET | INTTYPESET
726 *
727 * @param pin_mask This parameter can be a combination of the following values:
728 * @arg @ref LL_AON_GPIO_PIN_0
729 * @arg @ref LL_AON_GPIO_PIN_1
730 * @arg @ref LL_AON_GPIO_PIN_2
731 * @arg @ref LL_AON_GPIO_PIN_3
732 * @arg @ref LL_AON_GPIO_PIN_4
733 * @arg @ref LL_AON_GPIO_PIN_5
734 * @arg @ref LL_AON_GPIO_PIN_6
735 * @arg @ref LL_AON_GPIO_PIN_7
736 * @arg @ref LL_AON_GPIO_PIN_ALL
737 * @retval State of bit (1 or 0).
738 */
ll_aon_gpio_is_enabled_falling_trigger(uint32_t pin_mask)739 __STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_falling_trigger(uint32_t pin_mask)
740 {
741 return ((READ_BITS(GPIO2->INTPOLCLR, pin_mask) == (pin_mask)) &
742 (READ_BITS(GPIO2->INTTYPESET, pin_mask) == (pin_mask)));
743 }
744
745 /**
746 * @brief Enable AON_GPIO Rising Edge Trigger of specified AON_GPIO pins.
747 *
748 * Register|BitsName
749 * --------|--------
750 * INTPOLSET | INTPOLSET
751 * INTTYPESET | INTTYPESET
752 *
753 * @param pin_mask This parameter can be a combination of the following values:
754 * @arg @ref LL_AON_GPIO_PIN_0
755 * @arg @ref LL_AON_GPIO_PIN_1
756 * @arg @ref LL_AON_GPIO_PIN_2
757 * @arg @ref LL_AON_GPIO_PIN_3
758 * @arg @ref LL_AON_GPIO_PIN_4
759 * @arg @ref LL_AON_GPIO_PIN_5
760 * @arg @ref LL_AON_GPIO_PIN_6
761 * @arg @ref LL_AON_GPIO_PIN_7
762 * @arg @ref LL_AON_GPIO_PIN_ALL
763 * @retval None
764 */
ll_aon_gpio_enable_rising_trigger(uint32_t pin_mask)765 __STATIC_INLINE void ll_aon_gpio_enable_rising_trigger(uint32_t pin_mask)
766 {
767 WRITE_REG(GPIO2->INTPOLSET, pin_mask);
768 WRITE_REG(GPIO2->INTTYPESET, pin_mask);
769 }
770
771 /**
772 * @brief Check if rising edge trigger is enabled of specified AON_GPIO pins.
773 * @note Please check each device line mapping for AON_GPIO Line availability
774 *
775 * Register|BitsName
776 * --------|--------
777 * INTPOLSET | INTPOLSET
778 * INTTYPESET | INTTYPESET
779 *
780 * @param pin_mask This parameter can be a combination of the following values:
781 * @arg @ref LL_AON_GPIO_PIN_0
782 * @arg @ref LL_AON_GPIO_PIN_1
783 * @arg @ref LL_AON_GPIO_PIN_2
784 * @arg @ref LL_AON_GPIO_PIN_3
785 * @arg @ref LL_AON_GPIO_PIN_4
786 * @arg @ref LL_AON_GPIO_PIN_5
787 * @arg @ref LL_AON_GPIO_PIN_6
788 * @arg @ref LL_AON_GPIO_PIN_7
789 * @arg @ref LL_AON_GPIO_PIN_ALL
790 * @retval State of bit (1 or 0).
791 */
ll_aon_gpio_is_enabled_rising_trigger(uint32_t pin_mask)792 __STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_rising_trigger(uint32_t pin_mask)
793 {
794 return ((READ_BITS(GPIO2->INTPOLSET, pin_mask) == (pin_mask)) &
795 (READ_BITS(GPIO2->INTTYPESET, pin_mask) == (pin_mask)));
796 }
797
798 /**
799 * @brief Enable AON_GPIO High Level Trigger of specified AON_GPIO pins.
800 *
801 * Register|BitsName
802 * --------|--------
803 * INTPOLSET | INTPOLSET
804 * INTTYPECLR | INTTYPECLR
805 *
806 * @param pin_mask This parameter can be a combination of the following values:
807 * @arg @ref LL_AON_GPIO_PIN_0
808 * @arg @ref LL_AON_GPIO_PIN_1
809 * @arg @ref LL_AON_GPIO_PIN_2
810 * @arg @ref LL_AON_GPIO_PIN_3
811 * @arg @ref LL_AON_GPIO_PIN_4
812 * @arg @ref LL_AON_GPIO_PIN_5
813 * @arg @ref LL_AON_GPIO_PIN_6
814 * @arg @ref LL_AON_GPIO_PIN_7
815 * @arg @ref LL_AON_GPIO_PIN_ALL
816 * @retval None
817 */
ll_aon_gpio_enable_high_trigger(uint32_t pin_mask)818 __STATIC_INLINE void ll_aon_gpio_enable_high_trigger(uint32_t pin_mask)
819 {
820 WRITE_REG(GPIO2->INTPOLSET, pin_mask);
821 WRITE_REG(GPIO2->INTTYPECLR, pin_mask);
822 }
823
824 /**
825 * @brief Check if high level trigger is enabled of specified AON_GPIO pins.
826 *
827 * Register|BitsName
828 * --------|--------
829 * INTPOLSET | INTPOLSET
830 * INTTYPECLR | INTTYPECLR
831 *
832 * @param pin_mask This parameter can be a combination of the following values:
833 * @arg @ref LL_AON_GPIO_PIN_0
834 * @arg @ref LL_AON_GPIO_PIN_1
835 * @arg @ref LL_AON_GPIO_PIN_2
836 * @arg @ref LL_AON_GPIO_PIN_3
837 * @arg @ref LL_AON_GPIO_PIN_4
838 * @arg @ref LL_AON_GPIO_PIN_5
839 * @arg @ref LL_AON_GPIO_PIN_6
840 * @arg @ref LL_AON_GPIO_PIN_7
841 * @arg @ref LL_AON_GPIO_PIN_ALL
842 * @retval State of bit (1 or 0).
843 */
ll_aon_gpio_is_enabled_high_trigger(uint32_t pin_mask)844 __STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_high_trigger(uint32_t pin_mask)
845 {
846 return ((READ_BITS(GPIO2->INTPOLSET, pin_mask) == (pin_mask)) &
847 (READ_BITS(GPIO2->INTTYPECLR, pin_mask) == (pin_mask)));
848 }
849
850 /**
851 * @brief Enable AON_GPIO Low Level Trigger of specified AON_GPIO pins.
852 *
853 * Register|BitsName
854 * --------|--------
855 * INTPOLCLR | INTPOLCLR
856 * INTTYPECLR | INTTYPECLR
857 *
858 * @param pin_mask This parameter can be a combination of the following values:
859 * @arg @ref LL_AON_GPIO_PIN_0
860 * @arg @ref LL_AON_GPIO_PIN_1
861 * @arg @ref LL_AON_GPIO_PIN_2
862 * @arg @ref LL_AON_GPIO_PIN_3
863 * @arg @ref LL_AON_GPIO_PIN_4
864 * @arg @ref LL_AON_GPIO_PIN_5
865 * @arg @ref LL_AON_GPIO_PIN_6
866 * @arg @ref LL_AON_GPIO_PIN_7
867 * @arg @ref LL_AON_GPIO_PIN_ALL
868 * @retval None
869 */
ll_aon_gpio_enable_low_trigger(uint32_t pin_mask)870 __STATIC_INLINE void ll_aon_gpio_enable_low_trigger(uint32_t pin_mask)
871 {
872 WRITE_REG(GPIO2->INTPOLCLR, pin_mask);
873 WRITE_REG(GPIO2->INTTYPECLR, pin_mask);
874 }
875
876 /**
877 * @brief Check if low level trigger is enabled of specified AON_GPIO pins.
878 *
879 * Register|BitsName
880 * --------|--------
881 * INTPOLCLR | INTPOLCLR
882 * INTTYPECLR | INTTYPECLR
883 *
884 * @param pin_mask This parameter can be a combination of the following values:
885 * @arg @ref LL_AON_GPIO_PIN_0
886 * @arg @ref LL_AON_GPIO_PIN_1
887 * @arg @ref LL_AON_GPIO_PIN_2
888 * @arg @ref LL_AON_GPIO_PIN_3
889 * @arg @ref LL_AON_GPIO_PIN_4
890 * @arg @ref LL_AON_GPIO_PIN_5
891 * @arg @ref LL_AON_GPIO_PIN_6
892 * @arg @ref LL_AON_GPIO_PIN_7
893 * @arg @ref LL_AON_GPIO_PIN_ALL
894 * @retval State of bit (1 or 0).
895 */
ll_aon_gpio_is_enabled_low_trigger(uint32_t pin_mask)896 __STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_low_trigger(uint32_t pin_mask)
897 {
898 return ((READ_BITS(GPIO2->INTPOLCLR, pin_mask) == (pin_mask)) &
899 (READ_BITS(GPIO2->INTTYPECLR, pin_mask) == (pin_mask)));
900 }
901
902 /**
903 * @brief Enable AON_GPIO interrupts of specified AON_GPIO pins.
904 * @note @ref AON_GPIO_LL_EC_TRIGGER can be used to specify the interrupt trigger type
905 *
906 * Register|BitsName
907 * --------|--------
908 * INTENSET | INTENSET
909 *
910 * @param pin_mask This parameter can be a combination of the following values:
911 * @arg @ref LL_AON_GPIO_PIN_0
912 * @arg @ref LL_AON_GPIO_PIN_1
913 * @arg @ref LL_AON_GPIO_PIN_2
914 * @arg @ref LL_AON_GPIO_PIN_3
915 * @arg @ref LL_AON_GPIO_PIN_4
916 * @arg @ref LL_AON_GPIO_PIN_5
917 * @arg @ref LL_AON_GPIO_PIN_6
918 * @arg @ref LL_AON_GPIO_PIN_7
919 * @arg @ref LL_AON_GPIO_PIN_ALL
920 * @retval None
921 */
ll_aon_gpio_enable_it(uint32_t pin_mask)922 __STATIC_INLINE void ll_aon_gpio_enable_it(uint32_t pin_mask)
923 {
924 WRITE_REG(GPIO2->INTENSET, pin_mask);
925 }
926
927 /**
928 * @brief Disable AON_GPIO interrupts of specified AON_GPIO pins.
929 * @note @ref AON_GPIO_LL_EC_TRIGGER can be used to specify the interrupt trigger type
930 *
931 * Register|BitsName
932 * --------|--------
933 * INTENCLR | INTENCLR
934 *
935 * @param pin_mask This parameter can be a combination of the following values:
936 * @arg @ref LL_AON_GPIO_PIN_0
937 * @arg @ref LL_AON_GPIO_PIN_1
938 * @arg @ref LL_AON_GPIO_PIN_2
939 * @arg @ref LL_AON_GPIO_PIN_3
940 * @arg @ref LL_AON_GPIO_PIN_4
941 * @arg @ref LL_AON_GPIO_PIN_5
942 * @arg @ref LL_AON_GPIO_PIN_6
943 * @arg @ref LL_AON_GPIO_PIN_7
944 * @arg @ref LL_AON_GPIO_PIN_ALL
945 * @retval None
946 */
ll_aon_gpio_disable_it(uint32_t pin_mask)947 __STATIC_INLINE void ll_aon_gpio_disable_it(uint32_t pin_mask)
948 {
949 WRITE_REG(GPIO2->INTENCLR, pin_mask);
950 }
951
952 /**
953 * @brief Check if the Interrupt of specified GPIO pins is enabled or disabled.
954 *
955 * Register|BitsName
956 * --------|--------
957 * INTENSET | INTENSET
958 *
959 * @param pin_mask This parameter can be a combination of the following values:
960 * @arg @ref LL_AON_GPIO_PIN_0
961 * @arg @ref LL_AON_GPIO_PIN_1
962 * @arg @ref LL_AON_GPIO_PIN_2
963 * @arg @ref LL_AON_GPIO_PIN_3
964 * @arg @ref LL_AON_GPIO_PIN_4
965 * @arg @ref LL_AON_GPIO_PIN_5
966 * @arg @ref LL_AON_GPIO_PIN_6
967 * @arg @ref LL_AON_GPIO_PIN_7
968 * @arg @ref LL_AON_GPIO_PIN_ALL
969 * @retval State of bit (1 or 0).
970 */
ll_aon_gpio_is_enabled_it(uint32_t pin_mask)971 __STATIC_INLINE uint32_t ll_aon_gpio_is_enabled_it(uint32_t pin_mask)
972 {
973 return (READ_BITS(GPIO2->INTENSET, pin_mask) == (pin_mask));
974 }
975
976 /** @} */
977
978 /** @defgroup AON_GPIO_LL_EF_Flag_Management Flag_Management
979 * @{
980 */
981
982 /**
983 * @brief Read AON_GPIO Interrupt Combination Flag of specified AON_GPIO pins.
984 * @note After an interrupt is triggered, the corresponding bit in the INTSTATUS Register is set.
985 * The interrupt status can cleared by writing 1 to corresponding bit in INTCLEAR Register.
986 *
987 * Register|BitsName
988 * --------|--------
989 * INTSTATUS | INTSTATUS
990 *
991 * @param pin_mask This parameter can be a combination of the following values:
992 * @arg @ref LL_AON_GPIO_PIN_0
993 * @arg @ref LL_AON_GPIO_PIN_1
994 * @arg @ref LL_AON_GPIO_PIN_2
995 * @arg @ref LL_AON_GPIO_PIN_3
996 * @arg @ref LL_AON_GPIO_PIN_4
997 * @arg @ref LL_AON_GPIO_PIN_5
998 * @arg @ref LL_AON_GPIO_PIN_6
999 * @arg @ref LL_AON_GPIO_PIN_7
1000 * @arg @ref LL_AON_GPIO_PIN_ALL
1001 * @retval Interrupt flag whose bits were set when the selected trigger event arrives on the interrupt
1002 */
ll_aon_gpio_read_flag_it(uint32_t pin_mask)1003 __STATIC_INLINE uint32_t ll_aon_gpio_read_flag_it(uint32_t pin_mask)
1004 {
1005 uint32_t ext2 = READ_BITS(GPIO2->INTSTAT, pin_mask);
1006 uint32_t wkup = (READ_BITS(AON->SLP_EVENT, AON_SLP_EVENT_EXT_WKUP_STATUS) >> \
1007 AON_SLP_EVENT_EXT_WKUP_STATUS_Pos) & \
1008 pin_mask & READ_BITS(AON->EXT_WKUP_CTL, LL_AON_GPIO_PIN_ALL);
1009 return (uint32_t)(ext2 | wkup);
1010 }
1011
1012 /**
1013 * @brief Indicate if the AON_GPIO Interrupt Flag is set or not of specified AON_GPIO pins.
1014 * @note After an interrupt is triggered, the corresponding bit in the INTSTATUS Register is set.
1015 * The interrupt status can cleared by writing 1 to corresponding bit in INTCLEAR Register.
1016 *
1017 * Register|BitsName
1018 * --------|--------
1019 * INTSTATUS | INTSTATUS
1020 *
1021 * @param pin_mask This parameter can be a combination of the following values:
1022 * @arg @ref LL_AON_GPIO_PIN_0
1023 * @arg @ref LL_AON_GPIO_PIN_1
1024 * @arg @ref LL_AON_GPIO_PIN_2
1025 * @arg @ref LL_AON_GPIO_PIN_3
1026 * @arg @ref LL_AON_GPIO_PIN_4
1027 * @arg @ref LL_AON_GPIO_PIN_5
1028 * @arg @ref LL_AON_GPIO_PIN_6
1029 * @arg @ref LL_AON_GPIO_PIN_7
1030 * @arg @ref LL_AON_GPIO_PIN_ALL
1031 * @retval State of bit (1 or 0).
1032 */
ll_aon_gpio_is_active_flag_it(uint32_t pin_mask)1033 __STATIC_INLINE uint32_t ll_aon_gpio_is_active_flag_it(uint32_t pin_mask)
1034 {
1035 return (READ_BITS(GPIO2->INTSTAT, pin_mask) == pin_mask);
1036 }
1037
1038 /**
1039 * @brief Clear Interrupt Status flag of specified AON_GPIO pins.
1040 * @note After an interrupt is triggered, the corresponding bit in the INTSTATUS Register is set.
1041 * The interrupt status can be cleared by writing 1 to corresponding bit in INTCLEAR Register.
1042 *
1043 * Register|BitsName
1044 * --------|--------
1045 * INTSTATUS | INTSTATUS
1046 *
1047 * @param pin_mask This parameter can be a combination of the following values:
1048 * @arg @ref LL_AON_GPIO_PIN_0
1049 * @arg @ref LL_AON_GPIO_PIN_1
1050 * @arg @ref LL_AON_GPIO_PIN_2
1051 * @arg @ref LL_AON_GPIO_PIN_3
1052 * @arg @ref LL_AON_GPIO_PIN_4
1053 * @arg @ref LL_AON_GPIO_PIN_5
1054 * @arg @ref LL_AON_GPIO_PIN_6
1055 * @arg @ref LL_AON_GPIO_PIN_7
1056 * @arg @ref LL_AON_GPIO_PIN_ALL
1057 * @retval None
1058 */
ll_aon_gpio_clear_flag_it(uint32_t pin_mask)1059 __STATIC_INLINE void ll_aon_gpio_clear_flag_it(uint32_t pin_mask)
1060 {
1061 WRITE_REG(GPIO2->INTSTAT, pin_mask);
1062 }
1063
1064 /** @} */
1065
1066 /** @defgroup AON_GPIO_LL_EF_Init Initialization and de-initialization functions
1067 * @{
1068 */
1069
1070 /**
1071 * @brief De-initialize AON_GPIO registers (Registers restored to their default values).
1072 * @retval An error_status_t enumeration value:
1073 * - SUCCESS: AON_GPIO registers are de-initialized
1074 * - ERROR: AON_GPIO registers are not de-initialized
1075 */
1076 error_status_t ll_aon_gpio_deinit(void);
1077
1078 /**
1079 * @brief Initialize AON_GPIO registers according to the specified.
1080 * parameters in p_aon_gpio_init.
1081 * @param p_aon_gpio_init Pointer to a ll_aon_gpio_init_t structure that contains the configuration
1082 * information for the specified AON_GPIO peripheral.
1083 * @retval An error_status_t enumeration value:
1084 * - SUCCESS: AON_GPIO registers are initialized according to p_aon_gpio_init content
1085 * - ERROR: Problem occurred during AON_GPIO Registers initialization
1086 */
1087 error_status_t ll_aon_gpio_init(ll_aon_gpio_init_t *p_aon_gpio_init);
1088
1089 /**
1090 * @brief Set each field of a @ref ll_aon_gpio_init_t type structure to default value.
1091 * @param p_aon_gpio_init Pointer to a @ref ll_aon_gpio_init_t structure
1092 * whose fields will be set to default values.
1093 * @retval None
1094 */
1095 void ll_aon_gpio_struct_init(ll_aon_gpio_init_t *p_aon_gpio_init);
1096
1097 /** @} */
1098
1099 /** @} */
1100
1101 #endif /* AON */
1102
1103 #ifdef __cplusplus
1104 }
1105 #endif
1106
1107 #endif /* __GR55XX_LL_AON_GPIO_H__ */
1108
1109 /** @} */
1110
1111 /** @} */
1112
1113 /** @} */
1114