1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_i2c.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of I2C LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_I2C I2C
47 * @brief I2C LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55xx_LL_I2C_H__
53 #define __GR55xx_LL_I2C_H__
54
55 /* Includes ------------------------------------------------------------------*/
56 #include "gr55xx.h"
57
58 #ifdef __cplusplus
59 extern "C" {
60 #endif
61
62 #if defined (I2C0) || defined (I2C1)
63
64 /** @defgroup I2C_LL_STRUCTURES Structures
65 * @{
66 */
67
68 /* Exported types ------------------------------------------------------------*/
69 /** @defgroup I2C_LL_ES_INIT I2C Exported init structure
70 * @{
71 */
72
73 /**
74 * @brief LL I2C init Structure definition
75 */
76 typedef struct _ll_i2c_init {
77 uint32_t speed; /**< Specifies the transfer speed. See @ref I2C_LL_EC_SPEED. */
78
79 uint32_t own_address; /**< Specifies the device own address.
80 This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF
81
82 This feature can be modified afterwards using unitary function
83 @ref ll_i2c_set_own_address(). */
84
85 uint32_t own_addr_size; /**< Specifies the device own address 1 size (7-bit or 10-bit).
86 This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS
87
88 This feature can be modified afterwards using unitary function
89 @ref ll_i2c_set_own_address(). */
90 } ll_i2c_init_t;
91
92 /** @} */
93
94 /** @} */
95
96 /**
97 * @defgroup I2C_LL_MACRO Defines
98 * @{
99 */
100
101 /* Exported constants --------------------------------------------------------*/
102 /** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
103 * @{
104 */
105
106 /** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
107 * @brief Flags definitions which can be used with LL_I2C_ReadReg function
108 * @{
109 */
110 #define LL_I2C_INTR_STAT_MST_ON_HOLD I2C_INTR_GEN_CALL /**< MST_ON_HOLD interrupt flag */
111 #define LL_I2C_INTR_STAT_RESTART_DET I2C_INTR_RESTART_DET /**< RESTART_DET interrupt flag */
112 #define LL_I2C_INTR_STAT_GEN_CALL I2C_INTR_GEN_CALL /**< GEN_CALL interrupt flag */
113 #define LL_I2C_INTR_STAT_START_DET I2C_INTR_START_DET /**< START_DET interrupt flag */
114 #define LL_I2C_INTR_STAT_STOP_DET I2C_INTR_STOP_DET /**< STOP_DET interrupt flag */
115 #define LL_I2C_INTR_STAT_ACTIVITY I2C_INTR_ACTIVITY /**< ACTIVITY interrupt flag */
116 #define LL_I2C_INTR_STAT_RX_DONE I2C_INTR_RX_DONE /**< RX_DONE interrupt flag */
117 #define LL_I2C_INTR_STAT_TX_ABRT I2C_INTR_TX_ABRT /**< TX_ABRT interrupt flag */
118 #define LL_I2C_INTR_STAT_RD_REQ I2C_INTR_RD_REQ /**< RD_REQ interrupt flag */
119 #define LL_I2C_INTR_STAT_TX_EMPTY I2C_INTR_TX_EMPTY /**< TX_EMPTY interrupt flag */
120 #define LL_I2C_INTR_STAT_TX_OVER I2C_INTR_TX_OVER /**< TX_OVER interrupt flag */
121 #define LL_I2C_INTR_STAT_RX_FULL I2C_INTR_RX_FULL /**< RX_FULL interrupt flag */
122 #define LL_I2C_INTR_STAT_RX_OVER I2C_INTR_RX_OVER /**< RX_OVER interrupt flag */
123 #define LL_I2C_INTR_STAT_RX_UNDER I2C_INTR_RX_UNDER /**< RX_UNDER interrupt flag */
124
125 #define LL_I2C_ABRT_TX_FLUSH_CNT I2C_TX_ABRT_SRC_TX_FLUSH_CNT /**< Transfer abort detected by master */
126 #define LL_I2C_ABRT_USER_ABRT I2C_TX_ABRT_SRC_USER_ABRT /**< Transfer abort detected by master */
127 #define LL_I2C_ABRT_SLVRD_INTX I2C_TX_ABRT_SRC_SLVRD_INTX /**< Slave trying to transmit to
128 remote master in read mode */
129 #define LL_I2C_ABRT_SLV_ARBLOST I2C_TX_ABRT_SRC_SLV_ARBLOST /**< Slave lost arbitration to
130 remote master */
131 #define LL_I2C_ABRT_SLVFLUSH_TXFIFO I2C_TX_ABRT_SRC_SLVFLUSH_TXFIFO /**< Slave flushes existing data
132 in TX-FIFO upon getting read command */
133 #define LL_I2C_ABRT_ARB_LOST I2C_TX_ABRT_SRC_ARB_LOST /**< Master or Slave Transmitter
134 lost arbitration */
135 #define LL_I2C_ABRT_MST_DIS I2C_TX_ABRT_SRC_MST_DIS /**< User intitating master operation
136 when MASTER disabled */
137 #define LL_I2C_ABRT_10B_RD_NORSTRT I2C_TX_ABRT_SRC_10B_RD_NORSTRT /**< Master trying to read in 10-Bit
138 addressing mode when RESTART disable */
139 #define LL_I2C_ABRT_SBYTE_NORSTRT I2C_TX_ABRT_SRC_SBYTE_NORSTRT /**< User trying to send START byte
140 when RESTART disabled */
141 #define LL_I2C_ABRT_HS_NORSTRT I2C_TX_ABRT_SRC_HS_NORSTRT /**< User trying to swidth Master to HS mode
142 when RESTART disabled */
143 #define LL_I2C_ABRT_SBYTE_ACKDET I2C_TX_ABRT_SRC_SBYTE_ACKDET /**< ACK detected for START byte */
144 #define LL_I2C_ABRT_HS_ACKDET I2C_TX_ABRT_SRC_HS_ACKDET /**< HS Master code is ACKed in HS Mode */
145 #define LL_I2C_ABRT_GCALL_READ I2C_TX_ABRT_SRC_GCALL_READ /**< GCALL is followed by read from bus */
146 #define LL_I2C_ABRT_GCALL_NOACK I2C_TX_ABRT_SRC_GCALL_NOACK /**< GCALL is not ACKed by any slave */
147 #define LL_I2C_ABRT_TXDATA_NOACK I2C_TX_ABRT_SRC_TXDATA_NOACK /**< Transmitted data is not ACKed
148 by addressed slave */
149 #define LL_I2C_ABRT_10ADDR2_NOACK I2C_TX_ABRT_SRC_10ADDR2_NOACK /**< Byte 2 of 10-Bit Address is not ACKed
150 by any slave */
151 #define LL_I2C_ABRT_10ADDR1_NOACK I2C_TX_ABRT_SRC_10ADDR1_NOACK /**< Byte 1 of 10-Bit Address is not ACKed
152 by any slave */
153 #define LL_I2C_ABRT_7B_ADDR_NOACK I2C_TX_ABRT_SRC_7B_ADDR_NOACK /**< 7Bit Address is not ACKed
154 by any slave */
155 /** @} */
156
157 /** @defgroup I2C_LL_EC_IT IT Defines
158 * @brief Interrupt definitions which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions
159 * @{
160 */
161 #define LL_I2C_INTR_MASK_MST_ON_HOLD I2C_INTR_GEN_CALL /**< MST_ON_HOLD interrupt */
162 #define LL_I2C_INTR_MASK_RESTART_DET I2C_INTR_RESTART_DET /**< RESTART_DET interrupt */
163 #define LL_I2C_INTR_MASK_GEN_CALL I2C_INTR_GEN_CALL /**< GEN_CALL interrupt */
164 #define LL_I2C_INTR_MASK_START_DET I2C_INTR_START_DET /**< START_DET interrupt */
165 #define LL_I2C_INTR_MASK_STOP_DET I2C_INTR_STOP_DET /**< STOP_DET interrupt */
166 #define LL_I2C_INTR_MASK_ACTIVITY I2C_INTR_ACTIVITY /**< ACTIVITY interrupt */
167 #define LL_I2C_INTR_MASK_RX_DONE I2C_INTR_RX_DONE /**< RX_DONE interrupt */
168 #define LL_I2C_INTR_MASK_TX_ABRT I2C_INTR_TX_ABRT /**< TX_ABRT interrupt */
169 #define LL_I2C_INTR_MASK_RD_REQ I2C_INTR_RD_REQ /**< RD_REQ interrupt */
170 #define LL_I2C_INTR_MASK_TX_EMPTY I2C_INTR_TX_EMPTY /**< TX_EMPTY interrupt */
171 #define LL_I2C_INTR_MASK_TX_OVER I2C_INTR_TX_OVER /**< TX_OVER interrupt */
172 #define LL_I2C_INTR_MASK_RX_FULL I2C_INTR_RX_FULL /**< RX_FULL interrupt */
173 #define LL_I2C_INTR_MASK_RX_OVER I2C_INTR_RX_OVER /**< RX_OVER interrupt */
174 #define LL_I2C_INTR_MASK_RX_UNDER I2C_INTR_RX_UNDER /**< RX_UNDER interrupt */
175
176 #define LL_I2C_INTR_MASK_ALL 0x00000FFFU /**< All interrupt */
177 /** @} */
178
179 /** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode
180 * @{
181 */
182 #define LL_I2C_ADDRESSING_MODE_7BIT 0x00000000U /**< Master operates in 7-bit addressing mode. */
183 #define LL_I2C_ADDRESSING_MODE_10BIT I2C_CON_10BITADDR_MST /**< Master operates in 10-bit addressing mode.*/
184 /** @} */
185
186 /** @defgroup I2C_LL_EC_OWNADDRESS Own Address Length
187 * @{
188 */
189 #define LL_I2C_OWNADDRESS_7BIT 0x00000000U /**< Own address 1 is a 7-bit address. */
190 #define LL_I2C_OWNADDRESS_10BIT I2C_CON_10BITADDR_SLV /**< Own address 1 is a 10-bit address.*/
191 /** @} */
192
193
194 /** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation
195 * @{
196 */
197 #define LL_I2C_CMD_SLV_NONE 0x00000000U /**< Slave No command. */
198 #define LL_I2C_CMD_MST_WRITE 0x00000000U /**< Master write command. */
199 #define LL_I2C_CMD_MST_READ I2C_DATA_CMD_CMD /**< Master read command. */
200 #define LL_I2C_CMD_MST_GEN_STOP I2C_DATA_CMD_STOP /**< Master issue STOP after this command. */
201 #define LL_I2C_CMD_MST_GEN_RESTART I2C_DATA_CMD_RESTART /**< Master issue RESTART before this command. */
202 /** @} */
203
204 /** @defgroup I2C_LL_EC_SPEED_MODE Transfer Speed Mode
205 * @{
206 */
207 #define LL_I2C_SPEED_MODE_STANDARD I2C_CON_SPEED_STANDARD /**< Standard Speed mode (0 to 100 Kb/s)
208 of operation. */
209 #define LL_I2C_SPEED_MODE_FAST I2C_CON_SPEED_FAST /**< Fast (鈮?400 Kb/s) or
210 Fast Plus mode (鈮?1000 螝b/s) of operation. */
211 #define LL_I2C_SPEED_MODE_HIGH I2C_CON_SPEED_HIGH /**< High Speed mode (鈮?3.4 Mb/s) of operation. */
212 /** @} */
213
214 /** @defgroup I2C_LL_EC_SPEED Transfer Speed
215 * @{
216 */
217 #define LL_I2C_SPEED_100K (100000ul) /**< Standard Speed. */
218 #define LL_I2C_SPEED_400K (400000ul) /**< Fast Speed. */
219 #define LL_I2C_SPEED_1000K (1000000ul) /**< Fast Plus Speed. */
220 #define LL_I2C_SPEED_2000K (2000000ul) /**< High Speed. */
221 /** @} */
222
223 /** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
224 * @{
225 */
226 #define LL_I2C_DIRECTION_NONE 0x00000000U /**< No transfer request by master. */
227 #define LL_I2C_DIRECTION_WRITE I2C_INTR_RX_FULL /**< Write transfer request by master,
228 slave enters receiver mode. */
229 #define LL_I2C_DIRECTION_READ I2C_INTR_RD_REQ /**< Read transfer request by master,
230 slave enters transmitter mode. */
231 #define LL_I2C_DIRECTION_ERROR I2C_INTR_RX_FULL | I2C_INTR_RD_REQ /**< Transfer request error. */
232 /** @} */
233
234
235 /** @defgroup I2C_LL_EC_TX_FIFO_TH TX FIFO Threshold
236 * @{
237 */
238 #define LL_I2C_TX_FIFO_TH_EMPTY 0x00000000U /**< TX FIFO empty */
239 #define LL_I2C_TX_FIFO_TH_CHAR_1 0x00000001U /**< 1 character in TX FIFO */
240 #define LL_I2C_TX_FIFO_TH_CHAR_2 0x00000002U /**< 2 characters in TX FIFO */
241 #define LL_I2C_TX_FIFO_TH_CHAR_3 0x00000003U /**< 3 characters in TX FIFO */
242 #define LL_I2C_TX_FIFO_TH_CHAR_4 0x00000004U /**< 4 characters in TX FIFO */
243 #define LL_I2C_TX_FIFO_TH_CHAR_5 0x00000005U /**< 5 characters in TX FIFO */
244 #define LL_I2C_TX_FIFO_TH_CHAR_6 0x00000006U /**< 6 characters in TX FIFO */
245 #define LL_I2C_TX_FIFO_TH_CHAR_7 0x00000007U /**< 7 characters in TX FIFO */
246 /** @} */
247
248 /** @defgroup I2C_LL_EC_RX_FIFO_TH RX FIFO Threshold
249 * @{
250 */
251 #define LL_I2C_RX_FIFO_TH_CHAR_1 0x00000000U /**< 1 character in RX FIFO */
252 #define LL_I2C_RX_FIFO_TH_CHAR_2 0x00000001U /**< 2 characters in RX FIFO */
253 #define LL_I2C_RX_FIFO_TH_CHAR_3 0x00000002U /**< 3 characters in RX FIFO */
254 #define LL_I2C_RX_FIFO_TH_CHAR_4 0x00000003U /**< 4 characters in RX FIFO */
255 #define LL_I2C_RX_FIFO_TH_CHAR_5 0x00000004U /**< 5 characters in RX FIFO */
256 #define LL_I2C_RX_FIFO_TH_CHAR_6 0x00000005U /**< 6 characters in RX FIFO */
257 #define LL_I2C_RX_FIFO_TH_CHAR_7 0x00000006U /**< 7 characters in RX FIFO */
258 #define LL_I2C_RX_FIFO_TH_FULL 0x00000007U /**< RX FIFO full */
259 /** @} */
260
261 /** @defgroup I2C_LL_EC_DEFAULT_CONFIG InitStrcut default configuartion
262 * @{
263 */
264
265 /**
266 * @brief LL I2C InitStrcut default configuartion
267 */
268 #define LL_I2C_DEFAULT_CONFIG \
269 { \
270 .speed = LL_I2C_SPEED_400K, \
271 .own_address = 0x55U, \
272 .own_addr_size = LL_I2C_OWNADDRESS_7BIT, \
273 }
274 /** @} */
275
276 /** @} */
277
278 /* Exported macro ------------------------------------------------------------*/
279 /** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
280 * @{
281 */
282
283 /** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
284 * @{
285 */
286
287 /**
288 * @brief Write a value in I2C register
289 * @param __instance__ I2C instance
290 * @param __REG__ Register to be written
291 * @param __VALUE__ Value to be written in the register
292 * @retval None.
293 */
294 #define LL_I2C_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
295
296 /**
297 * @brief Read a value in I2C register
298 * @param __instance__ I2C instance
299 * @param __REG__ Register to be read
300 * @retval Register value
301 */
302 #define LL_I2C_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
303 /** @} */
304
305 /** @defgroup I2C_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
306 * @{
307 */
308
309 /**
310 * @brief Compute CLK_SSL_CNT value according to Peripheral Clock and expected Speed.
311 * @param __PERIPHCLK__ Peripheral Clock frequency used for I2C instance
312 * @param __SPEED__ Speed value to achieve
313 * @retval CLK_SSL_CNT value to be used for XS_SCL_HCNT, XS_SCL_LCNT registers where X can be (S, F, H)
314 */
315 #define __LL_I2C_CONVERT_CLK_SSL_CNT(__PERIPHCLK__, __SPEED__) ((__PERIPHCLK__) / 2 / (__SPEED__))
316
317 /**
318 * @brief Get Speed Mode according to expected Speed.
319 * @param __SPEED__ Speed value to achieve
320 * @retval Returned value can be one of the following values:
321 * @arg @ref LL_I2C_SPEED_MODE_STANDARD
322 * @arg @ref LL_I2C_SPEED_MODE_FAST
323 * @arg @ref LL_I2C_SPEED_MODE_HIGH
324 */
325 #define __LL_I2C_CONVERT_SPEED_MODE(__SPEED__) ((__SPEED__ <= LL_I2C_SPEED_100K) ? LL_I2C_SPEED_MODE_STANDARD : \
326 ((__SPEED__ <= LL_I2C_SPEED_1000K) ? LL_I2C_SPEED_MODE_FAST : \
327 LL_I2C_SPEED_MODE_HIGH))
328 /** @} */
329
330 /** @} */
331
332 /** @} */
333
334 /* Private types -------------------------------------------------------------*/
335 /* Private variables ---------------------------------------------------------*/
336 /* Private constants ---------------------------------------------------------*/
337 /* Private macros ------------------------------------------------------------*/
338
339 /* Exported functions --------------------------------------------------------*/
340 /** @defgroup I2C_LL_DRIVER_FUNCTIONS Functions
341 * @{
342 */
343
344 /** @defgroup I2C_LL_EF_Configuration Configuration
345 * @{
346 */
347
348 /**
349 * @brief Enable I2C peripheral (ENABLE = 1).
350 *
351 * Register|BitsName
352 * --------|--------
353 * IC_ENABLE | ENABLE
354 *
355 * @param I2Cx I2C instance.
356 * @retval None.
357 */
ll_i2c_enable(i2c_regs_t * I2Cx)358 __STATIC_INLINE void ll_i2c_enable(i2c_regs_t *I2Cx)
359 {
360 SET_BITS(I2Cx->ENABLE, I2C_ENABLE_ENABLE);
361 }
362
363 /**
364 * @brief Disable I2C peripheral (ENABLE = 0).
365 * @note When ENABLE = 0, the TX FIFO and RX FIFO get flushed.
366 * Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state.
367 * If the module is transmitting, it stops as well as deletes the contents of the transmit buffer
368 * after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops
369 * the current transfer at the end of the current byte and does not acknowledge the transfer..
370 *
371 * Register|BitsName
372 * --------|--------
373 * IC_ENABLE | ENABLE
374 *
375 * @param I2Cx I2C instance.
376 * @retval None.
377 */
ll_i2c_disable(i2c_regs_t * I2Cx)378 __STATIC_INLINE void ll_i2c_disable(i2c_regs_t *I2Cx)
379 {
380 CLEAR_BITS(I2Cx->ENABLE, I2C_ENABLE_ENABLE);
381 }
382
383 /**
384 * @brief Check if the I2C peripheral is enabled or disabled.
385 *
386 * Register|BitsName
387 * --------|--------
388 * IC_ENABLE_STATUS | IC_EN
389 *
390 * @param I2Cx I2C instance.
391 * @retval State of bit (1 or 0).
392 */
ll_i2c_is_enabled(i2c_regs_t * I2Cx)393 __STATIC_INLINE uint32_t ll_i2c_is_enabled(i2c_regs_t *I2Cx)
394 {
395 return (READ_BITS(I2Cx->ENABLE_STATUS, I2C_ENABLE_STATUS_IC_EN) == (I2C_ENABLE_STATUS_IC_EN));
396 }
397
398 /**
399 * @brief Enable I2C master mode.
400 *
401 * Register|BitsName
402 * --------|--------
403 * IC_CON | MASTER_ENABLE
404 * IC_CON | SLAVE_DISABLE
405 * @param I2Cx I2C instance.
406 * @retval None.
407 */
ll_i2c_enable_master_mode(i2c_regs_t * I2Cx)408 __STATIC_INLINE void ll_i2c_enable_master_mode(i2c_regs_t *I2Cx)
409 {
410 SET_BITS(I2Cx->CON, I2C_CON_MST_MODE | I2C_CON_SLV_DIS);
411 }
412
413 /**
414 * @brief Disable I2C master mode and enable slave mode.
415 *
416 * Register|BitsName
417 * --------|--------
418 * IC_CON | MASTER_ENABLE
419 * IC_CON | SLAVE_DISABLE
420 * @param I2Cx I2C instance.
421 * @retval None.
422 */
ll_i2c_disable_master_mode(i2c_regs_t * I2Cx)423 __STATIC_INLINE void ll_i2c_disable_master_mode(i2c_regs_t *I2Cx)
424 {
425 CLEAR_BITS(I2Cx->CON, I2C_CON_MST_MODE | I2C_CON_SLV_DIS);
426 }
427
428 /**
429 * @brief Check if I2C master mode is enabled or disabled.
430 *
431 * Register|BitsName
432 * --------|--------
433 * IC_CON | MASTER_ENABLE
434 * IC_CON | SLAVE_DISABLE
435 *
436 * @param I2Cx I2C instance.
437 * @retval State of bit (1 or 0).
438 */
ll_i2c_is_enabled_master_mode(i2c_regs_t * I2Cx)439 __STATIC_INLINE uint32_t ll_i2c_is_enabled_master_mode(i2c_regs_t *I2Cx)
440 {
441 return (READ_BITS(I2Cx->CON, I2C_CON_MST_MODE | I2C_CON_SLV_DIS) == (I2C_CON_MST_MODE | I2C_CON_SLV_DIS));
442 }
443
444 /**
445 * @brief Enable General Call(slave mode).
446 * @note When enabled, the Address 0x00 is ACKed.
447 *
448 * Register|BitsName
449 * --------|--------
450 * IC_ACK_GENERAL_CALL | ACK_GEN_CALL
451 *
452 * @param I2Cx I2C instance.
453 * @retval None.
454 */
ll_i2c_enable_general_call(i2c_regs_t * I2Cx)455 __STATIC_INLINE void ll_i2c_enable_general_call(i2c_regs_t *I2Cx)
456 {
457 SET_BITS(I2Cx->ACK_GENERAL_CALL, I2C_ACK_GENERAL_CALL_ACK_GC);
458 }
459
460 /**
461 * @brief Disable General Call(slave mode).
462 * @note When disabled, the Address 0x00 is NACKed.
463 *
464 * Register|BitsName
465 * --------|--------
466 * IC_ACK_GENERAL_CALL | ACK_GEN_CALL
467 *
468 * @param I2Cx I2C instance.
469 * @retval None.
470 */
ll_i2c_disable_general_call(i2c_regs_t * I2Cx)471 __STATIC_INLINE void ll_i2c_disable_general_call(i2c_regs_t *I2Cx)
472 {
473 CLEAR_BITS(I2Cx->ACK_GENERAL_CALL, I2C_ACK_GENERAL_CALL_ACK_GC);
474 }
475
476 /**
477 * @brief Check if General Call is enabled or disabled(slave mode).
478 *
479 * Register|BitsName
480 * --------|--------
481 * IC_ACK_GENERAL_CALL | ACK_GEN_CALL
482 *
483 * @param I2Cx I2C instance.
484 * @retval State of bit (1 or 0).
485 */
ll_i2c_is_enabled_general_call(i2c_regs_t * I2Cx)486 __STATIC_INLINE uint32_t ll_i2c_is_enabled_general_call(i2c_regs_t *I2Cx)
487 {
488 return (READ_BITS(I2Cx->ACK_GENERAL_CALL, I2C_ACK_GENERAL_CALL_ACK_GC) == (I2C_ACK_GENERAL_CALL_ACK_GC));
489 }
490
491 /**
492 * @brief Enable Master Restart.
493 * @note The register IC_CON can only be programmed when the I2C is disabled (ENABLE = 0).
494 * This bit determines whether RESTART conditions may be sent when acting as a master.
495 * Some older slaves do not support handling RESTART conditions.
496 * When RESTART is disabled, the master is prohibited from performing the following functions:
497 * - Performing any high-speed mode operation.
498 * - Performing direction changes in combined format mode.
499 * - Performing a read operation with a 10-bit address.
500 *
501 * Register|BitsName
502 * --------|--------
503 * IC_CON | CON_RESTART_EN
504 *
505 * @param I2Cx I2C instance.
506 * @retval None.
507 */
ll_i2c_enable_master_restart(i2c_regs_t * I2Cx)508 __STATIC_INLINE void ll_i2c_enable_master_restart(i2c_regs_t *I2Cx)
509 {
510 SET_BITS(I2Cx->CON, I2C_CON_RESTART_EN);
511 }
512
513 /**
514 * @brief Disable Master Restart.
515 * @note The register IC_CON can only be programmed when the I2C is disabled (ENABLE = 0).
516 *
517 * Register|BitsName
518 * --------|--------
519 * IC_CON | CON_RESTART_EN
520 *
521 * @param I2Cx I2C instance.
522 * @retval None.
523 */
ll_i2c_disable_master_restart(i2c_regs_t * I2Cx)524 __STATIC_INLINE void ll_i2c_disable_master_restart(i2c_regs_t *I2Cx)
525 {
526 CLEAR_BITS(I2Cx->CON, I2C_CON_RESTART_EN);
527 }
528
529 /**
530 * @brief Check if Master Restart is enabled or disabled.
531 *
532 * Register|BitsName
533 * --------|--------
534 * IC_CON | CON_RESTART_EN
535 *
536 * @param I2Cx I2C instance.
537 * @retval State of bit (1 or 0).
538 */
ll_i2c_is_enabled_master_restart(i2c_regs_t * I2Cx)539 __STATIC_INLINE uint32_t ll_i2c_is_enabled_master_restart(i2c_regs_t *I2Cx)
540 {
541 return (READ_BITS(I2Cx->CON, I2C_CON_RESTART_EN) == (I2C_CON_RESTART_EN));
542 }
543
544 /**
545 * @brief Enable Slave issues STOP_DET interrupt only if addressed function.
546 * @note The register IC_CON can only be programmed when the I2C is disabled (ENABLE = 0).
547 * During a general call address, the slave does not issue the STOP_DET interrupt if
548 * STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address
549 * by generating ACK. The STOP_DET interrupt is generated only when the transmitted
550 * address matches the slave address (SAR).
551 *
552 * Register|BitsName
553 * --------|--------
554 * IC_CON | STOP_DET_IF_ADDRESSED
555 *
556 * @param I2Cx I2C instance.
557 * @retval None.
558 */
ll_i2c_enable_stop_det_if_addressed(i2c_regs_t * I2Cx)559 __STATIC_INLINE void ll_i2c_enable_stop_det_if_addressed(i2c_regs_t *I2Cx)
560 {
561 SET_BITS(I2Cx->CON, I2C_CON_STOP_DET_IF_ADDRESSED);
562 }
563
564 /**
565 * @brief Disable Slave issues STOP_DET interrupt only if addressed function.
566 * @note The register IC_CON can only be programmed when the I2C is disabled (ENABLE = 0).
567 *
568 * Register|BitsName
569 * --------|--------
570 * IC_CON | STOP_DET_IF_ADDRESSED
571 *
572 * @param I2Cx I2C instance.
573 * @retval None.
574 */
ll_i2c_disable_stop_det_if_addressed(i2c_regs_t * I2Cx)575 __STATIC_INLINE void ll_i2c_disable_stop_det_if_addressed(i2c_regs_t *I2Cx)
576 {
577 CLEAR_BITS(I2Cx->CON, I2C_CON_STOP_DET_IF_ADDRESSED);
578 }
579
580 /**
581 * @brief Check if Slave issues STOP_DET interrupt only if addressed function is enabled or disabled.
582 *
583 * Register|BitsName
584 * --------|--------
585 * IC_CON | STOP_DET_IF_ADDRESSED
586 *
587 * @param I2Cx I2C instance.
588 * @retval State of bit (1 or 0).
589 */
ll_i2c_is_enabled_stop_det_if_addressed(i2c_regs_t * I2Cx)590 __STATIC_INLINE uint32_t ll_i2c_is_enabled_stop_det_if_addressed(i2c_regs_t *I2Cx)
591 {
592 return (READ_BITS(I2Cx->CON, I2C_CON_STOP_DET_IF_ADDRESSED) == (I2C_CON_STOP_DET_IF_ADDRESSED));
593 }
594
595 /**
596 * @brief Configure the Master to transfers in 7-bit or 10-bit addressing mode.
597 * @note The register IC_CON can only be programmed when the I2C is disabled (ENABLE = 0).
598 *
599 * Register|BitsName
600 * --------|--------
601 * IC_CON | CON_10BITADDR_MST
602 *
603 * @param I2Cx I2C instance.
604 * @param addressing_mode This parameter can be one of the following values:
605 * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
606 * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
607 * @retval None.
608 */
ll_i2c_set_master_addressing_mode(i2c_regs_t * I2Cx,uint32_t addressing_mode)609 __STATIC_INLINE void ll_i2c_set_master_addressing_mode(i2c_regs_t *I2Cx, uint32_t addressing_mode)
610 {
611 MODIFY_REG(I2Cx->CON, I2C_CON_10BITADDR_MST, addressing_mode);
612 }
613
614 /**
615 * @brief Get the Master addressing mode.
616 * @note The register IC_CON can only be programmed when the I2C is disabled (ENABLE = 0).
617 *
618 * Register|BitsName
619 * --------|--------
620 * IC_CON | CON_10BITADDR_MST
621 *
622 * @param I2Cx I2C instance.
623 * @retval Returned value can be one of the following values:
624 * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
625 * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
626 */
ll_i2c_get_master_addressing_mode(i2c_regs_t * I2Cx)627 __STATIC_INLINE uint32_t ll_i2c_get_master_addressing_mode(i2c_regs_t *I2Cx)
628 {
629 return (uint32_t)(READ_BITS(I2Cx->CON, I2C_CON_10BITADDR_MST));
630 }
631
632 /**
633 * @brief Set the Own Address.
634 * @note The register IC_CON and IC_SAR can only be programmed when the I2C is disabled (IC_ENABLE = 0).
635 *
636 * Register|BitsName
637 * --------|--------
638 * IC_CON | CON_10BITADDR_SLV
639 * IC_SAR | SAR
640 *
641 * @param I2Cx I2C instance.
642 * @param own_address This parameter must be a value range between 0 ~ 0x3FF(10-bit mode) or 0 ~ 0x7F(7-bit mode).
643 * Reserved address 0x00 to 0x07, or 0x78 to 0x7f should not be configured.
644 * @param own_addr_size This parameter can be one of the following values:
645 * @arg @ref LL_I2C_OWNADDRESS_7BIT
646 * @arg @ref LL_I2C_OWNADDRESS_10BIT
647 * @retval None.
648 */
ll_i2c_set_own_address(i2c_regs_t * I2Cx,uint32_t own_address,uint32_t own_addr_size)649 __STATIC_INLINE void ll_i2c_set_own_address(i2c_regs_t *I2Cx, uint32_t own_address, uint32_t own_addr_size)
650 {
651 MODIFY_REG(I2Cx->CON, I2C_CON_10BITADDR_SLV, own_addr_size);
652 WRITE_REG(I2Cx->SAR, own_address);
653 }
654
655 /**
656 * @brief Set the SCL clock high-period count for standard speed.
657 * @note The register IC_SS_SCL_HCNT can only be programmed when the I2C is disabled (ENABLE = 0).
658 *
659 * Register|BitsName
660 * --------|--------
661 * IC_SS_SCL_HCNT | SS_SCL_HCNT
662 *
663 * @param I2Cx I2C instance.
664 * @param count This parameter must be a value range between 6 ~ 0xFFF5.
665 * @retval None.
666 */
ll_i2c_set_clock_high_period_ss(i2c_regs_t * I2Cx,uint32_t count)667 __STATIC_INLINE void ll_i2c_set_clock_high_period_ss(i2c_regs_t *I2Cx, uint32_t count)
668 {
669 WRITE_REG(I2Cx->SS_SCL_HCNT, count);
670 }
671
672 /**
673 * @brief Get the SCL clock high-period count for standard speed.
674 *
675 * Register|BitsName
676 * --------|--------
677 * IC_SS_SCL_HCNT | SS_SCL_HCNT
678 *
679 * @param I2Cx I2C instance.
680 * @retval Value range between 0x6 and 0xFFF5.
681 */
ll_i2c_get_clock_high_period_ss(i2c_regs_t * I2Cx)682 __STATIC_INLINE uint32_t ll_i2c_get_clock_high_period_ss(i2c_regs_t *I2Cx)
683 {
684 return (uint32_t)(READ_BITS(I2Cx->SS_SCL_HCNT, I2C_SS_SCL_HCNT));
685 }
686
687 /**
688 * @brief Set the SCL clock low-period count for standard speed.
689 * @note The register IC_SS_SCL_LCNT can only be programmed when the I2C is disabled (ENABLE = 0).
690 *
691 * Register|BitsName
692 * --------|--------
693 * IC_SS_SCL_LCNT | SS_SCL_LCNT
694 *
695 * @param I2Cx I2C instance.
696 * @param count This parameter must be a value range between 0x8 and 0xFFFF.
697 * @retval None.
698 */
ll_i2c_set_clock_low_period_ss(i2c_regs_t * I2Cx,uint32_t count)699 __STATIC_INLINE void ll_i2c_set_clock_low_period_ss(i2c_regs_t *I2Cx, uint32_t count)
700 {
701 WRITE_REG(I2Cx->SS_SCL_LCNT, count);
702 }
703
704 /**
705 * @brief Get the SCL clock low-period count for standard speed.
706 *
707 * Register|BitsName
708 * --------|--------
709 * IC_SS_SCL_LCNT | SS_SCL_LCNT
710 *
711 * @param I2Cx I2C instance.
712 * @retval Value range between 0x8 and 0xFFFF.
713 */
ll_i2c_get_clock_low_period_ss(i2c_regs_t * I2Cx)714 __STATIC_INLINE uint32_t ll_i2c_get_clock_low_period_ss(i2c_regs_t *I2Cx)
715 {
716 return (uint32_t)(READ_BITS(I2Cx->SS_SCL_LCNT, I2C_SS_SCL_LCNT));
717 }
718
719 /**
720 * @brief Set the SCL clock high-period count for fast speed.
721 * @note The register IC_FS_SCL_HCNT can only be programmed when the I2C is disabled (ENABLE = 0).
722 *
723 * Register|BitsName
724 * --------|--------
725 * IC_FS_SCL_HCNT | FS_SCL_HCNT
726 *
727 * @param I2Cx I2C instance.
728 * @param count range between 0x6 and 0xFFFF.
729 * @retval None.
730 */
ll_i2c_set_clock_high_period_fs(i2c_regs_t * I2Cx,uint32_t count)731 __STATIC_INLINE void ll_i2c_set_clock_high_period_fs(i2c_regs_t *I2Cx, uint32_t count)
732 {
733 WRITE_REG(I2Cx->FS_SCL_HCNT, count);
734 }
735
736 /**
737 * @brief Get the SCL clock high-period count for fast speed.
738 *
739 * Register|BitsName
740 * --------|--------
741 * IC_FS_SCL_HCNT | FS_SCL_HCNT
742 *
743 * @param I2Cx I2C instance.
744 * @retval Value range between 0x6 and 0xFFFF.
745 */
ll_i2c_get_clock_high_period_fs(i2c_regs_t * I2Cx)746 __STATIC_INLINE uint32_t ll_i2c_get_clock_high_period_fs(i2c_regs_t *I2Cx)
747 {
748 return (uint32_t)(READ_BITS(I2Cx->FS_SCL_HCNT, I2C_FS_SCL_HCNT));
749 }
750
751 /**
752 * @brief Set the SCL clock low-period count for fast speed.
753 * @note The register IC_FS_SCL_LCNT can only be programmed when the I2C is disabled (ENABLE = 0).
754 *
755 * Register|BitsName
756 * --------|--------
757 * IC_FS_SCL_LCNT | FS_SCL_LCNT
758 *
759 * @param I2Cx I2C instance.
760 * @param count range between 0x8 and 0xFFFF
761 * @retval None.
762 */
ll_i2c_set_clock_low_period_fs(i2c_regs_t * I2Cx,uint32_t count)763 __STATIC_INLINE void ll_i2c_set_clock_low_period_fs(i2c_regs_t *I2Cx, uint32_t count)
764 {
765 WRITE_REG(I2Cx->FS_SCL_LCNT, count);
766 }
767
768 /**
769 * @brief Get the SCL clock low-period count for fast speed.
770 *
771 * Register|BitsName
772 * --------|--------
773 * IC_FS_SCL_LCNT | FS_SCL_LCNT
774 *
775 * @param I2Cx I2C instance.
776 * @retval Value range between 0x8 and 0xFFFF.
777 */
ll_i2c_get_clock_low_period_fs(i2c_regs_t * I2Cx)778 __STATIC_INLINE uint32_t ll_i2c_get_clock_low_period_fs(i2c_regs_t *I2Cx)
779 {
780 return (uint32_t)(READ_BITS(I2Cx->FS_SCL_LCNT, I2C_FS_SCL_LCNT));
781 }
782
783 /**
784 * @brief Get the SCL clock high-period count for high speed.
785 * @note The register IC_HS_SCL_HCNT can only be programmed when the I2C is disabled (ENABLE = 0).
786 *
787 * Register|BitsName
788 * --------|--------
789 * IC_HS_SCL_HCNT | HS_SCL_HCNT
790 *
791 * @param I2Cx I2C instance.
792 * @param count range between 0x6 and 0xFFFF, should be larger than IC_HS_SPKLEN + 5.
793 * @retval None.
794 */
ll_i2c_set_clock_high_period_hs(i2c_regs_t * I2Cx,uint32_t count)795 __STATIC_INLINE void ll_i2c_set_clock_high_period_hs(i2c_regs_t *I2Cx, uint32_t count)
796 {
797 WRITE_REG(I2Cx->HS_SCL_HCNT, count);
798 }
799
800 /**
801 * @brief Get the SCL clock high-period count for high speed.
802 *
803 * Register|BitsName
804 * --------|--------
805 * IC_HS_SCL_HCNT | HS_SCL_HCNT
806 *
807 * @param I2Cx I2C instance.
808 * @retval range between 0x6 and 0xFFFF, should be larger than IC_HS_SPKLEN + 7.
809 */
ll_i2c_get_clock_high_period_hs(i2c_regs_t * I2Cx)810 __STATIC_INLINE uint32_t ll_i2c_get_clock_high_period_hs(i2c_regs_t *I2Cx)
811 {
812 return (uint32_t)(READ_BITS(I2Cx->HS_SCL_HCNT, I2C_HS_SCL_HCNT));
813 }
814
815 /**
816 * @brief Get the SCL clock low-period count for high speed.
817 * @note The register IC_HS_SCL_LCNT can only be programmed when the I2C is disabled (ENABLE = 0).
818 *
819 * Register|BitsName
820 * --------|--------
821 * IC_HS_SCL_LCNT | HS_SCL_LCNT
822 *
823 * @param I2Cx I2C instance.
824 * @param count range between 0x8 and 0xFFFF
825 * @retval None.
826 */
ll_i2c_set_clock_low_period_hs(i2c_regs_t * I2Cx,uint32_t count)827 __STATIC_INLINE void ll_i2c_set_clock_low_period_hs(i2c_regs_t *I2Cx, uint32_t count)
828 {
829 WRITE_REG(I2Cx->HS_SCL_LCNT, count);
830 }
831
832 /**
833 * @brief Get the SCL clock low-period count for high speed.
834 *
835 * Register|BitsName
836 * --------|--------
837 * IC_HS_SCL_LCNT | HS_SCL_LCNT
838 *
839 * @param I2Cx I2C instance.
840 * @retval Value range between 0x8 and 0xFFFF
841 */
ll_i2c_get_clock_low_period_hs(i2c_regs_t * I2Cx)842 __STATIC_INLINE uint32_t ll_i2c_get_clock_low_period_hs(i2c_regs_t *I2Cx)
843 {
844 return (uint32_t)(READ_BITS(I2Cx->HS_SCL_LCNT, I2C_HS_SCL_LCNT));
845 }
846
847 /**
848 * @brief Set the spike len in fast speed mode.
849 * @note The register FS_SPKLEN can only be programmed when the I2C is disabled (ENABLE = 0).
850 *
851 * Register|BitsName
852 * --------|--------
853 * IC_FS_SPKLEN | FS_SPKLEN
854 *
855 * @param I2Cx I2C instance.
856 * @param length Spike len.
857 * @retval None.
858 */
ll_i2c_set_spike_len_fs(i2c_regs_t * I2Cx,uint32_t length)859 __STATIC_INLINE void ll_i2c_set_spike_len_fs(i2c_regs_t *I2Cx, uint32_t length)
860 {
861 MODIFY_REG(I2Cx->FS_SPKLEN, I2C_FS_SPKLEN_FS_SPKLEN, length);
862 }
863
864 /**
865 * @brief Get the spike len in fast speed mode.
866 *
867 * Register|BitsName
868 * --------|--------
869 * IC_FS_SPKLEN | FS_SPKLEN
870 *
871 * @param I2Cx I2C instance.
872 * @retval Value range between 0x2 and 0xFF.
873 */
ll_i2c_get_spike_len_fs(i2c_regs_t * I2Cx)874 __STATIC_INLINE uint32_t ll_i2c_get_spike_len_fs(i2c_regs_t *I2Cx)
875 {
876 return (uint32_t)(READ_BITS(I2Cx->FS_SPKLEN, I2C_FS_SPKLEN_FS_SPKLEN));
877 }
878
879 /**
880 * @brief Set the spike len in high speed mode.
881 * @note The register FS_SPKLEN can only be programmed when the I2C is disabled (ENABLE = 0).
882 *
883 * Register|BitsName
884 * --------|--------
885 * IC_HS_SPKLEN | HS_SPKLEN
886 *
887 * @param I2Cx I2C instance.
888 * @param length Spike len.
889 * @retval None.
890 */
ll_i2c_set_spike_len_hs(i2c_regs_t * I2Cx,uint32_t length)891 __STATIC_INLINE void ll_i2c_set_spike_len_hs(i2c_regs_t *I2Cx, uint32_t length)
892 {
893 MODIFY_REG(I2Cx->HS_SPKLEN, I2C_HS_SPKLEN_HS_SPKLEN, length);
894 }
895
896 /**
897 * @brief Get the spike len in high speed mode.
898 *
899 * Register|BitsName
900 * --------|--------
901 * IC_HS_SPKLEN | HS_SPKLEN
902 *
903 * @param I2Cx I2C instance.
904 * @retval Value range between 0x2 and 0xFF.
905 */
ll_i2c_get_spike_len_hs(i2c_regs_t * I2Cx)906 __STATIC_INLINE uint32_t ll_i2c_get_spike_len_hs(i2c_regs_t *I2Cx)
907 {
908 return (uint32_t)(READ_BITS(I2Cx->HS_SPKLEN, I2C_HS_SPKLEN_HS_SPKLEN));
909 }
910
911 /**
912 * @brief Set I2C Speed mode.
913 * @note The register IC_CON can only be programmed when the I2C is disabled (ENABLE = 0).
914 *
915 * Register|BitsName
916 * --------|--------
917 * IC_CON | SPEED
918 *
919 * @param I2Cx I2C instance.
920 * @param speed_mode This parameter can be one of the following values:
921 * @arg @ref LL_I2C_SPEED_MODE_STANDARD
922 * @arg @ref LL_I2C_SPEED_MODE_FAST
923 * @arg @ref LL_I2C_SPEED_MODE_HIGH
924 * @retval None.
925 */
ll_i2c_set_speed_mode(i2c_regs_t * I2Cx,uint32_t speed_mode)926 __STATIC_INLINE void ll_i2c_set_speed_mode(i2c_regs_t *I2Cx, uint32_t speed_mode)
927 {
928 MODIFY_REG(I2Cx->CON, I2C_CON_SPEED, speed_mode);
929 }
930
931 /**
932 * @brief Get I2C Speed mode.
933 *
934 * Register|BitsName
935 * --------|--------
936 * IC_CON | SPEED
937 *
938 * @param I2Cx I2C instance.
939 * @retval Value can be one of the following values:
940 * @arg @ref LL_I2C_SPEED_MODE_STANDARD
941 * @arg @ref LL_I2C_SPEED_MODE_FAST
942 * @arg @ref LL_I2C_SPEED_MODE_HIGH
943 */
ll_i2c_get_speed_mode(i2c_regs_t * I2Cx)944 __STATIC_INLINE uint32_t ll_i2c_get_speed_mode(i2c_regs_t *I2Cx)
945 {
946 return (uint32_t)(READ_BITS(I2Cx->CON, I2C_CON_SPEED));
947 }
948
949 /**
950 * @brief Set I2C High Speed Master Code Address.
951 * @note The register IC_CON can only be programmed when the I2C is disabled (ENABLE = 0).
952 *
953 * Register|BitsName
954 * --------|--------
955 * IC_HS_MADDR | HS_MAR
956 *
957 * @param I2Cx I2C instance.
958 * @param code HS mode master code, range between 0x00 and 0x07.
959 * @retval None.
960 */
ll_i2c_set_high_speed_master_code(i2c_regs_t * I2Cx,uint32_t code)961 __STATIC_INLINE void ll_i2c_set_high_speed_master_code(i2c_regs_t *I2Cx, uint32_t code)
962 {
963 WRITE_REG(I2Cx->HS_MADDR, code);
964 }
965
966 /**
967 * @brief Get I2C Speed mode.
968 *
969 * Register|BitsName
970 * --------|--------
971 * IC_HS_MADDR | HS_MAR
972 *
973 * @param I2Cx I2C instance.
974 * @retval Returned value range between 0x00 and 0x07.
975 */
ll_i2c_get_high_speed_master_code(i2c_regs_t * I2Cx)976 __STATIC_INLINE uint32_t ll_i2c_get_high_speed_master_code(i2c_regs_t *I2Cx)
977 {
978 return (uint32_t)(READ_BITS(I2Cx->HS_MADDR, I2C_HS_MADDR_HS_MAR));
979 }
980
981 /**
982 * @brief Set the required transmit SDA hold time in units of ic_clk period.
983 * @note The register IC_SDA_HOLD can only be programmed when the I2C is disabled (ENABLE = 0).
984 *
985 * Register|BitsName
986 * --------|--------
987 * IC_SDA_HOLD | TX_HOLD
988 *
989 * @param I2Cx I2C instance.
990 * @param time SDA Tx hold time in units of ic_clk period.
991 * Time should range between 1 and (N_SCL_LOW - 2) in master mode or 7 and (N_SCL_LOW - 2) in slave mode.
992 * @retval None.
993 */
ll_i2c_set_data_tx_hold_time(i2c_regs_t * I2Cx,uint32_t time)994 __STATIC_INLINE void ll_i2c_set_data_tx_hold_time(i2c_regs_t *I2Cx, uint32_t time)
995 {
996 MODIFY_REG(I2Cx->SDA_HOLD, I2C_SDA_HOLD_TX_HOLD, time << I2C_SDA_HOLD_TX_HOLD_Pos);
997 }
998
999 /**
1000 * @brief Get the required transmit SDA hold time in units of ic_clk period.
1001 *
1002 * Register|BitsName
1003 * --------|--------
1004 * IC_SDA_HOLD | TX_HOLD
1005 *
1006 * @param I2Cx I2C instance.
1007 * @retval Value range between 1 and (N_SCL_LOW - 2) in master mode or 7 and (N_SCL_LOW - 2) in slave mode
1008 */
ll_i2c_get_data_tx_hold_time(i2c_regs_t * I2Cx)1009 __STATIC_INLINE uint32_t ll_i2c_get_data_tx_hold_time(i2c_regs_t *I2Cx)
1010 {
1011 return (uint32_t)(READ_BITS(I2Cx->SDA_HOLD, I2C_SDA_HOLD_TX_HOLD) >> I2C_SDA_HOLD_TX_HOLD_Pos);
1012 }
1013
1014 /**
1015 * @brief Set the required receive SDA hold time in units of ic_clk period.
1016 * @note The register IC_SDA_HOLD can only be programmed when the I2C is disabled (ENABLE = 0).
1017 *
1018 * Register|BitsName
1019 * --------|--------
1020 * IC_SDA_HOLD | RX_HOLD
1021 *
1022 * @param I2Cx I2C instance.
1023 * @param time SDA Tx hold time in units of ic_clk period.
1024 * Time should range between 1 and (N_SCL_LOW - 2) in master mode or 7 and (N_SCL_LOW - 2) in slave mode.
1025 * @retval Value between Min_Data=0x0 and Max_Data=0xF
1026 */
ll_i2c_set_data_rx_hold_time(i2c_regs_t * I2Cx,uint32_t time)1027 __STATIC_INLINE void ll_i2c_set_data_rx_hold_time(i2c_regs_t *I2Cx, uint32_t time)
1028 {
1029 MODIFY_REG(I2Cx->SDA_HOLD, I2C_SDA_HOLD_RX_HOLD, time << I2C_SDA_HOLD_RX_HOLD_Pos);
1030 }
1031
1032 /**
1033 * @brief Get the required receive SDA hold time in units of ic_clk period.
1034 *
1035 * Register|BitsName
1036 * --------|--------
1037 * IC_SDA_HOLD | RX_HOLD
1038 *
1039 * @param I2Cx I2C instance.
1040 * @retval Value range between 1 and (N_SCL_LOW - 2) in master mode or 7 and (N_SCL_LOW - 2) in slave mode
1041 */
ll_i2c_get_data_rx_hold_time(i2c_regs_t * I2Cx)1042 __STATIC_INLINE uint32_t ll_i2c_get_data_rx_hold_time(i2c_regs_t *I2Cx)
1043 {
1044 return (uint32_t)(READ_BITS(I2Cx->SDA_HOLD, I2C_SDA_HOLD_RX_HOLD) >> I2C_SDA_HOLD_RX_HOLD_Pos);
1045 }
1046
1047 /**
1048 * @brief Set the SDA setup time when operating as a slave transmitter.
1049 * @note The register IC_SDA_SETUP can only be programmed when the I2C is disabled (ENABLE = 0).
1050 * The length of setup time is calculated using [(IC_SDA_SETUP - 1) * (ic_clk_period)], so if the
1051 * user requires 10 ic_clk periods of setup time, they should program a value of 11.
1052 *
1053 * Register|BitsName
1054 * --------|--------
1055 * IC_SDA_SETUP | SDA_SETUP
1056 *
1057 * @param I2Cx I2C instance.
1058 * @param time SDA data setup time in units of ic_clk period, range between 2 ~ 0xFF.
1059 * @retval None.
1060 */
ll_i2c_set_data_setup_time(i2c_regs_t * I2Cx,uint32_t time)1061 __STATIC_INLINE void ll_i2c_set_data_setup_time(i2c_regs_t *I2Cx, uint32_t time)
1062 {
1063 MODIFY_REG(I2Cx->SDA_SETUP, I2C_SDA_SETUP_SDA_SETUP, time);
1064 }
1065
1066 /**
1067 * @brief Get the SDA setup time when operating as a slave transmitter.
1068 *
1069 * Register|BitsName
1070 * --------|--------
1071 * IC_SDA_SETUP | SDA_SETUP
1072 *
1073 * @param I2Cx I2C instance.
1074 * @retval Value range between 0x02 and 0xFF.
1075 */
ll_i2c_get_data_setup_time(i2c_regs_t * I2Cx)1076 __STATIC_INLINE uint32_t ll_i2c_get_data_setup_time(i2c_regs_t *I2Cx)
1077 {
1078 return (uint32_t)(READ_BITS(I2Cx->SDA_SETUP, I2C_SDA_SETUP_SDA_SETUP));
1079 }
1080
1081 /**
1082 * @brief Set threshold of entries (or below) that trigger the TX_EMPTY interrupt
1083 * @note TX FIFO threshold only can be configured after FIFO was enabled.
1084 *
1085 * Register|BitsName
1086 * --------|--------
1087 * IC_TX_TL | TX_TL
1088 *
1089 * @param I2Cx I2C instance
1090 * @param threshold This parameter can be one of the following values:
1091 * @arg @ref LL_I2C_TX_FIFO_TH_EMPTY
1092 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_1
1093 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_2
1094 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_3
1095 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_4
1096 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_5
1097 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_6
1098 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_7
1099 * @retval None.
1100 */
ll_i2c_set_tx_fifo_threshold(i2c_regs_t * I2Cx,uint32_t threshold)1101 __STATIC_INLINE void ll_i2c_set_tx_fifo_threshold(i2c_regs_t *I2Cx, uint32_t threshold)
1102 {
1103 WRITE_REG(I2Cx->TX_TL, threshold);
1104 }
1105
1106 /**
1107 * @brief Get threshold of TX FIFO that triggers an THRE interrupt
1108 *
1109 * Register|BitsName
1110 * --------|--------
1111 * IC_TX_TL | TX_TL
1112 *
1113 * @param I2Cx I2C instance
1114 * @retval Returned value can be one of the following values:
1115 * @arg @ref LL_I2C_TX_FIFO_TH_EMPTY
1116 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_1
1117 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_2
1118 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_3
1119 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_4
1120 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_5
1121 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_6
1122 * @arg @ref LL_I2C_TX_FIFO_TH_CHAR_7
1123 */
ll_i2c_get_tx_fifo_threshold(i2c_regs_t * I2Cx)1124 __STATIC_INLINE uint32_t ll_i2c_get_tx_fifo_threshold(i2c_regs_t *I2Cx)
1125 {
1126 return (uint32_t)(READ_BITS(I2Cx->TX_TL, I2C_TX_TL_TXTL));
1127 }
1128
1129 /**
1130 * @brief Set threshold of RX FIFO that triggers an RDA interrupt
1131 * @note TX FIFO threshold only can be configured after FIFO was enabled.
1132 *
1133 * Register|BitsName
1134 * --------|--------
1135 * IC_RX_TL | RX_TL
1136 *
1137 * @param I2Cx I2C instance
1138 * @param threshold This parameter can be one of the following values:
1139 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_1
1140 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_2
1141 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_3
1142 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_4
1143 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_5
1144 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_6
1145 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_7
1146 * @arg @ref LL_I2C_RX_FIFO_TH_FULL
1147 * @retval None.
1148 */
ll_i2c_set_rx_fifo_threshold(i2c_regs_t * I2Cx,uint32_t threshold)1149 __STATIC_INLINE void ll_i2c_set_rx_fifo_threshold(i2c_regs_t *I2Cx, uint32_t threshold)
1150 {
1151 WRITE_REG(I2Cx->RX_TL, threshold);
1152 }
1153
1154 /**
1155 * @brief Get threshold of RX FIFO that triggers an RDA interrupt
1156 *
1157 * Register|BitsName
1158 * --------|--------
1159 * IC_RX_TL | RX_TL
1160 *
1161 * @param I2Cx I2C instance
1162 * @retval Returned value can be one of the following values:
1163 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_1
1164 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_2
1165 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_3
1166 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_4
1167 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_5
1168 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_6
1169 * @arg @ref LL_I2C_RX_FIFO_TH_CHAR_7
1170 * @arg @ref LL_I2C_RX_FIFO_TH_FULL
1171 */
ll_i2c_get_rx_fifo_threshold(i2c_regs_t * I2Cx)1172 __STATIC_INLINE uint32_t ll_i2c_get_rx_fifo_threshold(i2c_regs_t *I2Cx)
1173 {
1174 return (uint32_t)(READ_BITS(I2Cx->RX_TL, I2C_RX_TL_RXTL));
1175 }
1176
1177 /**
1178 * @brief Get FIFO Transmission Level
1179 *
1180 * Register|BitsName
1181 * --------|--------
1182 * IC_TXFLR | TXFLR
1183 *
1184 * @param I2Cx I2C instance
1185 * @retval Value range between 0x0 and 0x8.
1186 */
ll_i2c_get_tx_fifo_level(i2c_regs_t * I2Cx)1187 __STATIC_INLINE uint32_t ll_i2c_get_tx_fifo_level(i2c_regs_t *I2Cx)
1188 {
1189 return (uint32_t)(READ_BITS(I2Cx->TXFLR, I2C_TXFLR_TXFLR));
1190 }
1191
1192 /**
1193 * @brief Get FIFO reception Level
1194 *
1195 * Register|BitsName
1196 * --------|--------
1197 * IC_RXFLR | RXFLR
1198 *
1199 * @param I2Cx I2C instance
1200 * @retval Value range between 0x0 and 0x8.
1201 */
ll_i2c_get_rx_fifo_level(i2c_regs_t * I2Cx)1202 __STATIC_INLINE uint32_t ll_i2c_get_rx_fifo_level(i2c_regs_t *I2Cx)
1203 {
1204 return (uint32_t)(READ_BITS(I2Cx->RXFLR, I2C_RXFLR_RXFLR));
1205 }
1206
1207 /**
1208 * @brief Enable DMA reception requests.
1209 *
1210 * Register|BitsName
1211 * --------|--------
1212 * IC_ENABLE | ABORT
1213 *
1214 * @param I2Cx I2C instance.
1215 * @retval None.
1216 */
ll_i2c_enable_transfer_abort(i2c_regs_t * I2Cx)1217 __STATIC_INLINE void ll_i2c_enable_transfer_abort(i2c_regs_t *I2Cx)
1218 {
1219 SET_BITS(I2Cx->ENABLE, I2C_ENABLE_ABORT);
1220 }
1221
1222 /**
1223 * @brief Check if DMA reception requests are enabled or disabled.
1224 *
1225 * Register|BitsName
1226 * --------|--------
1227 * IC_ENABLE | ABORT
1228 *
1229 * @param I2Cx I2C instance.
1230 * @retval State of bit (1 or 0).
1231 */
ll_i2c_is_enabled_transfer_abort(i2c_regs_t * I2Cx)1232 __STATIC_INLINE uint32_t ll_i2c_is_enabled_transfer_abort(i2c_regs_t *I2Cx)
1233 {
1234 return (READ_BITS(I2Cx->ENABLE, I2C_ENABLE_ABORT) == (I2C_ENABLE_ABORT));
1235 }
1236
1237 /**
1238 * @brief Get the transmit abort source.
1239 * @note This can be used to retrieve source of TX_ABRT interrupt.
1240 *
1241 * Register|BitsName
1242 * --------|--------
1243 * IC_TX_ABRT_SOURCE | ABRT_USER_ABRT
1244 * IC_TX_ABRT_SOURCE | ABRT_SLVRD_INTX
1245 * IC_TX_ABRT_SOURCE | ABRT_SLV_ARBLOST
1246 * IC_TX_ABRT_SOURCE | ABRT_SLVFLUSH_TXFIFO
1247 * IC_TX_ABRT_SOURCE | ABRT_ARB_LOST
1248 * IC_TX_ABRT_SOURCE | ABRT_MST_DIS
1249 * IC_TX_ABRT_SOURCE | ABRT_10B_RD_NORSTRT
1250 * IC_TX_ABRT_SOURCE | ABRT_SBYTE_NORSTRT
1251 * IC_TX_ABRT_SOURCE | ABRT_HS_NORSTRT
1252 * IC_TX_ABRT_SOURCE | ABRT_SBYTE_ACKDET
1253 * IC_TX_ABRT_SOURCE | ABRT_HS_ACKDET
1254 * IC_TX_ABRT_SOURCE | ABRT_GCALL_READ
1255 * IC_TX_ABRT_SOURCE | ABRT_GCALL_NOACK
1256 * IC_TX_ABRT_SOURCE | ABRT_TXDATA_NOACK
1257 * IC_TX_ABRT_SOURCE | ABRT_10ADDR2_NOACK
1258 * IC_TX_ABRT_SOURCE | ABRT_10ADDR1_NOACK
1259 * IC_TX_ABRT_SOURCE | ABRT_7B_ADDR_NOACK
1260 *
1261 * @param I2Cx I2C instance
1262 * @retval Returned value can be a combination of the following values:
1263 * @arg @ref LL_I2C_ABRT_USER_ABRT
1264 * @arg @ref LL_I2C_ABRT_SLVRD_INTX
1265 * @arg @ref LL_I2C_ABRT_SLV_ARBLOST
1266 * @arg @ref LL_I2C_ABRT_SLVFLUSH_TXFIFO
1267 * @arg @ref LL_I2C_ABRT_ARB_LOST
1268 * @arg @ref LL_I2C_ABRT_MST_DIS
1269 * @arg @ref LL_I2C_ABRT_10B_RD_NORSTRT
1270 * @arg @ref LL_I2C_ABRT_SBYTE_NORSTRT
1271 * @arg @ref LL_I2C_ABRT_HS_NORSTRT
1272 * @arg @ref LL_I2C_ABRT_SBYTE_ACKDET
1273 * @arg @ref LL_I2C_ABRT_HS_ACKDET
1274 * @arg @ref LL_I2C_ABRT_GCALL_READ
1275 * @arg @ref LL_I2C_ABRT_GCALL_NOACK
1276 * @arg @ref LL_I2C_ABRT_TXDATA_NOACK
1277 * @arg @ref LL_I2C_ABRT_10ADDR2_NOACK
1278 * @arg @ref LL_I2C_ABRT_10ADDR1_NOACK
1279 * @arg @ref LL_I2C_ABRT_7B_ADDR_NOACK
1280 *
1281 * @note @arg @ref LL_I2C_ABRT_TX_FLUSH_CNT can be used as a mask to get the
1282 * number of Tx FIFO Data Commands which are flushed due to TX_ABRT
1283 * interrupt.
1284 */
ll_i2c_get_abort_source(i2c_regs_t * I2Cx)1285 __STATIC_INLINE uint32_t ll_i2c_get_abort_source(i2c_regs_t *I2Cx)
1286 {
1287 return (uint32_t)(READ_REG(I2Cx->TX_ABRT_SOURCE) & (~I2C_TX_ABRT_SRC_TX_FLUSH_CNT));
1288 }
1289
1290 /**
1291 * @brief Get the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt.
1292 *
1293 * Register|BitsName
1294 * --------|--------
1295 * IC_TX_ABRT_SOURCE | TX_FLUSH_CNT
1296 *
1297 * @param I2Cx I2C instance
1298 * @retval Tx flush count.
1299 */
ll_i2c_get_tx_flush_count(i2c_regs_t * I2Cx)1300 __STATIC_INLINE uint32_t ll_i2c_get_tx_flush_count(i2c_regs_t *I2Cx)
1301 {
1302 return (uint32_t)(READ_BITS(I2Cx->TX_ABRT_SOURCE, I2C_TX_ABRT_SRC_TX_FLUSH_CNT) >> \
1303 I2C_TX_ABRT_SRC_TX_FLUSH_CNT_Pos);
1304 }
1305
1306 /** @} */
1307
1308 /** @defgroup I2C_LL_EF_IT_Management IT_Management
1309 * @{
1310 */
1311
1312 /**
1313 * @brief Enable specified interrupts.
1314 *
1315 * Register|BitsName
1316 * --------|--------
1317 * INTR_MASK | INTR_MASK_GEN_CALL
1318 * INTR_MASK | INTR_MASK_START_DET
1319 * INTR_MASK | INTR_MASK_STOP_DET
1320 * INTR_MASK | INTR_MASK_ACTIVITY
1321 * INTR_MASK | INTR_MASK_RX_DONE
1322 * INTR_MASK | INTR_MASK_TX_ABRT
1323 * INTR_MASK | INTR_MASK_RD_REQ
1324 * INTR_MASK | INTR_MASK_TX_EMPTY
1325 * INTR_MASK | INTR_MASK_TX_OVER
1326 * INTR_MASK | INTR_MASK_RX_FULL
1327 * INTR_MASK | INTR_MASK_RX_OVER
1328 * INTR_MASK | INTR_MASK_RX_UNDER
1329 *
1330 * @param I2Cx I2C instance.
1331 * @param mask This parameter can be a combination of the following values:
1332 * @arg @ref LL_I2C_INTR_MASK_GEN_CALL
1333 * @arg @ref LL_I2C_INTR_MASK_START_DET
1334 * @arg @ref LL_I2C_INTR_MASK_STOP_DET
1335 * @arg @ref LL_I2C_INTR_MASK_ACTIVITY
1336 * @arg @ref LL_I2C_INTR_MASK_RX_DONE
1337 * @arg @ref LL_I2C_INTR_MASK_TX_ABRT
1338 * @arg @ref LL_I2C_INTR_MASK_RD_REQ
1339 * @arg @ref LL_I2C_INTR_MASK_TX_EMPTY
1340 * @arg @ref LL_I2C_INTR_MASK_TX_OVER
1341 * @arg @ref LL_I2C_INTR_MASK_RX_FULL
1342 * @arg @ref LL_I2C_INTR_MASK_RX_OVER
1343 * @arg @ref LL_I2C_INTR_MASK_RX_UNDER
1344 * @retval None.
1345 */
ll_i2c_enable_it(i2c_regs_t * I2Cx,uint32_t mask)1346 __STATIC_INLINE void ll_i2c_enable_it(i2c_regs_t *I2Cx, uint32_t mask)
1347 {
1348 SET_BITS(I2Cx->INTR_MASK, mask);
1349 }
1350
1351 /**
1352 * @brief Disable specified interrupts.
1353 *
1354 * Register|BitsName
1355 * --------|--------
1356 * INTR_MASK | INTR_MASK_GEN_CALL
1357 * INTR_MASK | INTR_MASK_START_DET
1358 * INTR_MASK | INTR_MASK_STOP_DET
1359 * INTR_MASK | INTR_MASK_ACTIVITY
1360 * INTR_MASK | INTR_MASK_RX_DONE
1361 * INTR_MASK | INTR_MASK_TX_ABRT
1362 * INTR_MASK | INTR_MASK_RD_REQ
1363 * INTR_MASK | INTR_MASK_TX_EMPTY
1364 * INTR_MASK | INTR_MASK_TX_OVER
1365 * INTR_MASK | INTR_MASK_RX_FULL
1366 * INTR_MASK | INTR_MASK_RX_OVER
1367 * INTR_MASK | INTR_MASK_RX_UNDER
1368 *
1369 * @param I2Cx I2C instance.
1370 * @param mask This parameter can be a combination of the following values:
1371 * @arg @ref LL_I2C_INTR_MASK_GEN_CALL
1372 * @arg @ref LL_I2C_INTR_MASK_START_DET
1373 * @arg @ref LL_I2C_INTR_MASK_STOP_DET
1374 * @arg @ref LL_I2C_INTR_MASK_ACTIVITY
1375 * @arg @ref LL_I2C_INTR_MASK_RX_DONE
1376 * @arg @ref LL_I2C_INTR_MASK_TX_ABRT
1377 * @arg @ref LL_I2C_INTR_MASK_RD_REQ
1378 * @arg @ref LL_I2C_INTR_MASK_TX_EMPTY
1379 * @arg @ref LL_I2C_INTR_MASK_TX_OVER
1380 * @arg @ref LL_I2C_INTR_MASK_RX_FULL
1381 * @arg @ref LL_I2C_INTR_MASK_RX_OVER
1382 * @arg @ref LL_I2C_INTR_MASK_RX_UNDER
1383 * @retval None.
1384 */
ll_i2c_disable_it(i2c_regs_t * I2Cx,uint32_t mask)1385 __STATIC_INLINE void ll_i2c_disable_it(i2c_regs_t *I2Cx, uint32_t mask)
1386 {
1387 CLEAR_BITS(I2Cx->INTR_MASK, mask);
1388 }
1389
1390 /**
1391 * @brief Check if the specified interrupts are enabled or disabled.
1392 *
1393 * Register|BitsName
1394 * --------|--------
1395 * INTR_MASK | INTR_MASK_GEN_CALL
1396 * INTR_MASK | INTR_MASK_START_DET
1397 * INTR_MASK | INTR_MASK_STOP_DET
1398 * INTR_MASK | INTR_MASK_ACTIVITY
1399 * INTR_MASK | INTR_MASK_RX_DONE
1400 * INTR_MASK | INTR_MASK_TX_ABRT
1401 * INTR_MASK | INTR_MASK_RD_REQ
1402 * INTR_MASK | INTR_MASK_TX_EMPTY
1403 * INTR_MASK | INTR_MASK_TX_OVER
1404 * INTR_MASK | INTR_MASK_RX_FULL
1405 * INTR_MASK | INTR_MASK_RX_OVER
1406 * INTR_MASK | INTR_MASK_RX_UNDER
1407 *
1408 * @param I2Cx I2C instance.
1409 * @param mask This parameter can be a combination of the following values:
1410 * @arg @ref LL_I2C_INTR_MASK_GEN_CALL
1411 * @arg @ref LL_I2C_INTR_MASK_START_DET
1412 * @arg @ref LL_I2C_INTR_MASK_STOP_DET
1413 * @arg @ref LL_I2C_INTR_MASK_ACTIVITY
1414 * @arg @ref LL_I2C_INTR_MASK_RX_DONE
1415 * @arg @ref LL_I2C_INTR_MASK_TX_ABRT
1416 * @arg @ref LL_I2C_INTR_MASK_RD_REQ
1417 * @arg @ref LL_I2C_INTR_MASK_TX_EMPTY
1418 * @arg @ref LL_I2C_INTR_MASK_TX_OVER
1419 * @arg @ref LL_I2C_INTR_MASK_RX_FULL
1420 * @arg @ref LL_I2C_INTR_MASK_RX_OVER
1421 * @arg @ref LL_I2C_INTR_MASK_RX_UNDER
1422 * @retval State of bit (1 or 0).
1423 */
ll_i2c_is_enabled_it(i2c_regs_t * I2Cx,uint32_t mask)1424 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it(i2c_regs_t *I2Cx, uint32_t mask)
1425 {
1426 return (READ_BITS(I2Cx->INTR_MASK, mask) == (mask));
1427 }
1428
1429 /**
1430 * @brief Enable MASTER_ON_HOLD interrupt.
1431 *
1432 * Register|BitsName
1433 * --------|--------
1434 * INTR_MASK | MST_ON_HOLD
1435 *
1436 * @param I2Cx I2C instance.
1437 * @retval None.
1438 */
ll_i2c_enable_it_master_on_hold(i2c_regs_t * I2Cx)1439 __STATIC_INLINE void ll_i2c_enable_it_master_on_hold(i2c_regs_t *I2Cx)
1440 {
1441 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_MST_ON_HOLD);
1442 }
1443
1444 /**
1445 * @brief Disable MASTER_ON_HOLD interrupt.
1446 *
1447 * Register|BitsName
1448 * --------|--------
1449 * INTR_MASK | MST_ON_HOLD
1450 *
1451 * @param I2Cx I2C instance.
1452 * @retval None.
1453 */
ll_i2c_disable_it_master_om_hold(i2c_regs_t * I2Cx)1454 __STATIC_INLINE void ll_i2c_disable_it_master_om_hold(i2c_regs_t *I2Cx)
1455 {
1456 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_MST_ON_HOLD);
1457 }
1458
1459 /**
1460 * @brief Check if the MASTER_ON_HOLD Interrupt is enabled or disabled.
1461 *
1462 * Register|BitsName
1463 * --------|--------
1464 * INTR_MASK | MST_ON_HOLD
1465 *
1466 * @param I2Cx I2C instance.
1467 * @retval State of bit (1 or 0).
1468 */
ll_i2c_is_enabled_it_master_on_hold(i2c_regs_t * I2Cx)1469 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_master_on_hold(i2c_regs_t *I2Cx)
1470 {
1471 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_MST_ON_HOLD) == (I2C_INTR_MST_ON_HOLD));
1472 }
1473
1474 /**
1475 * @brief Enable RESTART_DET interrupt.
1476 *
1477 * Register|BitsName
1478 * --------|--------
1479 * INTR_MASK | RESTART_DET
1480 *
1481 * @param I2Cx I2C instance.
1482 * @retval None.
1483 */
ll_i2c_enable_it_restart_det(i2c_regs_t * I2Cx)1484 __STATIC_INLINE void ll_i2c_enable_it_restart_det(i2c_regs_t *I2Cx)
1485 {
1486 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_RESTART_DET);
1487 }
1488
1489 /**
1490 * @brief Disable RESTART_DET interrupt.
1491 *
1492 * Register|BitsName
1493 * --------|--------
1494 * INTR_MASK | RESTART_DET
1495 *
1496 * @param I2Cx I2C instance.
1497 * @retval None.
1498 */
ll_i2c_disable_it_restart_det(i2c_regs_t * I2Cx)1499 __STATIC_INLINE void ll_i2c_disable_it_restart_det(i2c_regs_t *I2Cx)
1500 {
1501 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_RESTART_DET);
1502 }
1503
1504 /**
1505 * @brief Check if the RESTART_DET Interrupt is enabled or disabled.
1506 *
1507 * Register|BitsName
1508 * --------|--------
1509 * INTR_MASK | RESTART_DET
1510 *
1511 * @param I2Cx I2C instance.
1512 * @retval State of bit (1 or 0).
1513 */
ll_i2c_is_enabled_it_restart_det(i2c_regs_t * I2Cx)1514 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_restart_det(i2c_regs_t *I2Cx)
1515 {
1516 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_RESTART_DET) == (I2C_INTR_RESTART_DET));
1517 }
1518
1519 /**
1520 * @brief Enable GEN_CALL interrupt.
1521 *
1522 * Register|BitsName
1523 * --------|--------
1524 * INTR_MASK | GEN_CALL
1525 *
1526 * @param I2Cx I2C instance.
1527 * @retval None.
1528 */
ll_i2c_enable_it_gen_call(i2c_regs_t * I2Cx)1529 __STATIC_INLINE void ll_i2c_enable_it_gen_call(i2c_regs_t *I2Cx)
1530 {
1531 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_GEN_CALL);
1532 }
1533
1534 /**
1535 * @brief Disable GEN_CALL interrupt.
1536 *
1537 * Register|BitsName
1538 * --------|--------
1539 * INTR_MASK | GEN_CALL
1540 *
1541 * @param I2Cx I2C instance.
1542 * @retval None.
1543 */
ll_i2c_disable_it_gen_call(i2c_regs_t * I2Cx)1544 __STATIC_INLINE void ll_i2c_disable_it_gen_call(i2c_regs_t *I2Cx)
1545 {
1546 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_GEN_CALL);
1547 }
1548
1549 /**
1550 * @brief Check if GEN_CALL interrupt is enabled or disabled.
1551 *
1552 * Register|BitsName
1553 * --------|--------
1554 * INTR_MASK | GEN_CALL
1555 *
1556 * @param I2Cx I2C instance.
1557 * @retval State of bit (1 or 0).
1558 */
ll_i2c_is_enabled_it_gen_call(i2c_regs_t * I2Cx)1559 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_gen_call(i2c_regs_t *I2Cx)
1560 {
1561 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_GEN_CALL) == (I2C_INTR_GEN_CALL));
1562 }
1563
1564 /**
1565 * @brief Enable START_DET received interrupt.
1566 *
1567 * Register|BitsName
1568 * --------|--------
1569 * INTR_MASK | START_DET
1570 *
1571 * @param I2Cx I2C instance.
1572 * @retval None.
1573 */
ll_i2c_enable_it_start_det(i2c_regs_t * I2Cx)1574 __STATIC_INLINE void ll_i2c_enable_it_start_det(i2c_regs_t *I2Cx)
1575 {
1576 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_START_DET);
1577 }
1578
1579 /**
1580 * @brief Disable START_DET received interrupt.
1581 *
1582 * Register|BitsName
1583 * --------|--------
1584 * INTR_MASK | START_DET
1585 *
1586 * @param I2Cx I2C instance.
1587 * @retval None.
1588 */
ll_i2c_disable_it_start_det(i2c_regs_t * I2Cx)1589 __STATIC_INLINE void ll_i2c_disable_it_start_det(i2c_regs_t *I2Cx)
1590 {
1591 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_START_DET);
1592 }
1593
1594 /**
1595 * @brief Check if START_DET received interrupt is enabled or disabled.
1596 *
1597 * Register|BitsName
1598 * --------|--------
1599 * INTR_MASK | START_DET
1600 *
1601 * @param I2Cx I2C instance.
1602 * @retval State of bit (1 or 0).
1603 */
ll_i2c_is_enabled_it_start_det(i2c_regs_t * I2Cx)1604 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_start_det(i2c_regs_t *I2Cx)
1605 {
1606 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_START_DET) == (I2C_INTR_START_DET));
1607 }
1608
1609 /**
1610 * @brief Enable STOP_DET interrupt.
1611 *
1612 * Register|BitsName
1613 * --------|--------
1614 * INTR_MASK | STOP_DET
1615 *
1616 * @param I2Cx I2C instance.
1617 * @retval None.
1618 */
ll_i2c_enable_it_stop_det(i2c_regs_t * I2Cx)1619 __STATIC_INLINE void ll_i2c_enable_it_stop_det(i2c_regs_t *I2Cx)
1620 {
1621 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_STOP_DET);
1622 }
1623
1624 /**
1625 * @brief Disable STOP_DET interrupt.
1626 *
1627 * Register|BitsName
1628 * --------|--------
1629 * INTR_MASK | STOP_DET
1630 *
1631 * @param I2Cx I2C instance.
1632 * @retval None.
1633 */
ll_i2c_disable_it_stop_det(i2c_regs_t * I2Cx)1634 __STATIC_INLINE void ll_i2c_disable_it_stop_det(i2c_regs_t *I2Cx)
1635 {
1636 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_STOP_DET);
1637 }
1638
1639 /**
1640 * @brief Check if STOP_DET interrupt is enabled or disabled.
1641 *
1642 * Register|BitsName
1643 * --------|--------
1644 * INTR_MASK | STOP_DET
1645 *
1646 * @param I2Cx I2C instance.
1647 * @retval State of bit (1 or 0).
1648 */
ll_i2c_is_enabled_it_stop_det(i2c_regs_t * I2Cx)1649 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_stop_det(i2c_regs_t *I2Cx)
1650 {
1651 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_STOP_DET) == (I2C_INTR_STOP_DET));
1652 }
1653
1654 /**
1655 * @brief Enable ACTIVITY interrupt.
1656 *
1657 * Register|BitsName
1658 * --------|--------
1659 * INTR_MASK | ACTIVITY
1660 *
1661 * @param I2Cx I2C instance.
1662 * @retval None.
1663 */
ll_i2c_enable_it_activity(i2c_regs_t * I2Cx)1664 __STATIC_INLINE void ll_i2c_enable_it_activity(i2c_regs_t *I2Cx)
1665 {
1666 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_ACTIVITY);
1667 }
1668
1669 /**
1670 * @brief Disable ACTIVITY interrupt.
1671 *
1672 * Register|BitsName
1673 * --------|--------
1674 * INTR_MASK | ACTIVITY
1675 *
1676 * @param I2Cx I2C instance.
1677 * @retval None.
1678 */
ll_i2c_disable_it_activity(i2c_regs_t * I2Cx)1679 __STATIC_INLINE void ll_i2c_disable_it_activity(i2c_regs_t *I2Cx)
1680 {
1681 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_ACTIVITY);
1682 }
1683
1684 /**
1685 * @brief Check if ACTIVITY interrupt is enabled or disabled.
1686 *
1687 * Register|BitsName
1688 * --------|--------
1689 * INTR_MASK | ACTIVITY
1690 *
1691 * @param I2Cx I2C instance.
1692 * @retval State of bit (1 or 0).
1693 */
ll_i2c_is_enabled_it_activity(i2c_regs_t * I2Cx)1694 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_activity(i2c_regs_t *I2Cx)
1695 {
1696 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_ACTIVITY) == (I2C_INTR_ACTIVITY));
1697 }
1698
1699 /**
1700 * @brief Enable RX_DONE interrupt.
1701 *
1702 * Register|BitsName
1703 * --------|--------
1704 * INTR_MASK | RX_DONE
1705 *
1706 * @param I2Cx I2C instance.
1707 * @retval State of bit (1 or 0).
1708 */
ll_i2c_enable_it_rx_done(i2c_regs_t * I2Cx)1709 __STATIC_INLINE void ll_i2c_enable_it_rx_done(i2c_regs_t *I2Cx)
1710 {
1711 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_RX_DONE);
1712 }
1713
1714 /**
1715 * @brief Disable RX_DONE interrupt.
1716 *
1717 * Register|BitsName
1718 * --------|--------
1719 * INTR_MASK | RX_DONE
1720 *
1721 * @param I2Cx I2C instance.
1722 * @retval None.
1723 */
ll_i2c_disable_it_rx_done(i2c_regs_t * I2Cx)1724 __STATIC_INLINE void ll_i2c_disable_it_rx_done(i2c_regs_t *I2Cx)
1725 {
1726 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_RX_DONE);
1727 }
1728
1729 /**
1730 * @brief Check if RX_DONE interrupt is enabled or disabled.
1731 *
1732 * Register|BitsName
1733 * --------|--------
1734 * INTR_MASK | RX_DONE
1735 *
1736 * @param I2Cx I2C instance.
1737 * @retval State of bit (1 or 0).
1738 */
ll_i2c_is_enable_it_rx_done(i2c_regs_t * I2Cx)1739 __STATIC_INLINE uint32_t ll_i2c_is_enable_it_rx_done(i2c_regs_t *I2Cx)
1740 {
1741 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_RX_DONE) == (I2C_INTR_RX_DONE));
1742 }
1743
1744 /**
1745 * @brief Enable TX_ABRT interrupt.
1746 *
1747 * Register|BitsName
1748 * --------|--------
1749 * INTR_MASK | TX_ABRT
1750 *
1751 * @param I2Cx I2C instance.
1752 * @retval None.
1753 */
ll_i2c_enable_it_rx_abort(i2c_regs_t * I2Cx)1754 __STATIC_INLINE void ll_i2c_enable_it_rx_abort(i2c_regs_t *I2Cx)
1755 {
1756 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_TX_ABRT);
1757 }
1758
1759 /**
1760 * @brief Disable TX_ABRT interrupt.
1761 *
1762 * Register|BitsName
1763 * --------|--------
1764 * INTR_MASK | TX_ABRT
1765 *
1766 * @param I2Cx I2C instance.
1767 * @retval None.
1768 */
ll_i2c_disable_it_tx_abort(i2c_regs_t * I2Cx)1769 __STATIC_INLINE void ll_i2c_disable_it_tx_abort(i2c_regs_t *I2Cx)
1770 {
1771 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_TX_ABRT);
1772 }
1773
1774 /**
1775 * @brief Check if TX_ABRT interrupt is enabled or disabled.
1776 *
1777 * Register|BitsName
1778 * --------|--------
1779 * INTR_MASK | TX_ABRT
1780 *
1781 * @param I2Cx I2C instance.
1782 * @retval None.
1783 */
ll_i2c_is_enabled_it_tx_abort(i2c_regs_t * I2Cx)1784 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_tx_abort(i2c_regs_t *I2Cx)
1785 {
1786 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_TX_ABRT) == (I2C_INTR_TX_ABRT));
1787 }
1788
1789 /**
1790 * @brief Enable RD_REQ interrupt.
1791 *
1792 * Register|BitsName
1793 * --------|--------
1794 * INTR_MASK | RD_REQ
1795 *
1796 * @param I2Cx I2C instance.
1797 * @retval None.
1798 */
ll_i2c_enable_it_read_req(i2c_regs_t * I2Cx)1799 __STATIC_INLINE void ll_i2c_enable_it_read_req(i2c_regs_t *I2Cx)
1800 {
1801 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_RD_REQ);
1802 }
1803
1804 /**
1805 * @brief Disable RD_REQ interrupt.
1806 *
1807 * Register|BitsName
1808 * --------|--------
1809 * INTR_MASK | RD_REQ
1810 *
1811 * @param I2Cx I2C instance.
1812 * @retval None.
1813 */
ll_i2c_disable_it_read_req(i2c_regs_t * I2Cx)1814 __STATIC_INLINE void ll_i2c_disable_it_read_req(i2c_regs_t *I2Cx)
1815 {
1816 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_RD_REQ);
1817 }
1818
1819 /**
1820 * @brief Check if RD_REQ interrupt is enabled or disabled.
1821 *
1822 * Register|BitsName
1823 * --------|--------
1824 * INTR_MASK | RD_REQ
1825 *
1826 * @param I2Cx I2C instance.
1827 * @retval State of bit (1 or 0).
1828 */
ll_i2c_is_enabled_it_read_req(i2c_regs_t * I2Cx)1829 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_read_req(i2c_regs_t *I2Cx)
1830 {
1831 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_RD_REQ) == (I2C_INTR_RD_REQ));
1832 }
1833
1834 /**
1835 * @brief Enable TX_EMPTY interrupt.
1836 *
1837 * Register|BitsName
1838 * --------|--------
1839 * INTR_MASK | TX_EMPTY
1840 *
1841 * @param I2Cx I2C instance.
1842 * @retval None.
1843 */
ll_i2c_enable_it_tx_empty(i2c_regs_t * I2Cx)1844 __STATIC_INLINE void ll_i2c_enable_it_tx_empty(i2c_regs_t *I2Cx)
1845 {
1846 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_TX_EMPTY);
1847 }
1848
1849 /**
1850 * @brief Disable TX_EMPTY interrupt.
1851 *
1852 * Register|BitsName
1853 * --------|--------
1854 * INTR_MASK | TX_EMPTY
1855 *
1856 * @param I2Cx I2C instance.
1857 * @retval None.
1858 */
ll_i2c_disable_it_tx_empty(i2c_regs_t * I2Cx)1859 __STATIC_INLINE void ll_i2c_disable_it_tx_empty(i2c_regs_t *I2Cx)
1860 {
1861 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_TX_EMPTY);
1862 }
1863
1864 /**
1865 * @brief Check if TX_EMPTY interrupt is enabled or disabled.
1866 *
1867 * Register|BitsName
1868 * --------|--------
1869 * INTR_MASK | TX_EMPTY
1870 *
1871 * @param I2Cx I2C instance.
1872 * @retval State of bit (1 or 0).
1873 */
ll_i2c_is_enabled_it_tx_empty(i2c_regs_t * I2Cx)1874 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_tx_empty(i2c_regs_t *I2Cx)
1875 {
1876 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_TX_EMPTY) == (I2C_INTR_TX_EMPTY));
1877 }
1878
1879 /**
1880 * @brief Enable TX_OVER interrupt.
1881 *
1882 * Register|BitsName
1883 * --------|--------
1884 * INTR_MASK | TX_OVER
1885 *
1886 * @param I2Cx I2C instance.
1887 * @retval None.
1888 */
ll_i2c_enable_it_tx_over(i2c_regs_t * I2Cx)1889 __STATIC_INLINE void ll_i2c_enable_it_tx_over(i2c_regs_t *I2Cx)
1890 {
1891 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_TX_OVER);
1892 }
1893
1894 /**
1895 * @brief Disable TX_OVER interrupt.
1896 *
1897 * Register|BitsName
1898 * --------|--------
1899 * INTR_MASK | TX_OVER
1900 *
1901 * @param I2Cx I2C instance.
1902 * @retval None.
1903 */
ll_i2c_disable_it_tx_over(i2c_regs_t * I2Cx)1904 __STATIC_INLINE void ll_i2c_disable_it_tx_over(i2c_regs_t *I2Cx)
1905 {
1906 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_TX_OVER);
1907 }
1908
1909 /**
1910 * @brief Check if TX_OVER interrupt is enabled or disabled.
1911 *
1912 * Register|BitsName
1913 * --------|--------
1914 * INTR_MASK | TX_OVER
1915 *
1916 * @param I2Cx I2C instance.
1917 * @retval State of bit (1 or 0).
1918 */
ll_i2c_is_enabled_it_tx_over(i2c_regs_t * I2Cx)1919 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_tx_over(i2c_regs_t *I2Cx)
1920 {
1921 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_TX_OVER) == (I2C_INTR_TX_OVER));
1922 }
1923
1924 /**
1925 * @brief Enable RX_FULL interrupt.
1926 *
1927 * Register|BitsName
1928 * --------|--------
1929 * INTR_MASK | RX_FULL
1930 *
1931 * @param I2Cx I2C instance.
1932 * @retval None.
1933 */
ll_i2c_enable_it_rx_full(i2c_regs_t * I2Cx)1934 __STATIC_INLINE void ll_i2c_enable_it_rx_full(i2c_regs_t *I2Cx)
1935 {
1936 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_RX_FULL);
1937 }
1938
1939 /**
1940 * @brief Disable RX_FULL interrupt.
1941 *
1942 * Register|BitsName
1943 * --------|--------
1944 * INTR_MASK | RX_FULL
1945 *
1946 * @param I2Cx I2C instance.
1947 * @retval None.
1948 */
ll_i2c_disbale_it_rx_full(i2c_regs_t * I2Cx)1949 __STATIC_INLINE void ll_i2c_disbale_it_rx_full(i2c_regs_t *I2Cx)
1950 {
1951 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_RX_FULL);
1952 }
1953
1954 /**
1955 * @brief Check if RX_FULL interrupt is enabled or disabled.
1956 *
1957 * Register|BitsName
1958 * --------|--------
1959 * INTR_MASK | RX_FULL
1960 *
1961 * @param I2Cx I2C instance.
1962 * @retval None.
1963 */
ll_i2c_ls_enabled_it_rx_full(i2c_regs_t * I2Cx)1964 __STATIC_INLINE uint32_t ll_i2c_ls_enabled_it_rx_full(i2c_regs_t *I2Cx)
1965 {
1966 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_RX_FULL) == (I2C_INTR_RX_FULL));
1967 }
1968
1969 /**
1970 * @brief Enable RX_OVER interrupt.
1971 *
1972 * Register|BitsName
1973 * --------|--------
1974 * INTR_MASK | RX_OVER
1975 *
1976 * @param I2Cx I2C instance.
1977 * @retval None.
1978 */
ll_i2c_enable_it_rx_over(i2c_regs_t * I2Cx)1979 __STATIC_INLINE void ll_i2c_enable_it_rx_over(i2c_regs_t *I2Cx)
1980 {
1981 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_RX_OVER);
1982 }
1983
1984 /**
1985 * @brief Disable RX_OVER interrupt.
1986 *
1987 * Register|BitsName
1988 * --------|--------
1989 * INTR_MASK | RX_OVER
1990 *
1991 * @param I2Cx I2C instance.
1992 * @retval None.
1993 */
ll_i2c_disable_it_rx_over(i2c_regs_t * I2Cx)1994 __STATIC_INLINE void ll_i2c_disable_it_rx_over(i2c_regs_t *I2Cx)
1995 {
1996 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_RX_OVER);
1997 }
1998
1999 /**
2000 * @brief Check if RX_OVER interrupt is enabled or disabled.
2001 *
2002 * Register|BitsName
2003 * --------|--------
2004 * INTR_MASK | RX_OVER
2005 *
2006 * @param I2Cx I2C instance.
2007 * @retval None.
2008 */
ll_i2c_is_enabled_it_rx_over(i2c_regs_t * I2Cx)2009 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_rx_over(i2c_regs_t *I2Cx)
2010 {
2011 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_RX_OVER) == (I2C_INTR_RX_OVER));
2012 }
2013
2014 /**
2015 * @brief Enable RX_UNDER interrupt.
2016 *
2017 * Register|BitsName
2018 * --------|--------
2019 * INTR_MASK | RX_UNDER
2020 *
2021 * @param I2Cx I2C instance.
2022 * @retval None.
2023 */
ll_i2c_enable_it_rx_under(i2c_regs_t * I2Cx)2024 __STATIC_INLINE void ll_i2c_enable_it_rx_under(i2c_regs_t *I2Cx)
2025 {
2026 SET_BITS(I2Cx->INTR_MASK, I2C_INTR_RX_UNDER);
2027 }
2028
2029 /**
2030 * @brief Disable RX_UNDER interrupt.
2031 *
2032 * Register|BitsName
2033 * --------|--------
2034 * INTR_MASK | RX_UNDER
2035 *
2036 * @param I2Cx I2C instance.
2037 * @retval None.
2038 */
ll_i2c_disable_it_rx_under(i2c_regs_t * I2Cx)2039 __STATIC_INLINE void ll_i2c_disable_it_rx_under(i2c_regs_t *I2Cx)
2040 {
2041 CLEAR_BITS(I2Cx->INTR_MASK, I2C_INTR_RX_UNDER);
2042 }
2043
2044 /**
2045 * @brief Check if RX_UNDER interrupt is enabled or disabled.
2046 *
2047 * Register|BitsName
2048 * --------|--------
2049 * INTR_MASK | RX_UNDER
2050 *
2051 * @param I2Cx I2C instance.
2052 * @retval None.
2053 */
ll_i2c_is_enabled_it_rx_under(i2c_regs_t * I2Cx)2054 __STATIC_INLINE uint32_t ll_i2c_is_enabled_it_rx_under(i2c_regs_t *I2Cx)
2055 {
2056 return (READ_BITS(I2Cx->INTR_MASK, I2C_INTR_RX_UNDER) == (I2C_INTR_RX_UNDER));
2057 }
2058
2059 /** @} */
2060
2061 /** @defgroup I2C_LL_EF_FLAG_management FLAG_management
2062 * @{
2063 */
2064
2065 /**
2066 * @brief Get I2C interrupt flags
2067 *
2068 * Register|BitsName
2069 * --------|--------
2070 * IC_INTR_STAT | MST_ON_HOLD
2071 * IC_INTR_STAT | RESTART_DET
2072 * IC_INTR_STAT | GEN_CALL
2073 * IC_INTR_STAT | START_DET
2074 * IC_INTR_STAT | STOP_DET
2075 * IC_INTR_STAT | ACTIVITY
2076 * IC_INTR_STAT | RX_DONE
2077 * IC_INTR_STAT | TX_ABRT
2078 * IC_INTR_STAT | RD_REQ
2079 * IC_INTR_STAT | TX_EMPTY
2080 * IC_INTR_STAT | TX_OVER
2081 * IC_INTR_STAT | RX_FULL
2082 * IC_INTR_STAT | RX_OVER
2083 * IC_INTR_STAT | RX_UNDER
2084 *
2085 * @param I2Cx I2C instance.
2086 * @retval Returned value can be one or combination of the following values:
2087 * @arg @ref LL_I2C_INTR_STAT_MST_ON_HOLD
2088 * @arg @ref LL_I2C_INTR_STAT_RESTART_DET
2089 * @arg @ref LL_I2C_INTR_STAT_GEN_CALL
2090 * @arg @ref LL_I2C_INTR_STAT_START_DET
2091 * @arg @ref LL_I2C_INTR_STAT_STOP_DET
2092 * @arg @ref LL_I2C_INTR_STAT_ACTIVITY
2093 * @arg @ref LL_I2C_INTR_STAT_RX_DONE
2094 * @arg @ref LL_I2C_INTR_STAT_TX_ABRT
2095 * @arg @ref LL_I2C_INTR_STAT_RD_REQ
2096 * @arg @ref LL_I2C_INTR_STAT_TX_EMPTY
2097 * @arg @ref LL_I2C_INTR_STAT_TX_OVER
2098 * @arg @ref LL_I2C_INTR_STAT_RX_FULL
2099 * @arg @ref LL_I2C_INTR_STAT_RX_OVER
2100 * @arg @ref LL_I2C_INTR_STAT_RX_UNDER
2101 */
ll_i2c_get_it_flag(i2c_regs_t * I2Cx)2102 __STATIC_INLINE uint32_t ll_i2c_get_it_flag(i2c_regs_t *I2Cx)
2103 {
2104 return (uint32_t)(READ_REG(I2Cx->INTR_STAT));
2105 }
2106
2107 /**
2108 * @brief Get I2C RAW interrupt flags
2109 *
2110 * Register|BitsName
2111 * --------|--------
2112 * IC_RAW_INTR_STAT | RAW_MST_ON_HOLD
2113 * IC_RAW_INTR_STAT | RAW_RESTART_DET
2114 * IC_RAW_INTR_STAT | RAW_GEN_CALL
2115 * IC_RAW_INTR_STAT | RAW_START_DET
2116 * IC_RAW_INTR_STAT | RAW_STOP_DET
2117 * IC_RAW_INTR_STAT | RAW_ACTIVITY
2118 * IC_RAW_INTR_STAT | RAW_RX_DONE
2119 * IC_RAW_INTR_STAT | RAW_TX_ABRT
2120 * IC_RAW_INTR_STAT | RAW_RD_REQ
2121 * IC_RAW_INTR_STAT | RAW_TX_EMPTY
2122 * IC_RAW_INTR_STAT | RAW_TX_OVER
2123 * IC_RAW_INTR_STAT | RAW_RX_FULL
2124 * IC_RAW_INTR_STAT | RAW_RX_OVER
2125 * IC_RAW_INTR_STAT | RAW_RX_UNDER
2126 *
2127 * @param I2Cx I2C instance.
2128 * @retval Returned value can be one or combination of the following values:
2129 * @arg @ref LL_I2C_INTR_STAT_MST_ON_HOLD
2130 * @arg @ref LL_I2C_INTR_STAT_RESTART_DET
2131 * @arg @ref LL_I2C_INTR_STAT_GEN_CALL
2132 * @arg @ref LL_I2C_INTR_STAT_START_DET
2133 * @arg @ref LL_I2C_INTR_STAT_STOP_DET
2134 * @arg @ref LL_I2C_INTR_STAT_ACTIVITY
2135 * @arg @ref LL_I2C_INTR_STAT_RX_DONE
2136 * @arg @ref LL_I2C_INTR_STAT_TX_ABRT
2137 * @arg @ref LL_I2C_INTR_STAT_RD_REQ
2138 * @arg @ref LL_I2C_INTR_STAT_TX_EMPTY
2139 * @arg @ref LL_I2C_INTR_STAT_TX_OVER
2140 * @arg @ref LL_I2C_INTR_STAT_RX_FULL
2141 * @arg @ref LL_I2C_INTR_STAT_RX_OVER
2142 * @arg @ref LL_I2C_INTR_STAT_RX_UNDER
2143 */
ll_i2c_get_raw_it_flag(i2c_regs_t * I2Cx)2144 __STATIC_INLINE uint32_t ll_i2c_get_raw_it_flag(i2c_regs_t *I2Cx)
2145 {
2146 return (uint32_t)(READ_REG(I2Cx->RAW_INTR_STAT));
2147 }
2148
2149 /**
2150 * @brief Indicate the status of MST_ON_HOLD flag.
2151 * @note RESET: Clear default value.
2152 * SET : When MST_ON_HOLD interrupt is actived.
2153 *
2154 * Register|BitsName
2155 * --------|--------
2156 * RAW_INTR_STAT | MST_ON_HOLD
2157 *
2158 * @param I2Cx I2C instance.
2159 * @retval State of bit (1 or 0).
2160 */
ll_i2c_is_active_flag_master_on_hold(i2c_regs_t * I2Cx)2161 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_master_on_hold(i2c_regs_t *I2Cx)
2162 {
2163 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_MST_ON_HOLD) == (I2C_INTR_MST_ON_HOLD));
2164 }
2165
2166 /**
2167 * @brief Indicate the status of RAW_MST_ON_HOLD flag.
2168 * @note RESET: Clear default value.
2169 * SET : When unmasked MST_ON_HOLD interrupt is actived.
2170 *
2171 * Register|BitsName
2172 * --------|--------
2173 * IC_RAW_INTR_STAT | RAW_MST_ON_HOLD
2174 *
2175 * @param I2Cx I2C instance.
2176 * @retval State of bit (1 or 0).
2177 */
ll_i2c_is_active_flag_raw_master_on_hold(i2c_regs_t * I2Cx)2178 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_master_on_hold(i2c_regs_t *I2Cx)
2179 {
2180 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_MST_ON_HOLD) == (I2C_INTR_MST_ON_HOLD));
2181 }
2182
2183 /**
2184 * @brief Indicate the status of RESTART_DET flag.
2185 * @note RESET: Clear default value.
2186 * SET : When masked RESTART_DET interrupt is actived.
2187 *
2188 * Register|BitsName
2189 * --------|--------
2190 * IC_INTR_STAT | RESTART_DET
2191 *
2192 * @param I2Cx I2C instance.
2193 * @retval State of bit (1 or 0).
2194 */
ll_i2c_is_active_flag_restart_det(i2c_regs_t * I2Cx)2195 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_restart_det(i2c_regs_t *I2Cx)
2196 {
2197 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_RESTART_DET) == (I2C_INTR_RESTART_DET));
2198 }
2199
2200 /**
2201 * @brief Indicate the status of RAW_RESTART_DET flag.
2202 * @note RESET: Clear default value.
2203 * SET : When unmasked RESTART_DET interrupt is actived.
2204 *
2205 * Register|BitsName
2206 * --------|--------
2207 * IC_RAW_INTR_STAT | RAW_RESTART_DET
2208 *
2209 * @param I2Cx I2C instance.
2210 * @retval State of bit (1 or 0).
2211 */
ll_i2c_is_active_flag_raw_restart_det(i2c_regs_t * I2Cx)2212 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_restart_det(i2c_regs_t *I2Cx)
2213 {
2214 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_RESTART_DET) == (I2C_INTR_RESTART_DET));
2215 }
2216
2217 /**
2218 * @brief Indicate the status of GEN_CALL flag.
2219 * @note RESET: Clear default value.
2220 * SET : When masked GEN_CALL interrupt is actived.
2221 *
2222 * Register|BitsName
2223 * --------|--------
2224 * IC_INTR_STAT | GEN_CALL
2225 *
2226 * @param I2Cx I2C instance.
2227 * @retval State of bit (1 or 0).
2228 */
ll_i2c_is_active_flag_gen_call(i2c_regs_t * I2Cx)2229 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_gen_call(i2c_regs_t *I2Cx)
2230 {
2231 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_GEN_CALL) == (I2C_INTR_GEN_CALL));
2232 }
2233
2234 /**
2235 * @brief Indicate the status of RAW_GEN_CALL flag.
2236 * @note RESET: Clear default value.
2237 * SET : When unmasked GEN_CALL interrupt is actived.
2238 *
2239 * Register|BitsName
2240 * --------|--------
2241 * IC_RAW_INTR_STAT | RAW_GEN_CALL
2242 *
2243 * @param I2Cx I2C instance.
2244 * @retval State of bit (1 or 0).
2245 */
ll_i2c_is_active_flag_raw_gen_call(i2c_regs_t * I2Cx)2246 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_gen_call(i2c_regs_t *I2Cx)
2247 {
2248 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_GEN_CALL) == (I2C_INTR_GEN_CALL));
2249 }
2250
2251 /**
2252 * @brief Indicate the status of START_DET flag.
2253 * @note RESET: Clear default value.
2254 * SET : When masked START_DET interrupt is actived.
2255 *
2256 * Register|BitsName
2257 * --------|--------
2258 * IC_INTR_STAT | START_DET
2259 *
2260 * @param I2Cx I2C instance.
2261 * @retval State of bit (1 or 0).
2262 */
ll_i2c_is_active_flag_start_det(i2c_regs_t * I2Cx)2263 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_start_det(i2c_regs_t *I2Cx)
2264 {
2265 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_START_DET) == (I2C_INTR_START_DET));
2266 }
2267
2268 /**
2269 * @brief Indicate the status of RAW_START_DET flag.
2270 * @note RESET: Clear default value.
2271 * SET : When unmasked START_DET interrupt is actived.
2272 *
2273 * Register|BitsName
2274 * --------|--------
2275 * IC_RAW_INTR_STAT | RAW_START_DET
2276 *
2277 * @param I2Cx I2C instance.
2278 * @retval State of bit (1 or 0).
2279 */
ll_i2c_is_active_flag_raw_start_det(i2c_regs_t * I2Cx)2280 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_start_det(i2c_regs_t *I2Cx)
2281 {
2282 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_START_DET) == (I2C_INTR_START_DET));
2283 }
2284
2285 /**
2286 * @brief Indicate the status of STOP_DET flag.
2287 * @note RESET: Clear default value.
2288 * SET : When masked STOP_DET interrupt is actived.
2289 *
2290 * Register|BitsName
2291 * --------|--------
2292 * IC_INTR_STAT | STOP_DET
2293 *
2294 * @param I2Cx I2C instance.
2295 * @retval State of bit (1 or 0).
2296 */
ll_i2c_is_active_flag_stop_det(i2c_regs_t * I2Cx)2297 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_stop_det(i2c_regs_t *I2Cx)
2298 {
2299 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_STOP_DET) == (I2C_INTR_STOP_DET));
2300 }
2301
2302 /**
2303 * @brief Indicate the status of RAW_STOP_DET flag.
2304 * @note RESET: Clear default value.
2305 * SET : When unmasked STOP_DET interrupt is actived.
2306 *
2307 * Register|BitsName
2308 * --------|--------
2309 * IC_RAW_INTR_STAT | RAW_STOP_DET
2310 *
2311 * @param I2Cx I2C instance.
2312 * @retval State of bit (1 or 0).
2313 */
ll_i2c_is_active_flag_raw_stop_det(i2c_regs_t * I2Cx)2314 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_stop_det(i2c_regs_t *I2Cx)
2315 {
2316 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_STOP_DET) == (I2C_INTR_STOP_DET));
2317 }
2318
2319 /**
2320 * @brief Indicate the status of ACTIVITY flag.
2321 * @note RESET: Clear default value.
2322 * SET : When masked ACTIVITY interrupt is actived.
2323 *
2324 * Register|BitsName
2325 * --------|--------
2326 * IC_INTR_STAT | ACTIVITY
2327 *
2328 * @param I2Cx I2C instance.
2329 * @retval State of bit (1 or 0).
2330 */
ll_i2c_is_active_flag_activity(i2c_regs_t * I2Cx)2331 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_activity(i2c_regs_t *I2Cx)
2332 {
2333 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_ACTIVITY) == (I2C_INTR_ACTIVITY));
2334 }
2335
2336 /**
2337 * @brief Indicate the status of RAW_ACTIVITY flag.
2338 * @note RESET: Clear default value.
2339 * SET : When unmasked ACTIVITY interrupt is actived.
2340 *
2341 * Register|BitsName
2342 * --------|--------
2343 * IC_RAW_INTR_STAT | RAW_ACTIVITY
2344 *
2345 * @param I2Cx I2C instance.
2346 * @retval State of bit (1 or 0).
2347 */
ll_i2c_is_active_flag_raw_activity(i2c_regs_t * I2Cx)2348 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_activity(i2c_regs_t *I2Cx)
2349 {
2350 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_ACTIVITY) == (I2C_INTR_ACTIVITY));
2351 }
2352
2353 /**
2354 * @brief Indicate the status of RX_DONE flag.
2355 * @note RESET: Clear default value.
2356 * SET : When masked RX_DONE interrupt is actived.
2357 *
2358 * Register|BitsName
2359 * --------|--------
2360 * IC_INTR_STAT | RX_DONE
2361 *
2362 * @param I2Cx I2C instance.
2363 * @retval State of bit (1 or 0).
2364 */
ll_i2c_is_active_flag_rx_done(i2c_regs_t * I2Cx)2365 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_rx_done(i2c_regs_t *I2Cx)
2366 {
2367 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_RX_DONE) == (I2C_INTR_RX_DONE));
2368 }
2369
2370 /**
2371 * @brief Indicate the status of RAW_RX_DONE flag.
2372 * @note RESET: Clear default value.
2373 * SET : When unmasked RX_DONE interrupt is actived.
2374 *
2375 * Register|BitsName
2376 * --------|--------
2377 * IC_RAW_INTR_STAT | RAW_RX_DONE
2378 *
2379 * @param I2Cx I2C instance.
2380 * @retval State of bit (1 or 0).
2381 */
ll_i2c_is_active_flag_raw_rx_done(i2c_regs_t * I2Cx)2382 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_rx_done(i2c_regs_t *I2Cx)
2383 {
2384 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_RX_DONE) == (I2C_INTR_RX_DONE));
2385 }
2386
2387 /**
2388 * @brief Indicate the status of TX_ABRT flag.
2389 * @note RESET: Clear default value.
2390 * SET : When masked TX_ABRT interrupt is actived.
2391 *
2392 * Register|BitsName
2393 * --------|--------
2394 * IC_INTR_STAT | TX_ABRT
2395 *
2396 * @param I2Cx I2C instance.
2397 * @retval State of bit (1 or 0).
2398 */
ll_i2c_is_active_flag_tx_abort(i2c_regs_t * I2Cx)2399 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_tx_abort(i2c_regs_t *I2Cx)
2400 {
2401 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_TX_ABRT) == (I2C_INTR_TX_ABRT));
2402 }
2403
2404 /**
2405 * @brief Indicate the status of RAW_TX_ABRT flag.
2406 * @note RESET: Clear default value.
2407 * SET : When unmasked TX_ABRT interrupt is actived.
2408 *
2409 * Register|BitsName
2410 * --------|--------
2411 * IC_RAW_INTR_STAT | RAW_TX_ABRT
2412 *
2413 * @param I2Cx I2C instance.
2414 * @retval State of bit (1 or 0).
2415 */
ll_i2c_is_active_flag_raw_tx_abort(i2c_regs_t * I2Cx)2416 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_tx_abort(i2c_regs_t *I2Cx)
2417 {
2418 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_TX_ABRT) == (I2C_INTR_TX_ABRT));
2419 }
2420
2421 /**
2422 * @brief Indicate the status of RD_REQ flag.
2423 * @note RESET: Clear default value.
2424 * SET : When masked RD_REQ interrupt is actived.
2425 *
2426 * Register|BitsName
2427 * --------|--------
2428 * IC_INTR_STAT | RD_REQ
2429 *
2430 * @param I2Cx I2C instance.
2431 * @retval State of bit (1 or 0).
2432 */
ll_i2c_is_active_flag_read_req(i2c_regs_t * I2Cx)2433 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_read_req(i2c_regs_t *I2Cx)
2434 {
2435 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_RD_REQ) == (I2C_INTR_RD_REQ));
2436 }
2437
2438 /**
2439 * @brief Indicate the status of RAW_RD_REQ flag.
2440 * @note RESET: Clear default value.
2441 * SET : When unmasked RD_REQ interrupt is actived.
2442 *
2443 * Register|BitsName
2444 * --------|--------
2445 * IC_RAW_INTR_STAT | RAW_RD_REQ
2446 *
2447 * @param I2Cx I2C instance.
2448 * @retval State of bit (1 or 0).
2449 */
ll_i2c_is_active_flag_raw_read_req(i2c_regs_t * I2Cx)2450 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_read_req(i2c_regs_t *I2Cx)
2451 {
2452 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_RD_REQ) == (I2C_INTR_RD_REQ));
2453 }
2454
2455 /**
2456 * @brief Indicate the status of TX_EMPTY flag.
2457 * @note RESET: Clear default value.
2458 * SET : When masked TX_EMPTY interrupt is actived.
2459 *
2460 * Register|BitsName
2461 * --------|--------
2462 * IC_INTR_STAT | TX_EMPTY
2463 *
2464 * @param I2Cx I2C instance.
2465 * @retval State of bit (1 or 0).
2466 */
ll_i2c_is_active_flag_tx_empty(i2c_regs_t * I2Cx)2467 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_tx_empty(i2c_regs_t *I2Cx)
2468 {
2469 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_TX_EMPTY) == (I2C_INTR_TX_EMPTY));
2470 }
2471
2472 /**
2473 * @brief Indicate the status of RAW_TX_EMPTY flag.
2474 * @note RESET: Clear default value.
2475 * SET : When unmasked TX_EMPTY interrupt is actived.
2476 *
2477 * Register|BitsName
2478 * --------|--------
2479 * IC_RAW_INTR_STAT | RAW_TX_EMPTY
2480 *
2481 * @param I2Cx I2C instance.
2482 * @retval State of bit (1 or 0).
2483 */
ll_i2c_is_active_flag_raw_tx_empty(i2c_regs_t * I2Cx)2484 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_tx_empty(i2c_regs_t *I2Cx)
2485 {
2486 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_TX_EMPTY) == (I2C_INTR_TX_EMPTY));
2487 }
2488
2489 /**
2490 * @brief Indicate the status of TX_OVER flag.
2491 * @note RESET: Clear default value.
2492 * SET : When masked TX_OVER interrupt is actived.
2493 *
2494 * Register|BitsName
2495 * --------|--------
2496 * IC_INTR_STAT | TX_OVER
2497 *
2498 * @param I2Cx I2C instance.
2499 * @retval State of bit (1 or 0).
2500 */
ll_i2c_is_active_flag_tx_over(i2c_regs_t * I2Cx)2501 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_tx_over(i2c_regs_t *I2Cx)
2502 {
2503 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_TX_OVER) == (I2C_INTR_TX_OVER));
2504 }
2505
2506 /**
2507 * @brief Indicate the status of RAW_TX_OVER flag.
2508 * @note RESET: Clear default value.
2509 * SET : When unmasked TX_OVER interrupt is actived.
2510 *
2511 * Register|BitsName
2512 * --------|--------
2513 * IC_RAW_INTR_STAT | RAW_TX_OVER
2514 *
2515 * @param I2Cx I2C instance.
2516 * @retval State of bit (1 or 0).
2517 */
ll_i2c_is_active_flag_raw_tx_over(i2c_regs_t * I2Cx)2518 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_tx_over(i2c_regs_t *I2Cx)
2519 {
2520 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_TX_OVER) == (I2C_INTR_TX_OVER));
2521 }
2522
2523 /**
2524 * @brief Indicate the status of RX_FULL flag.
2525 * @note RESET: Clear default value.
2526 * SET : When masked RX_FULL interrupt is actived.
2527 *
2528 * Register|BitsName
2529 * --------|--------
2530 * IC_INTR_STAT | RX_FULL
2531 *
2532 * @param I2Cx I2C instance.
2533 * @retval State of bit (1 or 0).
2534 */
ll_i2c_is_active_flag_rx_full(i2c_regs_t * I2Cx)2535 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_rx_full(i2c_regs_t *I2Cx)
2536 {
2537 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_RX_FULL) == (I2C_INTR_RX_FULL));
2538 }
2539
2540 /**
2541 * @brief Indicate the status of RAW_RX_FULL flag.
2542 * @note RESET: Clear default value.
2543 * SET : When unmasked RX_FULL interrupt is actived.
2544 *
2545 * Register|BitsName
2546 * --------|--------
2547 * IC_RAW_INTR_STAT | RAW_RX_FULL
2548 *
2549 * @param I2Cx I2C instance.
2550 * @retval State of bit (1 or 0).
2551 */
ll_i2c_is_active_flag_raw_rx_full(i2c_regs_t * I2Cx)2552 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_rx_full(i2c_regs_t *I2Cx)
2553 {
2554 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_RX_FULL) == (I2C_INTR_RX_FULL));
2555 }
2556
2557 /**
2558 * @brief Indicate the status of RX_OVER flag.
2559 * @note RESET: Clear default value.
2560 * SET : When masked RX_OVER interrupt is actived.
2561 *
2562 * Register|BitsName
2563 * --------|--------
2564 * IC_INTR_STAT | RX_OVER
2565 *
2566 * @param I2Cx I2C instance.
2567 * @retval State of bit (1 or 0).
2568 */
ll_i2c_is_active_flag_rx_over(i2c_regs_t * I2Cx)2569 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_rx_over(i2c_regs_t *I2Cx)
2570 {
2571 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_RX_OVER) == (I2C_INTR_RX_OVER));
2572 }
2573
2574 /**
2575 * @brief Indicate the status of RAW_RX_OVER flag.
2576 * @note RESET: Clear default value.
2577 * SET : When unmasked RX_OVER interrupt is actived.
2578 *
2579 * Register|BitsName
2580 * --------|--------
2581 * IC_RAW_INTR_STAT | RAW_RX_OVER
2582 *
2583 * @param I2Cx I2C instance.
2584 * @retval State of bit (1 or 0).
2585 */
ll_i2c_is_active_flag_raw_rx_over(i2c_regs_t * I2Cx)2586 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_rx_over(i2c_regs_t *I2Cx)
2587 {
2588 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_RX_OVER) == (I2C_INTR_RX_OVER));
2589 }
2590
2591 /**
2592 * @brief Indicate the status of RX_UNDER flag.
2593 * @note RESET: Clear default value.
2594 * SET : When masked RX_UNDER interrupt is actived.
2595 *
2596 * Register|BitsName
2597 * --------|--------
2598 * IC_INTR_STAT | RX_UNDER
2599 *
2600 * @param I2Cx I2C instance.
2601 * @retval State of bit (1 or 0).
2602 */
ll_i2c_is_active_flag_rx_under(i2c_regs_t * I2Cx)2603 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_rx_under(i2c_regs_t *I2Cx)
2604 {
2605 return (READ_BITS(I2Cx->INTR_STAT, I2C_INTR_RX_UNDER) == (I2C_INTR_RX_UNDER));
2606 }
2607
2608 /**
2609 * @brief Indicate the status of RAW_RX_UNDER flag.
2610 * @note RESET: Clear default value.
2611 * SET : When unmasked RX_UNDER interrupt is actived.
2612 *
2613 * Register|BitsName
2614 * --------|--------
2615 * IC_RAW_INTR_STAT | RAW_RX_UNDER
2616 *
2617 * @param I2Cx I2C instance.
2618 * @retval State of bit (1 or 0).
2619 */
ll_i2c_is_active_flag_raw_rx_under(i2c_regs_t * I2Cx)2620 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_raw_rx_under(i2c_regs_t *I2Cx)
2621 {
2622 return (READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_RX_UNDER) == (I2C_INTR_RX_UNDER));
2623 }
2624
2625 /**
2626 * @brief Clear the combined interrupt, all individual interrupts, and the IC_TX_ABRT_SOURCE register
2627 *
2628 * Register|BitsName
2629 * --------|--------
2630 * IC_CLR_INTR | CLR_INTR
2631 *
2632 * @param I2Cx I2C instance.
2633 * @retval None.
2634 */
ll_i2c_clear_flag_intr(i2c_regs_t * I2Cx)2635 __STATIC_INLINE void ll_i2c_clear_flag_intr(i2c_regs_t *I2Cx)
2636 {
2637 __IO uint32_t tmpreg;
2638 tmpreg = READ_REG(I2Cx->CLR_INTR);
2639 (void) tmpreg;
2640 }
2641
2642 /**
2643 * @brief Clear GEN_CALL flag.
2644 *
2645 * Register|BitsName
2646 * --------|--------
2647 * IC_CLR_GEN_CALL | CLR_GEN_CALL
2648 *
2649 * @param I2Cx I2C instance.
2650 * @retval None.
2651 */
ll_i2c_clear_flag_gen_call(i2c_regs_t * I2Cx)2652 __STATIC_INLINE void ll_i2c_clear_flag_gen_call(i2c_regs_t *I2Cx)
2653 {
2654 __IO uint32_t tmpreg;
2655 tmpreg = READ_REG(I2Cx->CLR_GEN_CALL);
2656 (void) tmpreg;
2657 }
2658
2659 /**
2660 * @brief Clear START_DET flag.
2661 *
2662 * Register|BitsName
2663 * --------|--------
2664 * IC_CLR_START_DET | CLR_START_DET
2665 *
2666 * @param I2Cx I2C instance.
2667 * @retval None.
2668 */
ll_i2c_clear_flag_start_det(i2c_regs_t * I2Cx)2669 __STATIC_INLINE void ll_i2c_clear_flag_start_det(i2c_regs_t *I2Cx)
2670 {
2671 __IO uint32_t tmpreg;
2672 tmpreg = READ_REG(I2Cx->CLR_START_DET);
2673 (void) tmpreg;
2674 }
2675
2676 /**
2677 * @brief Clear STOP_DET flag.
2678 *
2679 * Register|BitsName
2680 * --------|--------
2681 * IC_CLR_STOP_DET | CLR_STOP_DET
2682 *
2683 * @param I2Cx I2C instance.
2684 * @retval None.
2685 */
ll_i2c_clear_flag_stop_det(i2c_regs_t * I2Cx)2686 __STATIC_INLINE void ll_i2c_clear_flag_stop_det(i2c_regs_t *I2Cx)
2687 {
2688 __IO uint32_t tmpreg;
2689 tmpreg = READ_REG(I2Cx->CLR_STOP_DET);
2690 (void) tmpreg;
2691 }
2692
2693 /**
2694 * @brief Clear ACTIVITY flag.
2695 *
2696 * Register|BitsName
2697 * --------|--------
2698 * IC_CLR_ACTIVITY | CLR_ACTIVITY
2699 *
2700 * @param I2Cx I2C instance.
2701 * @retval None.
2702 */
ll_i2c_clear_flag_activity(i2c_regs_t * I2Cx)2703 __STATIC_INLINE void ll_i2c_clear_flag_activity(i2c_regs_t *I2Cx)
2704 {
2705 __IO uint32_t tmpreg;
2706 tmpreg = READ_REG(I2Cx->CLR_ACTIVITY);
2707 (void) tmpreg;
2708 }
2709
2710 /**
2711 * @brief Clear RX_DONE flag.
2712 *
2713 * Register|BitsName
2714 * --------|--------
2715 * IC_CLR_RX_DONE | CLR_RX_DONE
2716 *
2717 * @param I2Cx I2C instance.
2718 * @retval None.
2719 */
ll_i2c_clear_flag_rx_done(i2c_regs_t * I2Cx)2720 __STATIC_INLINE void ll_i2c_clear_flag_rx_done(i2c_regs_t *I2Cx)
2721 {
2722 __IO uint32_t tmpreg;
2723 tmpreg = READ_REG(I2Cx->CLR_RX_DONE);
2724 (void) tmpreg;
2725 }
2726
2727 /**
2728 * @brief Clear TX_ABRT flag.
2729 *
2730 * Register|BitsName
2731 * --------|--------
2732 * IC_CLR_TX_ABRT | CLR_TX_ABRT
2733 *
2734 * @param I2Cx I2C instance.
2735 * @retval None.
2736 */
ll_i2c_clear_flag_tx_abort(i2c_regs_t * I2Cx)2737 __STATIC_INLINE void ll_i2c_clear_flag_tx_abort(i2c_regs_t *I2Cx)
2738 {
2739 __IO uint32_t tmpreg;
2740 tmpreg = READ_REG(I2Cx->CLR_TX_ABRT);
2741 (void) tmpreg;
2742 }
2743
2744 /**
2745 * @brief Clear RD_REQ flag.
2746 *
2747 * Register|BitsName
2748 * --------|--------
2749 * IC_CLR_RD_REQ | CLR_RD_REQ
2750 *
2751 * @param I2Cx I2C instance.
2752 * @retval None.
2753 */
ll_i2c_clear_flag_read_req(i2c_regs_t * I2Cx)2754 __STATIC_INLINE void ll_i2c_clear_flag_read_req(i2c_regs_t *I2Cx)
2755 {
2756 __IO uint32_t tmpreg;
2757 tmpreg = READ_REG(I2Cx->CLR_RD_REQ);
2758 (void) tmpreg;
2759 }
2760
2761 /**
2762 * @brief Clear TX_OVER flag.
2763 *
2764 * Register|BitsName
2765 * --------|--------
2766 * IC_CLR_TX_OVER | CLR_TX_OVER
2767 *
2768 * @param I2Cx I2C instance.
2769 * @retval None.
2770 */
ll_i2c_clear_flag_tx_over(i2c_regs_t * I2Cx)2771 __STATIC_INLINE void ll_i2c_clear_flag_tx_over(i2c_regs_t *I2Cx)
2772 {
2773 __IO uint32_t tmpreg;
2774 tmpreg = READ_REG(I2Cx->CLR_TX_OVER);
2775 (void) tmpreg;
2776 }
2777
2778 /**
2779 * @brief Clear RX_OVER flag.
2780 *
2781 * Register|BitsName
2782 * --------|--------
2783 * IC_CLR_RX_OVER | CLR_RX_OVER
2784 *
2785 * @param I2Cx I2C instance.
2786 * @retval None.
2787 */
ll_i2c_clear_flag_rx_over(i2c_regs_t * I2Cx)2788 __STATIC_INLINE void ll_i2c_clear_flag_rx_over(i2c_regs_t *I2Cx)
2789 {
2790 __IO uint32_t tmpreg;
2791 tmpreg = READ_REG(I2Cx->CLR_RX_OVER);
2792 (void) tmpreg;
2793 }
2794
2795 /**
2796 * @brief Clear RX_UNDER flag.
2797 *
2798 * Register|BitsName
2799 * --------|--------
2800 * IC_CLR_RX_UNDER | CLR_RX_UNDER
2801 *
2802 * @param I2Cx I2C instance.
2803 * @retval None.
2804 */
ll_i2c_clear_flag_rx_under(i2c_regs_t * I2Cx)2805 __STATIC_INLINE void ll_i2c_clear_flag_rx_under(i2c_regs_t *I2Cx)
2806 {
2807 __IO uint32_t tmpreg;
2808 tmpreg = READ_REG(I2Cx->CLR_RX_UNDER);
2809 (void) tmpreg;
2810 }
2811
2812 /**
2813 * @brief Indicate the status of IC_STATUS Slave FSM Activity Status flag.
2814 * @note RESET: Slave FSM is in IDLE state.
2815 * SET : When Slave FSM is not in IDLE state.
2816 *
2817 * Register|BitsName
2818 * --------|--------
2819 * IC_STATUS | SLV_ACTIVITY
2820 *
2821 * @param I2Cx I2C instance.
2822 * @retval State of bit (1 or 0).
2823 */
ll_i2c_is_active_flag_status_slave_activity(i2c_regs_t * I2Cx)2824 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_slave_activity(i2c_regs_t *I2Cx)
2825 {
2826 return (READ_BITS(I2Cx->STATUS, I2C_STATUS_SLV_ACTIVITY) == (I2C_STATUS_SLV_ACTIVITY));
2827 }
2828
2829 /**
2830 * @brief Indicate the status of IC_STATUS Master FSM Activity Status flag.
2831 * @note RESET: Master FSM is in IDLE state.
2832 * SET : When Master FSM is not in IDLE state.
2833 *
2834 * Register|BitsName
2835 * --------|--------
2836 * IC_STATUS | MST_ACTIVITY
2837 *
2838 * @param I2Cx I2C instance.
2839 * @retval State of bit (1 or 0).
2840 */
ll_i2c_is_active_flag_status_master_activity(i2c_regs_t * I2Cx)2841 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_master_activity(i2c_regs_t *I2Cx)
2842 {
2843 return (READ_BITS(I2Cx->STATUS, I2C_STATUS_MST_ACTIVITY) == (I2C_STATUS_MST_ACTIVITY));
2844 }
2845
2846 /**
2847 * @brief Indicate the status of IC_STATUS Receive FIFO Completely Full flag.
2848 * @note RESET: Receive FIFO is not full.
2849 * SET : When Receive FIFO is full.
2850 *
2851 * Register|BitsName
2852 * --------|--------
2853 * IC_STATUS | RFF
2854 *
2855 * @param I2Cx I2C instance.
2856 * @retval State of bit (1 or 0).
2857 */
ll_i2c_is_active_flag_status_rff(i2c_regs_t * I2Cx)2858 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_rff(i2c_regs_t *I2Cx)
2859 {
2860 return (READ_BITS(I2Cx->STATUS, I2C_STATUS_RFF) == (I2C_STATUS_RFF));
2861 }
2862
2863 /**
2864 * @brief Indicate the status of IC_STATUS Receive FIFO Not Empty flag.
2865 * @note RESET: Receive FIFO is empty.
2866 * SET : When Receive FIFO is not empty.
2867 *
2868 * Register|BitsName
2869 * --------|--------
2870 * IC_STATUS | RFNE
2871 *
2872 * @param I2Cx I2C instance.
2873 * @retval State of bit (1 or 0).
2874 */
ll_i2c_is_active_flag_status_rfne(i2c_regs_t * I2Cx)2875 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_rfne(i2c_regs_t *I2Cx)
2876 {
2877 return (READ_BITS(I2Cx->STATUS, I2C_STATUS_RFNE) == (I2C_STATUS_RFNE));
2878 }
2879
2880 /**
2881 * @brief Indicate the status of IC_STATUS Transmit FIFO Completely Empty flag.
2882 * @note RESET: Transmit FIFO is not empty.
2883 * SET : When Transmit FIFO is empty.
2884 *
2885 * Register|BitsName
2886 * --------|--------
2887 * IC_STATUS | TFE
2888 *
2889 * @param I2Cx I2C instance.
2890 * @retval State of bit (1 or 0).
2891 */
ll_i2c_is_active_flag_status_tfe(i2c_regs_t * I2Cx)2892 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_tfe(i2c_regs_t *I2Cx)
2893 {
2894 return (READ_BITS(I2Cx->STATUS, I2C_STATUS_TFE) == (I2C_STATUS_TFE));
2895 }
2896
2897 /**
2898 * @brief Indicate the status of IC_STATUS Transmit FIFO Not Full flag.
2899 * @note RESET: Transmit FIFO is full.
2900 * SET : When Transmit FIFO is not full.
2901 *
2902 * Register|BitsName
2903 * --------|--------
2904 * IC_STATUS | TFNF
2905 *
2906 * @param I2Cx I2C instance.
2907 * @retval State of bit (1 or 0).
2908 */
ll_i2c_is_active_flag_status_tfnf(i2c_regs_t * I2Cx)2909 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_tfnf(i2c_regs_t *I2Cx)
2910 {
2911 return (READ_BITS(I2Cx->STATUS, I2C_STATUS_TFNF) == (I2C_STATUS_TFNF));
2912 }
2913
2914 /**
2915 * @brief Indicate the status of IC_STATUS ACTIVITY flag.
2916 * @note RESET: I2C is idle.
2917 * SET : When I2C is active.
2918 *
2919 * Register|BitsName
2920 * --------|--------
2921 * IC_STATUS | ACTIVITY
2922 *
2923 * @param I2Cx I2C instance.
2924 * @retval State of bit (1 or 0).
2925 */
ll_i2c_is_active_flag_status_activity(i2c_regs_t * I2Cx)2926 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_status_activity(i2c_regs_t *I2Cx)
2927 {
2928 return (READ_BITS(I2Cx->STATUS, I2C_STATUS_ACTIVITY) == (I2C_STATUS_ACTIVITY));
2929 }
2930
2931 /**
2932 * @brief Indicate the status of Slave Received Data Lost flag.
2933 * @note RESET: Slave RX Data is not lost.
2934 * SET : Slave RX Data is lost.
2935 *
2936 * Register|BitsName
2937 * --------|--------
2938 * IC_ENABLE_STATUS | SLV_RX_LOST
2939 *
2940 * @param I2Cx I2C instance.
2941 * @retval State of bit (1 or 0).
2942 */
ll_i2c_is_active_flag_slave_rx_data_lost(i2c_regs_t * I2Cx)2943 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_slave_rx_data_lost(i2c_regs_t *I2Cx)
2944 {
2945 return (READ_BITS(I2Cx->ENABLE_STATUS, I2C_ENABLE_STATUS_SLV_RX_LOST) == (I2C_ENABLE_STATUS_SLV_RX_LOST));
2946 }
2947
2948 /**
2949 * @brief Indicate the status of Slave Disabled While Busy flag.
2950 * @note RESET: Slave is disabled when it is idle.
2951 * SET : Slave is disabled when it is active.
2952 *
2953 * Register|BitsName
2954 * --------|--------
2955 * IC_ENABLE_STATUS | SLV_DIS_WHL_BUSY
2956 *
2957 * @param I2Cx I2C instance.
2958 * @retval State of bit (1 or 0).
2959 */
ll_i2c_is_active_flag_slave_dis_whl_busy(i2c_regs_t * I2Cx)2960 __STATIC_INLINE uint32_t ll_i2c_is_active_flag_slave_dis_whl_busy(i2c_regs_t *I2Cx)
2961 {
2962 return (READ_BITS(I2Cx->ENABLE_STATUS, I2C_ENABLE_STATUS_SLV_DIS_WHL_BUSY) == (I2C_ENABLE_STATUS_SLV_DIS_WHL_BUSY));
2963 }
2964 /** @} */
2965
2966 /** @defgroup I2C_LL_EF_DMA_Management DMA_Management
2967 * @{
2968 */
2969
2970 /**
2971 * @brief Enable DMA transmission requests.
2972 *
2973 * Register|BitsName
2974 * --------|--------
2975 * IC_DMA_CR | TDMAE
2976 *
2977 * @retval Value range between 0 ~ 0x8.
2978 * @retval None.
2979 */
ll_i2c_enable_dma_req_tx(i2c_regs_t * I2Cx)2980 __STATIC_INLINE void ll_i2c_enable_dma_req_tx(i2c_regs_t *I2Cx)
2981 {
2982 SET_BITS(I2Cx->DMA_CR, I2C_DMA_CR_TDMAE);
2983 }
2984
2985 /**
2986 * @brief Disable DMA transmission requests.
2987 *
2988 * Register|BitsName
2989 * --------|--------
2990 * IC_DMA_CR | TDMAE
2991 *
2992 * @param I2Cx I2C instance.
2993 * @retval None.
2994 */
ll_i2c_disable_dma_req_tx(i2c_regs_t * I2Cx)2995 __STATIC_INLINE void ll_i2c_disable_dma_req_tx(i2c_regs_t *I2Cx)
2996 {
2997 CLEAR_BITS(I2Cx->DMA_CR, I2C_DMA_CR_TDMAE);
2998 }
2999
3000 /**
3001 * @brief Check if DMA transmission requests are enabled or disabled.
3002 *
3003 * Register|BitsName
3004 * --------|--------
3005 * IC_DMA_CR | TDMAE
3006 *
3007 * @param I2Cx I2C instance.
3008 * @retval State of bit (1 or 0).
3009 */
ll_i2c_is_enabled_dma_req_tx(i2c_regs_t * I2Cx)3010 __STATIC_INLINE uint32_t ll_i2c_is_enabled_dma_req_tx(i2c_regs_t *I2Cx)
3011 {
3012 return (READ_BITS(I2Cx->DMA_CR, I2C_DMA_CR_TDMAE) == (I2C_DMA_CR_TDMAE));
3013 }
3014
3015 /**
3016 * @brief Enable DMA reception requests.
3017 *
3018 * Register|BitsName
3019 * --------|--------
3020 * IC_DMA_CR | RDMAE
3021 *
3022 * @param I2Cx I2C instance.
3023 * @retval None.
3024 */
ll_i2c_enable_dma_req_rx(i2c_regs_t * I2Cx)3025 __STATIC_INLINE void ll_i2c_enable_dma_req_rx(i2c_regs_t *I2Cx)
3026 {
3027 SET_BITS(I2Cx->DMA_CR, I2C_DMA_CR_RDMAE);
3028 }
3029
3030 /**
3031 * @brief Disable DMA reception requests.
3032 *
3033 * Register|BitsName
3034 * --------|--------
3035 * IC_DMA_CR | RDMAE
3036 *
3037 * @param I2Cx I2C instance.
3038 * @retval None.
3039 */
ll_i2c_disable_dma_req_rx(i2c_regs_t * I2Cx)3040 __STATIC_INLINE void ll_i2c_disable_dma_req_rx(i2c_regs_t *I2Cx)
3041 {
3042 CLEAR_BITS(I2Cx->DMA_CR, I2C_DMA_CR_RDMAE);
3043 }
3044
3045 /**
3046 * @brief Check if DMA reception requests are enabled or disabled.
3047 *
3048 * Register|BitsName
3049 * --------|--------
3050 * IC_DMA_CR | RDMAE
3051 *
3052 * @param I2Cx I2C instance.
3053 * @retval State of bit (1 or 0).
3054 */
ll_i2c_is_enabled_dma_req_rx(i2c_regs_t * I2Cx)3055 __STATIC_INLINE uint32_t ll_i2c_is_enabled_dma_req_rx(i2c_regs_t *I2Cx)
3056 {
3057 return (READ_BITS(I2Cx->DMA_CR, I2C_DMA_CR_RDMAE) == (I2C_DMA_CR_RDMAE));
3058 }
3059
3060 /**
3061 * @brief Set level of TX FIFO that requests a DMA transmit.
3062 * @note TX data level should equal to the watermark level, that is, the dma_tx_req
3063 * signal is generated when the number of valid data entries in the transmit
3064 * FIFO is equal to or below this field value, and TDMAE = 1.
3065 *
3066 * Register|BitsName
3067 * --------|--------
3068 * IC_DMA_TDLR | DMATDL
3069 *
3070 * @param I2Cx I2C instance
3071 * @param level This parameter should range between 0x0 and 0x8.
3072 * @retval None.
3073 */
ll_i2c_set_dma_tx_data_level(i2c_regs_t * I2Cx,uint32_t level)3074 __STATIC_INLINE void ll_i2c_set_dma_tx_data_level(i2c_regs_t *I2Cx, uint32_t level)
3075 {
3076 WRITE_REG(I2Cx->DMA_TDLR, level);
3077 }
3078
3079 /**
3080 * @brief Get level of TX FIFO that request a DMA transmit.
3081 *
3082 * Register|BitsName
3083 * --------|--------
3084 * IC_DMA_TDLR | DMATDL
3085 *
3086 * @param I2Cx I2C instance
3087 * @retval Returned value should range between 0x0 and 0x8.
3088 */
ll_i2c_get_dma_tx_data_level(i2c_regs_t * I2Cx)3089 __STATIC_INLINE uint32_t ll_i2c_get_dma_tx_data_level(i2c_regs_t *I2Cx)
3090 {
3091 return (uint32_t)(READ_BITS(I2Cx->DMA_TDLR, I2C_DMA_TDLR_DMATDL));
3092 }
3093
3094 /**
3095 * @brief Set level of RX FIFO that requests a DMA receive.
3096 * @note The watermark level = DMARDL + 1, that is, dma_rx_req is generated when
3097 * the number of valid data entries in the receive FIFO is equal to or
3098 * more than this field value + 1, and RDMAE = 1. For instance, when DMARDL
3099 * is 0, then dma_rx_req is asserted when 1 or more data entries are present
3100 * in the receive FIFO.
3101 *
3102 * Register|BitsName
3103 * --------|--------
3104 * IC_DMA_RDLR | DMARDL
3105 *
3106 * @param I2Cx I2C instance
3107 * @param level This parameter should range between 0x0 and 0x8.
3108 * @retval None.
3109 */
ll_i2c_set_dma_rx_data_level(i2c_regs_t * I2Cx,uint32_t level)3110 __STATIC_INLINE void ll_i2c_set_dma_rx_data_level(i2c_regs_t *I2Cx, uint32_t level)
3111 {
3112 WRITE_REG(I2Cx->DMA_RDLR, level);
3113 }
3114
3115 /**
3116 * @brief Get level of RX FIFO that request a DMA receive.
3117 *
3118 * Register|BitsName
3119 * --------|--------
3120 * IC_DMA_RDLR | DMARDL
3121 *
3122 * @param I2Cx I2C instance
3123 * @retval Returned value should range between 0x0 and 0x8.
3124 */
ll_i2c_get_dma_rx_data_level(i2c_regs_t * I2Cx)3125 __STATIC_INLINE uint32_t ll_i2c_get_dma_rx_data_level(i2c_regs_t *I2Cx)
3126 {
3127 return (uint32_t)(READ_BITS(I2Cx->DMA_RDLR, I2C_DMA_RDLR_DMARDL));
3128 }
3129
3130 /**
3131 * @brief Get the data register address used for DMA transfer
3132 *
3133 * Register|BitsName
3134 * --------|--------
3135 * IC_DATA_CMD | DAT
3136 *
3137 * @param I2Cx I2C instance
3138 * @retval Address of data register
3139 */
ll_i2c_dma_get_register_address(i2c_regs_t * I2Cx)3140 __STATIC_INLINE uint32_t ll_i2c_dma_get_register_address(i2c_regs_t *I2Cx)
3141 {
3142 return ((uint32_t) & (I2Cx->DATA_CMD));
3143 }
3144
3145 /** @} */
3146
3147 /** @defgroup I2C_LL_EF_Data_Management Data_Management
3148 * @{
3149 */
3150
3151 /**
3152 * @brief Configure the slave address for transfer (master mode).
3153 * @note The register IC_TAR can only be programmed when the I2C is disabled (ENABLE = 0).
3154 *
3155 * Register|BitsName
3156 * --------|--------
3157 * IC_TAR | TAR_ADDR
3158 *
3159 * @param I2Cx I2C instance.
3160 * @param slave_addr This parameter must be a value between 0x00 and 0x3F.
3161 * @retval None.
3162 */
ll_i2c_set_slave_address(i2c_regs_t * I2Cx,uint32_t slave_addr)3163 __STATIC_INLINE void ll_i2c_set_slave_address(i2c_regs_t *I2Cx, uint32_t slave_addr)
3164 {
3165 MODIFY_REG(I2Cx->TAR, I2C_TAR_ADDR, slave_addr << I2C_TAR_ADDR_Pos);
3166 }
3167
3168 /**
3169 * @brief Get the slave address programmed for transfer (master mode).
3170 *
3171 * Register|BitsName
3172 * --------|--------
3173 * IC_TAR | TAR_ADDR
3174 *
3175 * @param I2Cx I2C instance.
3176 * @retval Value between 0x0 and0x3F
3177 */
ll_i2c_get_slave_address(i2c_regs_t * I2Cx)3178 __STATIC_INLINE uint32_t ll_i2c_get_slave_address(i2c_regs_t *I2Cx)
3179 {
3180 return (uint32_t)(READ_BITS(I2Cx->TAR, I2C_TAR_ADDR) >> I2C_TAR_ADDR_Pos);
3181 }
3182
3183 /**
3184 * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
3185 * @note The register IC_CON and IC_TAR can only be programmed when the I2C is disabled (ENABLE = 0).
3186 *
3187 * Register|BitsName
3188 * --------|--------
3189 * IC_CON | CON_10BITADDR_MST
3190 * IC_TAR | TAR_ADDR
3191 *
3192 * @param I2Cx I2C instance.
3193 * @param slave_addr Specifies the slave address to be programmed.
3194 * @param slave_addr_size This parameter can be one of the following values:
3195 * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
3196 * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
3197 * @note SlaveAddrSize in IC_CON register can only be programmed when the I2C is disabled (IC_ENABLE = 0).
3198 * @retval None.
3199 */
ll_i2c_handle_transfer(i2c_regs_t * I2Cx,uint32_t slave_addr,uint32_t slave_addr_size)3200 __STATIC_INLINE void ll_i2c_handle_transfer(i2c_regs_t *I2Cx, uint32_t slave_addr, uint32_t slave_addr_size)
3201 {
3202 MODIFY_REG(I2Cx->TAR, I2C_TAR_ADDR, slave_addr << I2C_TAR_ADDR_Pos);
3203 ll_i2c_set_master_addressing_mode(I2Cx, slave_addr_size);
3204 }
3205
3206 /**
3207 * @brief Indicate the value of transfer direction (slave mode).
3208 * @note RESET: Write transfer, Slave enters in receiver mode.
3209 * SET: Read transfer, Slave enters in transmitter mode.
3210 *
3211 * Register|BitsName
3212 * --------|--------
3213 * IC_RAW_INTR_STAT | INTR_RD_REQ
3214 * IC_RAW_INTR_STAT | INTR_RX_FULL
3215 *
3216 * @param I2Cx I2C instance.
3217 * @retval Returned value can be one of the following values:
3218 * @arg @ref LL_I2C_DIRECTION_WRITE
3219 * @arg @ref LL_I2C_DIRECTION_READ
3220 */
ll_i2c_get_transfer_direction(i2c_regs_t * I2Cx)3221 __STATIC_INLINE uint32_t ll_i2c_get_transfer_direction(i2c_regs_t *I2Cx)
3222 {
3223 return (uint32_t)(READ_BITS(I2Cx->RAW_INTR_STAT, I2C_INTR_RD_REQ | I2C_INTR_RX_FULL));
3224 }
3225
3226 /**
3227 * @brief Read Receive Data register.
3228 *
3229 * Register|BitsName
3230 * --------|--------
3231 * IC_DATA_CMD | DAT
3232 *
3233 * @param I2Cx I2C instance.
3234 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
3235 */
ll_i2c_receive_data8(i2c_regs_t * I2Cx)3236 __STATIC_INLINE uint8_t ll_i2c_receive_data8(i2c_regs_t *I2Cx)
3237 {
3238 return (uint8_t)(READ_BITS(I2Cx->DATA_CMD, I2C_DATA_CMD_DAT));
3239 }
3240
3241 /**
3242 * @brief Write in Transmit Data Register .
3243 *
3244 * Register|BitsName
3245 * --------|--------
3246 * IC_DATA_CMD | STOP
3247 * IC_DATA_CMD | CMD
3248 * IC_DATA_CMD | DAT
3249 *
3250 * @param I2Cx I2C instance.
3251 * @param data Value range between 0x00 and 0xFF.
3252 * @param cmd This parameter can be one of the following values:
3253 * @arg @ref LL_I2C_CMD_SLV_NONE
3254 * @arg @ref LL_I2C_CMD_MST_WRITE
3255 * @arg @ref LL_I2C_CMD_MST_READ
3256 * @arg @ref LL_I2C_CMD_MST_GEN_STOP
3257 * @arg @ref LL_I2C_CMD_MST_GEN_RESTART
3258 * @retval None.
3259 */
ll_i2c_transmit_data8(i2c_regs_t * I2Cx,uint8_t data,uint32_t cmd)3260 __STATIC_INLINE void ll_i2c_transmit_data8(i2c_regs_t *I2Cx, uint8_t data, uint32_t cmd)
3261 {
3262 WRITE_REG(I2Cx->DATA_CMD, data | cmd);
3263 }
3264
3265 /** @} */
3266
3267 /** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
3268 * @{
3269 */
3270
3271 /**
3272 * @brief De-initialize I2C registers (Registers restored to their default values).
3273 * @param I2Cx I2C instance
3274 * @retval An error_status_t enumeration value:
3275 * - SUCCESS: I2C registers are de-initialized
3276 * - ERROR: I2C registers are not de-initialized
3277 */
3278 error_status_t ll_i2c_deinit(i2c_regs_t *I2Cx);
3279
3280 /**
3281 * @brief Initialize I2C registers according to the specified
3282 * parameters in p_i2c_init.
3283 * @param I2Cx I2C instance
3284 * @param p_i2c_init Pointer to a ll_i2c_init_t structure that contains the configuration
3285 * information for the specified I2C peripheral.
3286 * @retval An error_status_t enumeration value:
3287 * - SUCCESS: I2C registers are initialized according to p_i2c_init content
3288 * - ERROR: Problem occurred during I2C Registers initialization
3289 */
3290 error_status_t ll_i2c_init(i2c_regs_t *I2Cx, ll_i2c_init_t *p_i2c_init);
3291
3292 /**
3293 * @brief Set each field of a @ref ll_i2c_init_t type structure to default value.
3294 * @param p_i2c_init Pointer to a @ref ll_i2c_init_t structure
3295 * whose fields will be set to default values.
3296 * @retval None
3297 */
3298 void ll_i2c_struct_init(ll_i2c_init_t *p_i2c_init);
3299
3300 /** @} */
3301
3302 /** @} */
3303
3304 #endif /* I2C0 || I2C1 */
3305
3306 #ifdef __cplusplus
3307 }
3308 #endif
3309
3310 #endif /* __GR55xx_LL_I2C_H__ */
3311
3312 /** @} */
3313
3314 /** @} */
3315
3316 /** @} */
3317