1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_msio.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of MSIO LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_MSIO MSIO
47 * @brief MSIO LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55XX_LL_MSIO_H__
53 #define __GR55XX_LL_MSIO_H__
54
55 /* Includes ------------------------------------------------------------------*/
56 #include "gr55xx.h"
57
58 #ifdef __cplusplus
59 extern "C" {
60 #endif
61
62 #if defined(AON)
63
64 /** @defgroup MSIO_LL_STRUCTURES Structures
65 * @{
66 */
67
68 /* Exported types ------------------------------------------------------------*/
69 /** @defgroup MSIO_LL_ES_INIT MSIO Exported init structures
70 * @{
71 */
72
73 /**
74 * @brief LL MSIO init Structure definition
75 */
76 typedef struct _ll_msio_init {
77 uint32_t pin; /**< Specifies the MSIO pins to be MSIO_InitStructured.
78 This parameter can be any value of @ref MSIO_LL_EC_PIN */
79
80 uint32_t direction; /**< Specifies the direction for the selected pins.
81 This parameter can be a value of @ref MSIO_LL_EC_DIRECTION.
82 MSIO HW MSIO_InitStructuration can be
83 modified afterwards using unitary
84 function
85 @ref ll_msio_set_pin_direction(). */
86
87 uint32_t mode; /**< Specifies the operating mode for the selected pins.
88 This parameter can be a value of @ref MSIO_LL_EC_MODE.
89 MSIO HW MSIO_InitStructuration can be
90 modified afterwards using unitary
91 function
92 @ref ll_msio_set_pin_mode(). */
93
94 uint32_t pull; /**< Specifies the operating Pull-up/Pull down for the selected pins.
95 This parameter can be a value of @ref MSIO_LL_EC_PULL.
96 MSIO HW configuration can be modified
97 afterwards using unitary function
98 @ref ll_msio_set_pin_pull(). */
99
100 uint32_t mux; /*!< Specifies the Peripheral to be connected to the selected pins.
101 This parameter can be a value of @ref MSIO_LL_EC_MUX.
102 GPIO HW MSIO_InitStructuration can be
103 modified afterwards using unitary
104 function
105 @ref ll_msio_set_pin_mux(). */
106 } ll_msio_init_t;
107
108 /** @} */
109
110 /** @} */
111
112 /**
113 * @defgroup MSIO_LL_MACRO Defines
114 * @{
115 */
116
117 /* Exported constants --------------------------------------------------------*/
118 /** @defgroup MSIO_LL_Exported_Constants MSIO Exported Constants
119 * @{
120 */
121
122 /** @defgroup MSIO_LL_EC_PIN PIN
123 * @{
124 */
125 #define LL_MSIO_PIN_0 ((uint32_t)0x01U) /**< Select pin 0 */
126 #define LL_MSIO_PIN_1 ((uint32_t)0x02U) /**< Select pin 1 */
127 #define LL_MSIO_PIN_2 ((uint32_t)0x04U) /**< Select pin 2 */
128 #define LL_MSIO_PIN_3 ((uint32_t)0x08U) /**< Select pin 3 */
129 #define LL_MSIO_PIN_4 ((uint32_t)0x10U) /**< Select pin 4 */
130 #define LL_MSIO_PIN_ALL ((uint32_t)0x1FU) /**< Select all pins */
131 /** @} */
132
133 /** @defgroup MSIO_LL_EC_DIRECTION Direction
134 * @{
135 */
136 #define LL_MSIO_DIRECTION_NONE ((uint32_t)0x0U) /**< Disable input/output */
137 #define LL_MSIO_DIRECTION_INPUT ((uint32_t)0x1U) /**< Enable input */
138 #define LL_MSIO_DIRECTION_OUTPUT ((uint32_t)0x2U) /**< Enable output */
139 #define LL_MSIO_DIRECTION_INOUT ((uint32_t)0x3U) /**< Enable input&output */
140 /** @} */
141
142 /** @defgroup MSIO_LL_EC_MODE Mode
143 * @{
144 */
145 #define LL_MSIO_MODE_ANALOG ((uint32_t)0x0U) /**< Select analog mode */
146 #define LL_MSIO_MODE_DIGITAL ((uint32_t)0x1U) /**< Enable digital mode */
147 /** @} */
148
149 /** @defgroup MSIO_LL_EC_PULL Pull Up Pull Down
150 * @{
151 */
152 #define LL_MSIO_PULL_NO ((uint32_t)0x0U) /**< Select I/O no pull */
153 #define LL_MSIO_PULL_UP ((uint32_t)0x1U) /**< Select I/O pull up */
154 #define LL_MSIO_PULL_DOWN ((uint32_t)0x2U) /**< Select I/O pull down */
155 /** @} */
156
157 /** @defgroup MSIO_LL_EC_MUX Alternate Function
158 * @{
159 */
160 #define LL_MSIO_MUX_0 ((uint32_t)0x0U) /*!< Select alternate function 0 */
161 #define LL_MSIO_MUX_1 ((uint32_t)0x1U) /*!< Select alternate function 1 */
162 #define LL_MSIO_MUX_2 ((uint32_t)0x2U) /*!< Select alternate function 2 */
163 #define LL_MSIO_MUX_3 ((uint32_t)0x3U) /*!< Select alternate function 3 */
164 #define LL_MSIO_MUX_4 ((uint32_t)0x4U) /*!< Select alternate function 4 */
165 #define LL_MSIO_MUX_5 ((uint32_t)0x5U) /*!< Select alternate function 5 */
166 #define LL_MSIO_MUX_6 ((uint32_t)0x6U) /*!< Select alternate function 6 */
167 #define LL_MSIO_MUX_7 ((uint32_t)0x7U) /*!< Select alternate function 7 */
168 /** @} */
169
170 /** @} */
171
172 /* Exported macro ------------------------------------------------------------*/
173 /** @defgroup MSIO_LL_Exported_Macros MSIO Exported Macros
174 * @{
175 */
176
177 /** @defgroup MSIO_LL_EM_WRITE_READ Common Write and read registers Macros
178 * @{
179 */
180
181 /**
182 * @brief Write a value in MSIO register
183 * @param __instance__ MSIO instance
184 * @param __REG__ Register to be written
185 * @param __VALUE__ Value to be written in the register
186 * @retval None
187 */
188 #define LL_MSIO_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
189
190 /**
191 * @brief Read a value in MSIO register
192 * @param __instance__ MSIO instance
193 * @param __REG__ Register to be read
194 * @retval Register value
195 */
196 #define LL_MSIO_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
197
198 /** @} */
199
200 /** @} */
201
202 /* Private types -------------------------------------------------------------*/
203 /* Private variables ---------------------------------------------------------*/
204 /* Private constants ---------------------------------------------------------*/
205 /* Private macros ------------------------------------------------------------*/
206 /** @defgroup MSIO_LL_Private_Macros MSIO Private Macros
207 * @{
208 */
209
210 /** @defgroup MSIO_LL_EC_DEFAULT_CONFIG InitStruct default configuartion
211 * @{
212 */
213
214 /**
215 * @brief LL MSIO InitStrcut default configuartion
216 */
217 #define LL_MSIO_DEFAULT_CONFIG \
218 { \
219 .pin = LL_MSIO_PIN_ALL, \
220 .direction = LL_MSIO_DIRECTION_INPUT, \
221 .mode = LL_MSIO_MODE_DIGITAL, \
222 .pull = LL_MSIO_PULL_DOWN, \
223 .mux = LL_MSIO_MUX_7, \
224 }
225 /** @} */
226
227 /** @} */
228
229 /** @} */
230
231 /* Exported functions --------------------------------------------------------*/
232 /** @defgroup MSIO_LL_DRIVER_FUNCTIONS Functions
233 * @{
234 */
235
236 /** @defgroup MSIO_LL_EF_Port_Configuration Port Configuration
237 * @{
238 */
239
240 /**
241 * @brief Set several MSIO pins to input/output direction.
242 *
243 * Register|BitsName
244 * --------|--------
245 * MSIO_PAD_CFG_0 | OE_N
246 * MSIO_PAD_CFG_0 | IE_N
247 *
248 * @param pin_mask This parameter can be a combination of the following values:
249 * @arg @ref LL_MSIO_PIN_0
250 * @arg @ref LL_MSIO_PIN_1
251 * @arg @ref LL_MSIO_PIN_2
252 * @arg @ref LL_MSIO_PIN_3
253 * @arg @ref LL_MSIO_PIN_4
254 * @arg @ref LL_MSIO_PIN_ALL
255 * @param direction This parameter can be one of the following values:
256 * @arg @ref LL_MSIO_DIRECTION_NONE
257 * @arg @ref LL_MSIO_DIRECTION_INPUT
258 * @arg @ref LL_MSIO_DIRECTION_OUTPUT
259 * @arg @ref LL_MSIO_DIRECTION_INOUT
260 * @retval None
261 */
ll_msio_set_pin_direction(uint32_t pin_mask,uint32_t direction)262 __STATIC_INLINE void ll_msio_set_pin_direction(uint32_t pin_mask, uint32_t direction)
263 {
264 uint32_t oe_mask = (pin_mask << AON_MSIO_PAD_CFG_0_OE_N_Pos) & AON_MSIO_PAD_CFG_0_OE_N;
265 uint32_t ie_mask = (pin_mask << AON_MSIO_PAD_CFG_0_IE_N_Pos) & AON_MSIO_PAD_CFG_0_IE_N;
266 if (direction != LL_MSIO_DIRECTION_NONE) {
267 if (direction != LL_MSIO_DIRECTION_INOUT) {
268 MODIFY_REG(AON->MSIO_PAD_CFG_0, (ie_mask | oe_mask), \
269 (direction != LL_MSIO_DIRECTION_INPUT) ? ie_mask : oe_mask);
270 } else {
271 CLEAR_BITS(AON->MSIO_PAD_CFG_0, (ie_mask | oe_mask));
272 }
273 } else {
274 SET_BITS(AON->MSIO_PAD_CFG_0, (ie_mask | oe_mask));
275 }
276 }
277
278 /**
279 * @brief Return gpio direction for a MSIO pin.
280 * @note I/O direction can be Input direction, General purpose output.
281 * @note Warning: only one pin can be passed as parameter.
282 *
283 * Register|BitsName
284 * --------|--------
285 * MSIO_PAD_CFG_0 | OE_N
286 * MSIO_PAD_CFG_0 | IE_N
287 *
288 * @param pin This parameter can be one of the following values:
289 * @arg @ref LL_MSIO_PIN_0
290 * @arg @ref LL_MSIO_PIN_1
291 * @arg @ref LL_MSIO_PIN_2
292 * @arg @ref LL_MSIO_PIN_3
293 * @arg @ref LL_MSIO_PIN_4
294 * @retval Returned value can be one of the following values:
295 * @arg @ref LL_MSIO_DIRECTION_NONE
296 * @arg @ref LL_MSIO_DIRECTION_INPUT
297 * @arg @ref LL_MSIO_DIRECTION_OUTPUT
298 * @arg @ref LL_MSIO_DIRECTION_INOUT
299 */
ll_msio_get_pin_direction(uint32_t pin)300 __STATIC_INLINE uint32_t ll_msio_get_pin_direction(uint32_t pin)
301 {
302 uint32_t oe_mask = (pin << AON_MSIO_PAD_CFG_0_OE_N_Pos) & AON_MSIO_PAD_CFG_0_OE_N;
303 uint32_t ie_mask = (pin << AON_MSIO_PAD_CFG_0_IE_N_Pos) & AON_MSIO_PAD_CFG_0_IE_N;
304 uint32_t mask = READ_BITS(AON->MSIO_PAD_CFG_0, (ie_mask | oe_mask));
305 if (mask == (ie_mask | oe_mask)) {
306 return LL_MSIO_DIRECTION_NONE;
307 } else {
308 if (mask == 0) {
309 return LL_MSIO_DIRECTION_INOUT;
310 } else {
311 return ((mask == ie_mask) ? LL_MSIO_DIRECTION_OUTPUT : LL_MSIO_DIRECTION_INPUT);
312 }
313 }
314 }
315
316 /**
317 * @brief Set several MSIO pins to analog/digital mode.
318 *
319 * Register|BitsName
320 * --------|--------
321 * MSIO_PAD_CFG_1 | AE_N
322 *
323 * @param pin_mask This parameter can be a combination of the following values:
324 * @arg @ref LL_MSIO_PIN_0
325 * @arg @ref LL_MSIO_PIN_1
326 * @arg @ref LL_MSIO_PIN_2
327 * @arg @ref LL_MSIO_PIN_3
328 * @arg @ref LL_MSIO_PIN_4
329 * @arg @ref LL_MSIO_PIN_ALL
330 * @param mode This parameter can be one of the following values:
331 * @arg @ref LL_MSIO_MODE_ANALOG
332 * @arg @ref LL_MSIO_MODE_DIGITAL
333 * @retval None
334 */
ll_msio_set_pin_mode(uint32_t pin_mask,uint32_t mode)335 __STATIC_INLINE void ll_msio_set_pin_mode(uint32_t pin_mask, uint32_t mode)
336 {
337 uint32_t ae_mask = (pin_mask << AON_MSIO_PAD_CFG_1_AE_N_Pos) & AON_MSIO_PAD_CFG_1_AE_N;
338 uint32_t ae_n = (mode != LL_MSIO_MODE_DIGITAL) ? 0U : ae_mask;
339 GLOBAL_EXCEPTION_DISABLE();
340 MODIFY_REG(AON->MSIO_PAD_CFG_1, ae_mask, ae_n);
341 GLOBAL_EXCEPTION_ENABLE();
342 }
343
344 /**
345 * @brief Return gpio mode for a MSIO pin.
346 * @note I/O mode can be analog or digital.
347 * @note Warning: only one pin can be passed as parameter.
348 *
349 * Register|BitsName
350 * --------|--------
351 * MSIO_PAD_CFG_1 | AE_N
352 *
353 * @param pin This parameter can be one of the following values:
354 * @arg @ref LL_MSIO_PIN_0
355 * @arg @ref LL_MSIO_PIN_1
356 * @arg @ref LL_MSIO_PIN_2
357 * @arg @ref LL_MSIO_PIN_3
358 * @arg @ref LL_MSIO_PIN_4
359 * @retval Returned value can be one of the following values:
360 * @arg @ref LL_MSIO_MODE_ANALOG
361 * @arg @ref LL_MSIO_MODE_DIGITAL
362 */
ll_msio_get_pin_mode(uint32_t pin)363 __STATIC_INLINE uint32_t ll_msio_get_pin_mode(uint32_t pin)
364 {
365 uint32_t ae_mask = (pin << AON_MSIO_PAD_CFG_1_AE_N_Pos) & AON_MSIO_PAD_CFG_1_AE_N;
366 return ((READ_BITS(AON->MSIO_PAD_CFG_1, ae_mask) == ae_mask) ? LL_MSIO_MODE_DIGITAL : LL_MSIO_MODE_ANALOG);
367 }
368
369 /**
370 * @brief Configure gpio pull-up or pull-down for a dedicated MSIO pin.
371 *
372 * Register|BitsName
373 * --------|--------
374 * MSIO_PAD_CFG_0 | RE_N
375 * MSIO_PAD_CFG_1 | RTYPE
376 *
377 * @param pin_mask This parameter can be a combination of the following values:
378 * @arg @ref LL_MSIO_PIN_0
379 * @arg @ref LL_MSIO_PIN_1
380 * @arg @ref LL_MSIO_PIN_2
381 * @arg @ref LL_MSIO_PIN_3
382 * @arg @ref LL_MSIO_PIN_4
383 * @arg @ref LL_MSIO_PIN_ALL
384 * @param pull This parameter can be one of the following values:
385 * @arg @ref LL_MSIO_PULL_NO
386 * @arg @ref LL_MSIO_PULL_UP
387 * @arg @ref LL_MSIO_PULL_DOWN
388 * @retval None
389 */
ll_msio_set_pin_pull(uint32_t pin_mask,uint32_t pull)390 __STATIC_INLINE void ll_msio_set_pin_pull(uint32_t pin_mask, uint32_t pull)
391 {
392 if (pull != LL_MSIO_PULL_NO) {
393 uint32_t rtype_mask = (pin_mask << AON_MSIO_PAD_CFG_1_RTYPE_Pos) & AON_MSIO_PAD_CFG_1_RTYPE;
394 uint32_t rtype = (pull != LL_MSIO_PULL_UP) ? 0U : rtype_mask;
395 CLEAR_BITS(AON->MSIO_PAD_CFG_0, (pin_mask << AON_MSIO_PAD_CFG_0_RE_N_Pos) & AON_MSIO_PAD_CFG_0_RE_N);
396 GLOBAL_EXCEPTION_DISABLE();
397 MODIFY_REG(AON->MSIO_PAD_CFG_1, rtype_mask, rtype);
398 GLOBAL_EXCEPTION_ENABLE();
399 } else {
400 SET_BITS(AON->MSIO_PAD_CFG_0, (pin_mask << AON_MSIO_PAD_CFG_0_RE_N_Pos) & AON_MSIO_PAD_CFG_0_RE_N);
401 }
402 }
403
404 /**
405 * @brief Return gpio pull-up or pull-down for a dedicated MSIO pin.
406 * @note Warning: only one pin can be passed as parameter.
407 *
408 * Register|BitsName
409 * --------|--------
410 * MSIO_PAD_CFG_0 | RE_N
411 * MSIO_PAD_CFG_1 | RTYPE
412 *
413 * @param pin This parameter can be one of the following values:
414 * @arg @ref LL_MSIO_PIN_0
415 * @arg @ref LL_MSIO_PIN_1
416 * @arg @ref LL_MSIO_PIN_2
417 * @arg @ref LL_MSIO_PIN_3
418 * @arg @ref LL_MSIO_PIN_4
419 * @retval Returned value can be one of the following values:
420 * @arg @ref LL_MSIO_PULL_NO
421 * @arg @ref LL_MSIO_PULL_UP
422 * @arg @ref LL_MSIO_PULL_DOWN
423 */
ll_msio_get_pin_pull(uint32_t pin)424 __STATIC_INLINE uint32_t ll_msio_get_pin_pull(uint32_t pin)
425 {
426 if (READ_BITS(AON->MSIO_PAD_CFG_0, (pin << AON_MSIO_PAD_CFG_0_RE_N_Pos) & AON_MSIO_PAD_CFG_0_RE_N)) {
427 return LL_MSIO_PULL_NO;
428 } else {
429 uint32_t rtype_mask = (pin << AON_MSIO_PAD_CFG_1_RTYPE_Pos) & AON_MSIO_PAD_CFG_1_RTYPE;
430 return ((READ_BITS(AON->MSIO_PAD_CFG_1, rtype_mask) != RESET) ? LL_MSIO_PULL_UP : LL_MSIO_PULL_DOWN);
431 }
432 }
433
434 /**
435 * @brief Configure gpio pinmux number of a dedicated pin from 0 to 4 for a dedicated port.
436 * @note Possible values are from AF0 to AF7 depending on target.
437 * @note Warning: only one pin can be passed as parameter.
438 *
439 * Register|BitsName
440 * --------|--------
441 * MSIO_PAD_MUX_CTL | CTL_00_04
442 * MSIO_PAD_CFG_1 | MCU_OVR
443 *
444 * @param pin This parameter can be one of the following values:
445 * @arg @ref LL_MSIO_PIN_0
446 * @arg @ref LL_MSIO_PIN_1
447 * @arg @ref LL_MSIO_PIN_2
448 * @arg @ref LL_MSIO_PIN_3
449 * @arg @ref LL_MSIO_PIN_4
450 * @param mux This parameter can be one of the following values:
451 * @arg @ref LL_MSIO_MUX_0
452 * @arg @ref LL_MSIO_MUX_1
453 * @arg @ref LL_MSIO_MUX_2
454 * @arg @ref LL_MSIO_MUX_3
455 * @arg @ref LL_MSIO_MUX_4
456 * @arg @ref LL_MSIO_MUX_5
457 * @arg @ref LL_MSIO_MUX_6
458 * @arg @ref LL_MSIO_MUX_7
459 * @retval None
460 */
ll_msio_set_pin_mux(uint32_t pin,uint32_t mux)461 __STATIC_INLINE void ll_msio_set_pin_mux(uint32_t pin, uint32_t mux)
462 {
463 uint32_t pos = POSITION_VAL(pin) << 2;
464 if (LL_MSIO_MUX_7 == mux) {
465 GLOBAL_EXCEPTION_DISABLE();
466 CLEAR_BITS(AON->MSIO_PAD_CFG_1, pin << AON_MSIO_PAD_CFG_1_MCU_OVR_Pos);
467 GLOBAL_EXCEPTION_ENABLE();
468 } else {
469 MODIFY_REG(MCU_SUB->MSIO_PAD_MUX_CTL, 0xF << pos, mux << pos);
470 GLOBAL_EXCEPTION_DISABLE();
471 SET_BITS(AON->MSIO_PAD_CFG_1, pin << AON_MSIO_PAD_CFG_1_MCU_OVR_Pos);
472 GLOBAL_EXCEPTION_ENABLE();
473 }
474 }
475
476 /**
477 * @brief Return gpio alternate function of a dedicated pin from 0 to 4 for a dedicated port.
478 *
479 * Register|BitsName
480 * --------|--------
481 * MSIO_PAD_MUX_CTL | CTL_00_04
482 * MSIO_PAD_CFG_1 | MCU_OVR
483 *
484 * @param pin This parameter can be one of the following values:
485 * @arg @ref LL_MSIO_PIN_0
486 * @arg @ref LL_MSIO_PIN_1
487 * @arg @ref LL_MSIO_PIN_2
488 * @arg @ref LL_MSIO_PIN_3
489 * @arg @ref LL_MSIO_PIN_4
490 * @retval Returned value can be one of the following values:
491 * @arg @ref LL_MSIO_MUX_0
492 * @arg @ref LL_MSIO_MUX_1
493 * @arg @ref LL_MSIO_MUX_2
494 * @arg @ref LL_MSIO_MUX_3
495 * @arg @ref LL_MSIO_MUX_4
496 * @arg @ref LL_MSIO_MUX_5
497 * @arg @ref LL_MSIO_MUX_6
498 * @arg @ref LL_MSIO_MUX_7
499 */
ll_msio_get_pin_mux(uint32_t pin)500 __STATIC_INLINE uint32_t ll_msio_get_pin_mux(uint32_t pin)
501 {
502 if (READ_BITS(AON->MSIO_PAD_CFG_1, pin << AON_MSIO_PAD_CFG_1_MCU_OVR_Pos)) {
503 uint32_t pos = POSITION_VAL(pin) << 2;
504 return (READ_BITS(MCU_SUB->MSIO_PAD_MUX_CTL, 0xF << pos) >> pos);
505 } else {
506 return LL_MSIO_MUX_7;
507 }
508 }
509
510 /** @} */
511
512 /** @defgroup MSIO_LL_EF_Data_Access Data Access
513 * @{
514 */
515
516 /**
517 * @brief Return full input data register value of MSIO.
518 *
519 * Register|BitsName
520 * --------|--------
521 * MSIO_REG0 | MSIO_C
522 *
523 * @retval Input data register value of port
524 */
ll_msio_read_input_port(void)525 __STATIC_INLINE uint32_t ll_msio_read_input_port(void)
526 {
527 return (uint32_t)(READ_BITS(MCU_SUB->MSIO_REG0, MCU_SUB_MSIO_REG0_MSIO_C));
528 }
529
530 /**
531 * @brief Return if input data level of several MSIO pins is high or low.
532 *
533 * Register|BitsName
534 * --------|--------
535 * MSIO_REG0 | MSIO_C
536 *
537 * @param pin_mask This parameter can be a combination of the following values:
538 * @arg @ref LL_MSIO_PIN_0
539 * @arg @ref LL_MSIO_PIN_1
540 * @arg @ref LL_MSIO_PIN_2
541 * @arg @ref LL_MSIO_PIN_3
542 * @arg @ref LL_MSIO_PIN_4
543 * @arg @ref LL_MSIO_PIN_ALL
544 * @retval State of bit (1 or 0).
545 */
ll_msio_is_input_pin_set(uint32_t pin_mask)546 __STATIC_INLINE uint32_t ll_msio_is_input_pin_set(uint32_t pin_mask)
547 {
548 return (uint32_t)(READ_BITS(MCU_SUB->MSIO_REG0, pin_mask) == pin_mask);
549 }
550
551 /**
552 * @brief Write output data register of MSIO.
553 *
554 * Register|BitsName
555 * --------|--------
556 * MSIO_PAD_CFG_0 | IN
557 *
558 * @param port_value Level value for each pin of the port
559 * @retval None
560 */
ll_msio_write_output_port(uint32_t port_value)561 __STATIC_INLINE void ll_msio_write_output_port(uint32_t port_value)
562 {
563 MODIFY_REG(AON->MSIO_PAD_CFG_0, AON_MSIO_PAD_CFG_0_IN, \
564 (port_value << AON_MSIO_PAD_CFG_0_IN_Pos) & AON_MSIO_PAD_CFG_0_IN);
565 }
566
567 /**
568 * @brief Return full output data register value of MSIO.
569 *
570 * Register|BitsName
571 * --------|--------
572 * MSIO_PAD_CFG_0 | IN
573 *
574 * @retval Output data register value of port
575 */
ll_msio_read_output_port(void)576 __STATIC_INLINE uint32_t ll_msio_read_output_port(void)
577 {
578 return (uint32_t)(READ_BITS(AON->MSIO_PAD_CFG_0, AON_MSIO_PAD_CFG_0_IN) >> AON_MSIO_PAD_CFG_0_IN_Pos);
579 }
580
581 /**
582 * @brief Return if input data level of several MSIO pins is high or low.
583 *
584 * Register|BitsName
585 * --------|--------
586 * MSIO_PAD_CFG_0 | IN
587 *
588 * @param pin_mask This parameter can be a combination of the following values:
589 * @arg @ref LL_MSIO_PIN_0
590 * @arg @ref LL_MSIO_PIN_1
591 * @arg @ref LL_MSIO_PIN_2
592 * @arg @ref LL_MSIO_PIN_3
593 * @arg @ref LL_MSIO_PIN_4
594 * @arg @ref LL_MSIO_PIN_ALL
595 * @retval State of bit (1 or 0).
596 */
ll_msio_is_output_pin_set(uint32_t pin_mask)597 __STATIC_INLINE uint32_t ll_msio_is_output_pin_set(uint32_t pin_mask)
598 {
599 pin_mask = (pin_mask << AON_MSIO_PAD_CFG_0_IN_Pos) & AON_MSIO_PAD_CFG_0_IN;
600 return (uint32_t)(READ_BITS(AON->MSIO_PAD_CFG_0, pin_mask) == pin_mask);
601 }
602
603 /**
604 * @brief Set specified MSIO pins to high level
605 *
606 * Register|BitsName
607 * --------|--------
608 * MSIO_PAD_CFG_0 | IN
609 *
610 * @param pin_mask This parameter can be a combination of the following values:
611 * @arg @ref LL_MSIO_PIN_0
612 * @arg @ref LL_MSIO_PIN_1
613 * @arg @ref LL_MSIO_PIN_2
614 * @arg @ref LL_MSIO_PIN_3
615 * @arg @ref LL_MSIO_PIN_4
616 * @arg @ref LL_MSIO_PIN_ALL
617 * @retval None
618 */
ll_msio_set_output_pin(uint32_t pin_mask)619 __STATIC_INLINE void ll_msio_set_output_pin(uint32_t pin_mask)
620 {
621 SET_BITS(AON->MSIO_PAD_CFG_0, (pin_mask << AON_MSIO_PAD_CFG_0_IN_Pos) & AON_MSIO_PAD_CFG_0_IN);
622 }
623
624 /**
625 * @brief Set specified MSIO pins to low level.
626 *
627 * Register|BitsName
628 * --------|--------
629 * MSIO_PAD_CFG_0 | IN
630 *
631 * @param pin_mask This parameter can be a combination of the following values:
632 * @arg @ref LL_MSIO_PIN_0
633 * @arg @ref LL_MSIO_PIN_1
634 * @arg @ref LL_MSIO_PIN_2
635 * @arg @ref LL_MSIO_PIN_3
636 * @arg @ref LL_MSIO_PIN_4
637 * @arg @ref LL_MSIO_PIN_ALL
638 * @retval None
639 */
ll_msio_reset_output_pin(uint32_t pin_mask)640 __STATIC_INLINE void ll_msio_reset_output_pin(uint32_t pin_mask)
641 {
642 CLEAR_BITS(AON->MSIO_PAD_CFG_0, (pin_mask << AON_MSIO_PAD_CFG_0_IN_Pos) & AON_MSIO_PAD_CFG_0_IN);
643 }
644
645 /**
646 * @brief Toggle data value of specified MSIO pins.
647 *
648 * Register|BitsName
649 * --------|--------
650 * MSIO_PAD_CFG_0 | IN
651 *
652 * @param pin_mask This parameter can be a combination of the following values:
653 * @arg @ref LL_MSIO_PIN_0
654 * @arg @ref LL_MSIO_PIN_1
655 * @arg @ref LL_MSIO_PIN_2
656 * @arg @ref LL_MSIO_PIN_3
657 * @arg @ref LL_MSIO_PIN_4
658 * @arg @ref LL_MSIO_PIN_ALL
659 * @retval None
660 */
ll_msio_toggle_pin(uint32_t pin_mask)661 __STATIC_INLINE void ll_msio_toggle_pin(uint32_t pin_mask)
662 {
663 WRITE_REG(AON->MSIO_PAD_CFG_0, \
664 (READ_REG(AON->MSIO_PAD_CFG_0) ^ ((pin_mask << AON_MSIO_PAD_CFG_0_IN_Pos) & AON_MSIO_PAD_CFG_0_IN)));
665 }
666
667 /** @} */
668
669 /** @defgroup MSIO_LL_EF_Init Initialization and de-initialization functions
670 * @{
671 */
672
673 /**
674 * @brief De-initialize MSIO registers (Registers restored to their default values).
675 * @retval An error_status_t enumeration value:
676 * - SUCCESS: MSIO registers are de-initialized
677 * - ERROR: MSIO registers are not de-initialized
678 */
679 error_status_t ll_msio_deinit(void);
680
681 /**
682 * @brief Initialize MSIO registers according to the specified.
683 * parameters in p_msio_init.
684 * @param p_msio_init Pointer to a ll_msio_init_t structure that contains the configuration
685 * information for the specified MSIO peripheral.
686 * @retval An error_status_t enumeration value:
687 * - SUCCESS: MSIO registers are initialized according to p_msio_init content
688 * - ERROR: Problem occurred during MSIO Registers initialization
689 */
690 error_status_t ll_msio_init(ll_msio_init_t *p_msio_init);
691
692 /**
693 * @brief Set each field of a @ref ll_msio_init_t type structure to default value.
694 * @param p_msio_init Pointer to a @ref ll_msio_init_t structure
695 * whose fields will be set to default values.
696 * @retval None
697 */
698 void ll_msio_struct_init(ll_msio_init_t *p_msio_init);
699
700 /** @} */
701
702 /** @} */
703
704 #endif /* AON */
705
706 #ifdef __cplusplus
707 }
708 #endif
709
710 #endif /* __GR55XX_LL_MSIO_H__ */
711
712 /** @} */
713
714 /** @} */
715
716 /** @} */
717