1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_pwm.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of PWM LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_PWM PWM
47 * @brief PWM LL module driver.
48 * @{
49 */
50
51 #ifndef __GR55XX_LL_PWM_H__
52 #define __GR55XX_LL_PWM_H__
53
54 #include "gr55xx.h"
55
56 #ifdef __cplusplus
57 extern "C" {
58 #endif
59
60 #if defined (PWM0) || defined (PWM1)
61
62 /** @defgroup PWM_LL_STRUCTURES Structures
63 * @{
64 */
65
66 /* Exported types ------------------------------------------------------------*/
67 /** @defgroup PWM_LL_ES_INIT PWM Exported init structures
68 * @{
69 */
70
71 /**
72 * @brief LL PWM Output Channel init Structure definition.
73 */
74 typedef struct _ll_pwm_channel_init_t {
75 uint8_t duty; /**< Specifies the duty in PWM output mode.
76 This parameter must be a number ranges between Min_Data=0 and Max_Data=100.
77 This feature can be modified afterwards using unitary function
78 ll_pwm_set_compare_xn()
79 where X can be (A, B, C) and n can be (0, 1). */
80
81 uint8_t drive_polarity; /**< Specifies the drive polarity in PWM output mode.
82 This parameter can be a value of @ref PWM_LL_EC_DRIVEPOLARITY.
83 This feature can be modified afterwards using unitary function
84 ll_pwm_enable_positive_drive_channel_x()
85 and ll_pwm_disable_positive_drive_channel_x() where X can be (A, B, C). */
86 } ll_pwm_channel_init_t;
87
88 /**
89 * @brief LL PWM init Structure definition.
90 */
91 typedef struct _ll_pwm_init_t {
92 uint32_t mode; /**< Specifies the PWM output mode.
93 This parameter can be a value of @ref PWM_LL_EC_MODE.
94 This feature can be modified afterwards using unitary function
95 @ref ll_pwm_set_mode(). */
96
97 uint32_t align; /**< Specifies the PWM alignment pulses.
98 This parameter can be a value of @ref PWM_LL_EC_ALIGN. */
99
100 uint32_t prescaler; /**< Specifies the prescaler value
101 which will be used configure PWM
102 output frequency.
103 This parameter must be a number ranges between Min_Data = 0 and
104 Max_Data = 0xFFFFFFFF.
105 This parameter should be larger than 128.
106 This feature can be modified afterwards using unitary function
107 @ref ll_pwm_set_prescaler(). */
108
109 uint32_t bprescaler; /**< Specifies the required prescaler that the duty changes from 0% to 100% in
110 breath mode. This parameter must
111 be a number ranges between
112 Min_Data=0 and
113 Max_Data=0xFFFFFFFF. This
114 parameter is recommended to be
115 larger than 128*prescaler
116 to guarantee an ideal breath effect.
117 This feature can be modified afterwards using unitary function
118 @ref ll_pwm_set_breath_prescaler(). */
119
120 uint32_t hprescaler; /**< Specifies the required prescaler in breath hold state.
121 This parameter must be a number
122 ranges between Min_Data=0 and
123 Max_Data=0xFFFFFF.
124 This feature can be modified afterwards using unitary function
125 @ref ll_pwm_set_hold_prescaler(). */
126
127 ll_pwm_channel_init_t channel_a; /**< Specifies the configuration of channelA.
128 This parameter can be a value of @ref ll_pwm_channel_init_t. */
129
130 ll_pwm_channel_init_t channel_b; /**< Specifies the configuration of channelB.
131 This parameter can be a value of @ref ll_pwm_channel_init_t. */
132
133 ll_pwm_channel_init_t channel_c; /**< Specifies the configuration of channelC.
134 This parameter can be a value of @ref ll_pwm_channel_init_t. */
135 } ll_pwm_init_t;
136
137 /** @} */
138
139 /** @} */
140
141 /**
142 * @defgroup PWM_LL_MACRO Defines
143 * @{
144 */
145
146 /* Exported constants --------------------------------------------------------*/
147 /** @defgroup PWM_LL_Exported_Constants PWM Exported Constants
148 * @{
149 */
150
151 /** @defgroup PWM_LL_EC_MODE PWM mode
152 * @{
153 */
154 #define LL_PWM_FLICKER_MODE (0x00000000U) /**< PWM flicker mode */
155 #define LL_PWM_BREATH_MODE PWM_MODE_BREATHEN /**< PWM breath mode */
156 /** @} */
157
158 /** @defgroup PWM_LL_EC_ALIGN PWM alignment pulses
159 * @{
160 */
161 #define LL_PWM_EDGE_ALIGNED (0x00000000U) /**< PWM edge-aligned */
162 #define LL_PWM_CENTER_ALIGNED (0x00000001U) /**< PWM center-aligned */
163 /** @} */
164
165 /** @defgroup PWM_LL_EC_DRIVEPOLARITY PWM drive polarity
166 * @{
167 */
168 #define LL_PWM_DRIVEPOLARITY_NEGATIVE (0x00000000U) /**< PWM led-negative-drive mode */
169 #define LL_PWM_DRIVEPOLARITY_POSITIVE (0x00000001U) /**< PWM led-positive-drive mode */
170 /** @} */
171
172 /** @defgroup PWM_LL_EC_ACTIONEVENT PWM action event
173 * @{
174 */
175 #define LL_PWM_ACTIONEVENT_NONE (0x00000000U) /**< No action event */
176 #define LL_PWM_ACTIONEVENT_CLEAR (0x00000001U) /**< Action event CLEAR */
177 #define LL_PWM_ACTIONEVENT_SET (0x00000002U) /**< Action event SET */
178 #define LL_PWM_ACTIONEVENT_TOGGLE (0x00000003U) /**< Action event TOGGLE */
179 /** @} */
180
181 /** @defgroup PWM_LL_EC_PERIOD_UNIT PWM period unit default configuretion
182 * @{
183 */
184 #define LL_PWM_PRESCALER_UNIT (128) /**< The unit of prescaler is 128 */
185 #define LL_PWM_BREATH_PRESCALER_UNIT (128) /**< The unit of breath prescaler is 128 */
186 #define LL_PWM_HOLD_PRESCALER_UNIT (10) /**< The unit of hold prescaler is 10 */
187 /** @} */
188
189 /** @defgroup PWM_LL_EC_DEFAULT_CONFIG InitStrcut default configuartion
190 * @{
191 */
192
193 /**
194 * @brief LL PWM Channel InitStrcut default configuartion
195 */
196 #define LL_PWM_CHANNEL_DEFAULT_CONFIG \
197 { \
198 .duty = 50, \
199 .drive_polarity = LL_PWM_DRIVEPOLARITY_POSITIVE, \
200 }
201
202 /**
203 * @brief LL PWM InitStrcut default configuartion
204 */
205 #define LL_PWM_DEFAULT_CONFIG \
206 { \
207 .mode = LL_PWM_FLICKER_MODE, \
208 .align = LL_PWM_EDGE_ALIGNED, \
209 .prescaler = 10 * LL_PWM_PRESCALER_UNIT, \
210 .bprescaler = 10 * LL_PWM_BREATH_PRESCALER_UNIT * 10 * LL_PWM_PRESCALER_UNIT, \
211 .hprescaler = 10 * LL_PWM_HOLD_PRESCALER_UNIT * 10 * LL_PWM_PRESCALER_UNIT, \
212 .channel_a = LL_PWM_CHANNEL_DEFAULT_CONFIG, \
213 .channel_b = LL_PWM_CHANNEL_DEFAULT_CONFIG, \
214 .channel_c = LL_PWM_CHANNEL_DEFAULT_CONFIG, \
215 }
216
217 /** @} */
218
219 /** @} */
220
221 /* Exported macro ------------------------------------------------------------*/
222 /** @defgroup PWM_LL_Exported_Macros PWM Exported Macros
223 * @{
224 */
225
226 /** @defgroup PWM_LL_EM_WRITE_READ Common Write and read registers Macros
227 * @{
228 */
229
230 /**
231 * @brief Write a value in PWM register
232 * @param __instance__ PWM instance
233 * @param __REG__ Register to be written
234 * @param __VALUE__ Value to be written in the register
235 * @retval None
236 */
237 #define LL_PWM_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
238
239 /**
240 * @brief Read a value in PWM register
241 * @param __instance__ PWM instance
242 * @param __REG__ Register to be read
243 * @retval Register value
244 */
245 #define LL_PWM_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
246
247 /** @} */
248
249 /** @} */
250
251 /** @} */
252
253 /* Exported functions --------------------------------------------------------*/
254 /** @defgroup PWM_LL_DRIVER_FUNCTIONS Functions
255 * @{
256 */
257
258 /** @defgroup PWM_LL_EF_Configuration Configuration functions
259 * @{
260 */
261
262 /**
263 * @brief Enable PWM.
264 *
265 * Register|BitsName
266 * --------|--------
267 * MODE | EN
268 *
269 * @param PWMx PWM instance
270 * @retval None
271 */
ll_pwm_enable(pwm_regs_t * PWMx)272 __STATIC_INLINE void ll_pwm_enable(pwm_regs_t *PWMx)
273 {
274 SET_BITS(PWMx->MODE, PWM_MODE_EN);
275 }
276
277 /**
278 * @brief Disable PWM.
279 *
280 * Register|BitsName
281 * --------|--------
282 * MODE | EN
283 *
284 * @param PWMx PWM instance
285 * @retval None
286 */
ll_pwm_disable(pwm_regs_t * PWMx)287 __STATIC_INLINE void ll_pwm_disable(pwm_regs_t *PWMx)
288 {
289 CLEAR_BITS(PWMx->MODE, PWM_MODE_EN);
290 }
291
292 /**
293 * @brief Indicate whether the PWM is enabled.
294 *
295 * Register|BitsName
296 * --------|--------
297 * MODE | EN
298 *
299 * @param PWMx PWM instance
300 * @retval State of bit (1 or 0).
301 */
ll_pwm_is_enabled(pwm_regs_t * PWMx)302 __STATIC_INLINE uint32_t ll_pwm_is_enabled(pwm_regs_t *PWMx)
303 {
304 return (READ_BITS(PWMx->MODE, PWM_MODE_EN) == (PWM_MODE_EN));
305 }
306
307 /**
308 * @brief Enable PWM pause.
309 *
310 * Register|BitsName
311 * --------|--------
312 * MODE | PAUSE
313 *
314 * @param PWMx PWM instance
315 * @retval None
316 */
ll_pwm_enable_pause(pwm_regs_t * PWMx)317 __STATIC_INLINE void ll_pwm_enable_pause(pwm_regs_t *PWMx)
318 {
319 SET_BITS(PWMx->MODE, PWM_MODE_PAUSE);
320 }
321
322 /**
323 * @brief Disable PWM pause.
324 *
325 * Register|BitsName
326 * --------|--------
327 * MODE | PAUSE
328 *
329 * @param PWMx PWM instance
330 * @retval None
331 */
ll_pwm_disable_pause(pwm_regs_t * PWMx)332 __STATIC_INLINE void ll_pwm_disable_pause(pwm_regs_t *PWMx)
333 {
334 CLEAR_BITS(PWMx->MODE, PWM_MODE_PAUSE);
335 }
336
337 /**
338 * @brief Indicate whether the PWM pause is enabled.
339 *
340 * Register|BitsName
341 * --------|--------
342 * MODE | PAUSE
343 *
344 * @param PWMx PWM instance
345 * @retval State of bit (1 or 0).
346 */
ll_pwm_is_enabled_pause(pwm_regs_t * PWMx)347 __STATIC_INLINE uint32_t ll_pwm_is_enabled_pause(pwm_regs_t *PWMx)
348 {
349 return (READ_BITS(PWMx->MODE, PWM_MODE_PAUSE) == (PWM_MODE_PAUSE));
350 }
351
352 /**
353 * @brief Set PWM mode.
354 *
355 * Register|BitsName
356 * --------|--------
357 * MODE | BREATHEN
358 *
359 * @param PWMx PWM instance
360 * @param mode This parameter can be one of the following values:
361 * @arg @ref LL_PWM_FLICKER_MODE
362 * @arg @ref LL_PWM_BREATH_MODE
363 * @retval None
364 */
ll_pwm_set_mode(pwm_regs_t * PWMx,uint32_t mode)365 __STATIC_INLINE void ll_pwm_set_mode(pwm_regs_t *PWMx, uint32_t mode)
366 {
367 MODIFY_REG(PWMx->MODE, PWM_MODE_BREATHEN, mode);
368 }
369
370 /**
371 * @brief Get PWM mode.
372 *
373 * Register|BitsName
374 * --------|--------
375 * MODE | BREATHEN
376 *
377 * @param PWMx PWM instance
378 * @retval Return value can be one of the following values:
379 * @arg @ref LL_PWM_FLICKER_MODE
380 * @arg @ref LL_PWM_BREATH_MODE
381 */
ll_pwm_get_mode(pwm_regs_t * PWMx)382 __STATIC_INLINE uint32_t ll_pwm_get_mode(pwm_regs_t *PWMx)
383 {
384 return (READ_BITS(PWMx->MODE, PWM_MODE_BREATHEN));
385 }
386
387 /**
388 * @brief Enable positive drive mode in channelA.
389 *
390 * Register|BitsName
391 * --------|--------
392 * MODE | DPENA
393 *
394 * @param PWMx PWM instance
395 * @retval None
396 */
ll_pwm_enable_positive_drive_channel_a(pwm_regs_t * PWMx)397 __STATIC_INLINE void ll_pwm_enable_positive_drive_channel_a(pwm_regs_t *PWMx)
398 {
399 SET_BITS(PWMx->MODE, PWM_MODE_DPENA);
400 }
401
402 /**
403 * @brief Disable positive drive mode in channelA.
404 *
405 * Register|BitsName
406 * --------|--------
407 * MODE | DPENA
408 *
409 * @param PWMx PWM instance
410 * @retval None
411 */
ll_pwm_disable_positive_drive_channel_a(pwm_regs_t * PWMx)412 __STATIC_INLINE void ll_pwm_disable_positive_drive_channel_a(pwm_regs_t *PWMx)
413 {
414 CLEAR_BITS(PWMx->MODE, PWM_MODE_DPENA);
415 }
416
417 /**
418 * @brief Indicate whether the positive drive mode in channelA is enabled.
419 *
420 * Register|BitsName
421 * --------|--------
422 * MODE | DPENA
423 *
424 * @param PWMx PWM instance
425 * @retval State of bit (1 or 0).
426 */
ll_pwm_is_enabled_positive_drive_channel_a(pwm_regs_t * PWMx)427 __STATIC_INLINE uint32_t ll_pwm_is_enabled_positive_drive_channel_a(pwm_regs_t *PWMx)
428 {
429 return (READ_BITS(PWMx->MODE, PWM_MODE_DPENA) == (PWM_MODE_DPENA));
430 }
431
432 /**
433 * @brief Enable positive drive mode in channelB.
434 *
435 * Register|BitsName
436 * --------|--------
437 * MODE | DPENB
438 *
439 * @param PWMx PWM instance
440 * @retval None
441 */
ll_pwm_enable_positive_drive_channel_b(pwm_regs_t * PWMx)442 __STATIC_INLINE void ll_pwm_enable_positive_drive_channel_b(pwm_regs_t *PWMx)
443 {
444 SET_BITS(PWMx->MODE, PWM_MODE_DPENB);
445 }
446
447 /**
448 * @brief Disable positive drive mode in channelB.
449 *
450 * Register|BitsName
451 * --------|--------
452 * MODE | DPENB
453 *
454 * @param PWMx PWM instance
455 * @retval None
456 */
ll_pwm_disable_positive_drive_channel_b(pwm_regs_t * PWMx)457 __STATIC_INLINE void ll_pwm_disable_positive_drive_channel_b(pwm_regs_t *PWMx)
458 {
459 CLEAR_BITS(PWMx->MODE, PWM_MODE_DPENB);
460 }
461
462 /**
463 * @brief Indicate whether the positive drive mode in channelB is enabled.
464 *
465 * Register|BitsName
466 * --------|--------
467 * MODE | DPENB
468 *
469 * @param PWMx PWM instance
470 * @retval State of bit (1 or 0).
471 */
ll_pwm_is_enabled_positive_drive_channel_b(pwm_regs_t * PWMx)472 __STATIC_INLINE uint32_t ll_pwm_is_enabled_positive_drive_channel_b(pwm_regs_t *PWMx)
473 {
474 return (READ_BITS(PWMx->MODE, PWM_MODE_DPENB) == (PWM_MODE_DPENB));
475 }
476
477 /**
478 * @brief Enable positive drive mode in channelC.
479 *
480 * Register|BitsName
481 * --------|--------
482 * MODE | DPENC
483 *
484 * @param PWMx PWM instance
485 * @retval None
486 */
ll_pwm_enable_positive_drive_channel_c(pwm_regs_t * PWMx)487 __STATIC_INLINE void ll_pwm_enable_positive_drive_channel_c(pwm_regs_t *PWMx)
488 {
489 SET_BITS(PWMx->MODE, PWM_MODE_DPENC);
490 }
491
492 /**
493 * @brief Disable positive drive mode in channelC.
494 *
495 * Register|BitsName
496 * --------|--------
497 * MODE | DPENC
498 *
499 * @param PWMx PWM instance
500 * @retval None
501 */
ll_pwm_disable_positive_drive_channel_c(pwm_regs_t * PWMx)502 __STATIC_INLINE void ll_pwm_disable_positive_drive_channel_c(pwm_regs_t *PWMx)
503 {
504 CLEAR_BITS(PWMx->MODE, PWM_MODE_DPENC);
505 }
506
507 /**
508 * @brief Indicate whether the positive drive mode in channelC is enabled.
509 *
510 * Register|BitsName
511 * --------|--------
512 * MODE | DPENC
513 *
514 * @param PWMx PWM instance
515 * @retval State of bit (1 or 0).
516 */
ll_pwm_is_enabled_positive_drive_channel_c(pwm_regs_t * PWMx)517 __STATIC_INLINE uint32_t ll_pwm_is_enabled_positive_drive_channel_c(pwm_regs_t *PWMx)
518 {
519 return (READ_BITS(PWMx->MODE, PWM_MODE_DPENC) == (PWM_MODE_DPENC));
520 }
521
522 /**
523 * @brief Check update active flag
524 *
525 * Register|BitsName
526 * --------|--------
527 * UPDATE | SAG
528 *
529 * @param PWMx PWM instance
530 * @retval State of bit (1 or 0).
531 */
ll_pwm_is_active_flag_update_all(pwm_regs_t * PWMx)532 __STATIC_INLINE uint32_t ll_pwm_is_active_flag_update_all(pwm_regs_t *PWMx)
533 {
534 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SAG) == (PWM_UPDATE_SAG));
535 }
536
537 /**
538 * @brief Enable update all parameters.
539 *
540 * Register|BitsName
541 * --------|--------
542 * UPDATE | SA
543 *
544 * @param PWMx PWM instance
545 * @retval None
546 */
ll_pwm_enable_update_all(pwm_regs_t * PWMx)547 __STATIC_INLINE void ll_pwm_enable_update_all(pwm_regs_t *PWMx)
548 {
549 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SA);
550 }
551
552 /**
553 * @brief Disable update all parameters.
554 *
555 * Register|BitsName
556 * --------|--------
557 * UPDATE | SA
558 *
559 * @param PWMx PWM instance
560 * @retval None
561 */
ll_pwm_disable_update_all(pwm_regs_t * PWMx)562 __STATIC_INLINE void ll_pwm_disable_update_all(pwm_regs_t *PWMx)
563 {
564 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SA);
565 }
566
567 /**
568 * @brief Indicate whether the update all parameters is enabled.
569 *
570 * Register|BitsName
571 * --------|--------
572 * UPDATE | SA
573 *
574 * @param PWMx PWM instance
575 * @retval State of bit (1 or 0).
576 */
ll_pwm_is_enabled_update_all(pwm_regs_t * PWMx)577 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_all(pwm_regs_t *PWMx)
578 {
579 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SA) == (PWM_UPDATE_SA));
580 }
581
582 /**
583 * @brief Enable update period.
584 *
585 * Register|BitsName
586 * --------|--------
587 * UPDATE | SSPRD
588 *
589 * @param PWMx PWM instance
590 * @retval None
591 */
ll_pwm_enable_update_period(pwm_regs_t * PWMx)592 __STATIC_INLINE void ll_pwm_enable_update_period(pwm_regs_t *PWMx)
593 {
594 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSPRD);
595 }
596
597 /**
598 * @brief Disable update period.
599 *
600 * Register|BitsName
601 * --------|--------
602 * UPDATE | SSPRD
603 *
604 * @param PWMx PWM instance
605 * @retval None
606 */
ll_pwm_disable_update_period(pwm_regs_t * PWMx)607 __STATIC_INLINE void ll_pwm_disable_update_period(pwm_regs_t *PWMx)
608 {
609 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSPRD);
610 }
611
612 /**
613 * @brief Indicate whether the update period is enabled.
614 *
615 * Register|BitsName
616 * --------|--------
617 * UPDATE | SSPRD
618 *
619 * @param PWMx PWM instance
620 * @retval State of bit (1 or 0).
621 */
ll_pwm_is_enabled_update_period(pwm_regs_t * PWMx)622 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_period(pwm_regs_t *PWMx)
623 {
624 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSPRD) == (PWM_UPDATE_SSPRD));
625 }
626
627 /**
628 * @brief Enable update compareA0.
629 *
630 * Register|BitsName
631 * --------|--------
632 * UPDATE | SSCMPA0
633 *
634 * @param PWMx PWM instance
635 * @retval None
636 */
ll_pwm_enable_update_compare_a0(pwm_regs_t * PWMx)637 __STATIC_INLINE void ll_pwm_enable_update_compare_a0(pwm_regs_t *PWMx)
638 {
639 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPA0);
640 }
641
642 /**
643 * @brief Disable update compareA0.
644 *
645 * Register|BitsName
646 * --------|--------
647 * UPDATE | SSCMPA0
648 *
649 * @param PWMx PWM instance
650 * @retval None
651 */
ll_pwm_disable_update_compare_a0(pwm_regs_t * PWMx)652 __STATIC_INLINE void ll_pwm_disable_update_compare_a0(pwm_regs_t *PWMx)
653 {
654 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPA0);
655 }
656
657 /**
658 * @brief Indicate whether the update compareA0 is enabled.
659 *
660 * Register|BitsName
661 * --------|--------
662 * UPDATE | SSCMPA0
663 *
664 * @param PWMx PWM instance
665 * @retval State of bit (1 or 0).
666 */
ll_pwm_is_enabled_update_compare_a0(pwm_regs_t * PWMx)667 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_a0(pwm_regs_t *PWMx)
668 {
669 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPA0) == (PWM_UPDATE_SSCMPA0));
670 }
671
672 /**
673 * @brief Enable update compareA1.
674 *
675 * Register|BitsName
676 * --------|--------
677 * UPDATE | SSCMPA1
678 *
679 * @param PWMx PWM instance
680 * @retval None
681 */
ll_pwm_enable_update_compare_a1(pwm_regs_t * PWMx)682 __STATIC_INLINE void ll_pwm_enable_update_compare_a1(pwm_regs_t *PWMx)
683 {
684 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPA1);
685 }
686
687 /**
688 * @brief Disable update compareA1.
689 *
690 * Register|BitsName
691 * --------|--------
692 * UPDATE | SSCMPA1
693 *
694 * @param PWMx PWM instance
695 * @retval None
696 */
ll_pwm_disable_update_compare_a1(pwm_regs_t * PWMx)697 __STATIC_INLINE void ll_pwm_disable_update_compare_a1(pwm_regs_t *PWMx)
698 {
699 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPA1);
700 }
701
702 /**
703 * @brief Indicate whether the update compareA1 is enabled.
704 *
705 * Register|BitsName
706 * --------|--------
707 * UPDATE | SSCMPA1
708 *
709 * @param PWMx PWM instance
710 * @retval State of bit (1 or 0).
711 */
ll_pwm_is_enabled_update_compare_a1(pwm_regs_t * PWMx)712 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_a1(pwm_regs_t *PWMx)
713 {
714 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPA1) == (PWM_UPDATE_SSCMPA1));
715 }
716
717 /**
718 * @brief Enable update compareB0.
719 *
720 * Register|BitsName
721 * --------|--------
722 * UPDATE | SSCMPB0
723 *
724 * @param PWMx PWM instance
725 * @retval None
726 */
ll_pwm_enable_update_compare_b0(pwm_regs_t * PWMx)727 __STATIC_INLINE void ll_pwm_enable_update_compare_b0(pwm_regs_t *PWMx)
728 {
729 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPB0);
730 }
731
732 /**
733 * @brief Disable update compareB0.
734 *
735 * Register|BitsName
736 * --------|--------
737 * UPDATE | SSCMPB0
738 *
739 * @param PWMx PWM instance
740 * @retval None
741 */
ll_pwm_disable_update_compare_b0(pwm_regs_t * PWMx)742 __STATIC_INLINE void ll_pwm_disable_update_compare_b0(pwm_regs_t *PWMx)
743 {
744 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPB0);
745 }
746
747 /**
748 * @brief Indicate whether the update compareB0 is enabled.
749 *
750 * Register|BitsName
751 * --------|--------
752 * UPDATE | SSCMPB0
753 *
754 * @param PWMx PWM instance
755 * @retval State of bit (1 or 0).
756 */
ll_pwm_is_enabled_update_compare_b0(pwm_regs_t * PWMx)757 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_b0(pwm_regs_t *PWMx)
758 {
759 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPB0) == (PWM_UPDATE_SSCMPB0));
760 }
761
762 /**
763 * @brief Enable update compareB1.
764 *
765 * Register|BitsName
766 * --------|--------
767 * UPDATE | SSCMPB1
768 *
769 * @param PWMx PWM instance
770 * @retval None
771 */
ll_pwm_enable_update_compare_b1(pwm_regs_t * PWMx)772 __STATIC_INLINE void ll_pwm_enable_update_compare_b1(pwm_regs_t *PWMx)
773 {
774 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPB1);
775 }
776
777 /**
778 * @brief Disable update compareB1.
779 *
780 * Register|BitsName
781 * --------|--------
782 * UPDATE | SSCMPB1
783 *
784 * @param PWMx PWM instance
785 * @retval None
786 */
ll_pwm_disable_update_compare_b1(pwm_regs_t * PWMx)787 __STATIC_INLINE void ll_pwm_disable_update_compare_b1(pwm_regs_t *PWMx)
788 {
789 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPB1);
790 }
791
792 /**
793 * @brief Indicate whether the update compareB1 is enabled.
794 *
795 * Register|BitsName
796 * --------|--------
797 * UPDATE | SSCMPB1
798 *
799 * @param PWMx PWM instance
800 * @retval State of bit (1 or 0).
801 */
ll_pwm_is_enabled_update_compare_b1(pwm_regs_t * PWMx)802 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_b1(pwm_regs_t *PWMx)
803 {
804 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPB1) == (PWM_UPDATE_SSCMPB1));
805 }
806
807 /**
808 * @brief Enable update compareC0.
809 *
810 * Register|BitsName
811 * --------|--------
812 * UPDATE | SSCMPC0
813 *
814 * @param PWMx PWM instance
815 * @retval None
816 */
ll_pwm_enable_update_compare_c0(pwm_regs_t * PWMx)817 __STATIC_INLINE void ll_pwm_enable_update_compare_c0(pwm_regs_t *PWMx)
818 {
819 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPC0);
820 }
821
822 /**
823 * @brief Disable update compareC0.
824 *
825 * Register|BitsName
826 * --------|--------
827 * UPDATE | SSCMPC0
828 *
829 * @param PWMx PWM instance
830 * @retval None
831 */
ll_pwm_disable_update_compare_c0(pwm_regs_t * PWMx)832 __STATIC_INLINE void ll_pwm_disable_update_compare_c0(pwm_regs_t *PWMx)
833 {
834 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPC0);
835 }
836
837 /**
838 * @brief Indicate whether the update compareC0 is enabled.
839 *
840 * Register|BitsName
841 * --------|--------
842 * UPDATE | SSCMPC0
843 *
844 * @param PWMx PWM instance
845 * @retval State of bit (1 or 0).
846 */
ll_pwm_is_enabled_update_compare_c0(pwm_regs_t * PWMx)847 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_c0(pwm_regs_t *PWMx)
848 {
849 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPC0) == (PWM_UPDATE_SSCMPC0));
850 }
851
852 /**
853 * @brief Enable update compareC1.
854 *
855 * Register|BitsName
856 * --------|--------
857 * UPDATE | SSCMPC1
858 *
859 * @param PWMx PWM instance
860 * @retval None
861 */
ll_pwm_enable_update_compare_c1(pwm_regs_t * PWMx)862 __STATIC_INLINE void ll_pwm_enable_update_compare_c1(pwm_regs_t *PWMx)
863 {
864 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPC1);
865 }
866
867 /**
868 * @brief Disable update compareC1.
869 *
870 * Register|BitsName
871 * --------|--------
872 * UPDATE | SSCMPC1
873 *
874 * @param PWMx PWM instance
875 * @retval None
876 */
ll_pwm_disable_update_compare_c1(pwm_regs_t * PWMx)877 __STATIC_INLINE void ll_pwm_disable_update_compare_c1(pwm_regs_t *PWMx)
878 {
879 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPC1);
880 }
881
882 /**
883 * @brief Indicate whether the update compareC1 is enabled.
884 *
885 * Register|BitsName
886 * --------|--------
887 * UPDATE | SSCMPC1
888 *
889 * @param PWMx PWM instance
890 * @retval State of bit (1 or 0).
891 */
ll_pwm_is_enabled_update_compare_c1(pwm_regs_t * PWMx)892 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_compare_c1(pwm_regs_t *PWMx)
893 {
894 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSCMPC1) == (PWM_UPDATE_SSCMPC1));
895 }
896
897 /**
898 * @brief Enable update pause.
899 *
900 * Register|BitsName
901 * --------|--------
902 * UPDATE | SSPAUSE
903 *
904 * @param PWMx PWM instance
905 * @retval None
906 */
ll_pwm_enable_update_pause(pwm_regs_t * PWMx)907 __STATIC_INLINE void ll_pwm_enable_update_pause(pwm_regs_t *PWMx)
908 {
909 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSPAUSE);
910 }
911
912 /**
913 * @brief Disable update pause.
914 *
915 * Register|BitsName
916 * --------|--------
917 * UPDATE | SSPAUSE
918 *
919 * @param PWMx PWM instance
920 * @retval None
921 */
ll_pwm_disable_update_pause(pwm_regs_t * PWMx)922 __STATIC_INLINE void ll_pwm_disable_update_pause(pwm_regs_t *PWMx)
923 {
924 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSPAUSE);
925 }
926
927 /**
928 * @brief Indicate whether the update pause is enabled.
929 *
930 * Register|BitsName
931 * --------|--------
932 * UPDATE | SSPAUSE
933 *
934 * @param PWMx PWM instance
935 * @retval State of bit (1 or 0).
936 */
ll_pwm_is_enabled_update_pause(pwm_regs_t * PWMx)937 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_pause(pwm_regs_t *PWMx)
938 {
939 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSPAUSE) == (PWM_UPDATE_SSPAUSE));
940 }
941
942 /**
943 * @brief Enable update breath period.
944 *
945 * Register|BitsName
946 * --------|--------
947 * UPDATE | SSBRPRD
948 *
949 * @param PWMx PWM instance
950 * @retval None
951 */
ll_pwm_enable_update_breath_period(pwm_regs_t * PWMx)952 __STATIC_INLINE void ll_pwm_enable_update_breath_period(pwm_regs_t *PWMx)
953 {
954 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSBRPRD);
955 }
956
957 /**
958 * @brief Disable update breath period.
959 *
960 * Register|BitsName
961 * --------|--------
962 * UPDATE | SSBRPRD
963 *
964 * @param PWMx PWM instance
965 * @retval None
966 */
ll_pwm_disable_update_breath_period(pwm_regs_t * PWMx)967 __STATIC_INLINE void ll_pwm_disable_update_breath_period(pwm_regs_t *PWMx)
968 {
969 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSBRPRD);
970 }
971
972 /**
973 * @brief Indicate whether the update breath period is enabled.
974 *
975 * Register|BitsName
976 * --------|--------
977 * UPDATE | SSBRPRD
978 *
979 * @param PWMx PWM instance
980 * @retval State of bit (1 or 0).
981 */
ll_pwm_is_enabled_update_breath_period(pwm_regs_t * PWMx)982 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_breath_period(pwm_regs_t *PWMx)
983 {
984 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSBRPRD) == (PWM_UPDATE_SSBRPRD));
985 }
986
987 /**
988 * @brief Enable update hold period.
989 *
990 * Register|BitsName
991 * --------|--------
992 * UPDATE | SSHOLD
993 *
994 * @param PWMx PWM instance
995 * @retval None
996 */
ll_pwm_enable_update_hold_period(pwm_regs_t * PWMx)997 __STATIC_INLINE void ll_pwm_enable_update_hold_period(pwm_regs_t *PWMx)
998 {
999 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSHOLD);
1000 }
1001
1002 /**
1003 * @brief Disable update hold period.
1004 *
1005 * Register|BitsName
1006 * --------|--------
1007 * UPDATE | SSHOLD
1008 *
1009 * @param PWMx PWM instance
1010 * @retval None
1011 */
ll_pwm_disable_update_hold_period(pwm_regs_t * PWMx)1012 __STATIC_INLINE void ll_pwm_disable_update_hold_period(pwm_regs_t *PWMx)
1013 {
1014 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSHOLD);
1015 }
1016
1017 /**
1018 * @brief Indicate whether the update hold period is enabled.
1019 *
1020 * Register|BitsName
1021 * --------|--------
1022 * UPDATE | SSHOLD
1023 *
1024 * @param PWMx PWM instance
1025 * @retval State of bit (1 or 0).
1026 */
ll_pwm_is_enabled_update_hold_period(pwm_regs_t * PWMx)1027 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_hold_period(pwm_regs_t *PWMx)
1028 {
1029 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSHOLD) == (PWM_UPDATE_SSHOLD));
1030 }
1031
1032 /**
1033 * @brief Enable update active event.
1034 *
1035 * Register|BitsName
1036 * --------|--------
1037 * UPDATE | SSAQCTRL
1038 *
1039 * @param PWMx PWM instance
1040 * @retval None
1041 */
ll_pwm_enable_update_active_event(pwm_regs_t * PWMx)1042 __STATIC_INLINE void ll_pwm_enable_update_active_event(pwm_regs_t *PWMx)
1043 {
1044 SET_BITS(PWMx->UPDATE, PWM_UPDATE_SSAQCTRL);
1045 }
1046
1047 /**
1048 * @brief Disable update active event.
1049 *
1050 * Register|BitsName
1051 * --------|--------
1052 * UPDATE | SSAQCTRL
1053 *
1054 * @param PWMx PWM instance
1055 * @retval None
1056 */
ll_pwm_disable_update_active_event(pwm_regs_t * PWMx)1057 __STATIC_INLINE void ll_pwm_disable_update_active_event(pwm_regs_t *PWMx)
1058 {
1059 CLEAR_BITS(PWMx->UPDATE, PWM_UPDATE_SSAQCTRL);
1060 }
1061
1062 /**
1063 * @brief Indicate whether the update active event is enabled.
1064 *
1065 * Register|BitsName
1066 * --------|--------
1067 * UPDATE | SSAQCTRL
1068 *
1069 * @param PWMx PWM instance
1070 * @retval State of bit (1 or 0).
1071 */
ll_pwm_is_enabled_update_active_event(pwm_regs_t * PWMx)1072 __STATIC_INLINE uint32_t ll_pwm_is_enabled_update_active_event(pwm_regs_t *PWMx)
1073 {
1074 return (READ_BITS(PWMx->UPDATE, PWM_UPDATE_SSAQCTRL) == (PWM_UPDATE_SSAQCTRL));
1075 }
1076
1077 /**
1078 * @brief Set the PWM prescaler.
1079 *
1080 * Register|BitsName
1081 * --------|--------
1082 * PRD | PRD
1083 *
1084 * @param PWMx PWM instance
1085 * @param prescaler This parameter ranges between Min_Data=1 and Max_Data=0xFFFFFFFF
1086 * @retval None
1087 */
ll_pwm_set_prescaler(pwm_regs_t * PWMx,uint32_t prescaler)1088 __STATIC_INLINE void ll_pwm_set_prescaler(pwm_regs_t *PWMx, uint32_t prescaler)
1089 {
1090 WRITE_REG(PWMx->PRD, prescaler);
1091 }
1092
1093 /**
1094 * @brief Get the PWM prescaler.
1095 *
1096 * Register|BitsName
1097 * --------|--------
1098 * PRD | PRD
1099 *
1100 * @param PWMx PWM instance
1101 * @retval Return value ranges between Min_Data=1 and Max_Data=0xFFFFFFFF
1102 */
ll_pwm_get_prescaler(pwm_regs_t * PWMx)1103 __STATIC_INLINE uint32_t ll_pwm_get_prescaler(pwm_regs_t *PWMx)
1104 {
1105 return (READ_REG(PWMx->PRD));
1106 }
1107
1108 /**
1109 * @brief Set the PWM compare counter A0.
1110 *
1111 * Register|BitsName
1112 * --------|--------
1113 * CMPA0 | CMPA0
1114 *
1115 * @param PWMx PWM instance
1116 * @param compare This parameter ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1117 * @retval None
1118 */
ll_pwm_set_compare_a0(pwm_regs_t * PWMx,uint32_t compare)1119 __STATIC_INLINE void ll_pwm_set_compare_a0(pwm_regs_t *PWMx, uint32_t compare)
1120 {
1121 WRITE_REG(PWMx->CMPA0, compare);
1122 }
1123
1124 /**
1125 * @brief Get the PWM compare counter A0.
1126 *
1127 * Register|BitsName
1128 * --------|--------
1129 * CMPA0 | CMPA0
1130 *
1131 * @param PWMx PWM instance
1132 * @retval Return value ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1133 */
ll_pwm_get_compare_a0(pwm_regs_t * PWMx)1134 __STATIC_INLINE uint32_t ll_pwm_get_compare_a0(pwm_regs_t *PWMx)
1135 {
1136 return (READ_REG(PWMx->CMPA0));
1137 }
1138
1139 /**
1140 * @brief Set the PWM compare counter A1.
1141 *
1142 * Register|BitsName
1143 * --------|--------
1144 * CMPA1 | CMPA1
1145 *
1146 * @param PWMx PWM instance
1147 * @param compare This parameter ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1148 * @retval None
1149 */
ll_pwm_set_compare_a1(pwm_regs_t * PWMx,uint32_t compare)1150 __STATIC_INLINE void ll_pwm_set_compare_a1(pwm_regs_t *PWMx, uint32_t compare)
1151 {
1152 WRITE_REG(PWMx->CMPA1, compare);
1153 }
1154
1155 /**
1156 * @brief Get the PWM compare counter A1.
1157 *
1158 * Register|BitsName
1159 * --------|--------
1160 * CMPA1 | CMPA1
1161 *
1162 * @param PWMx PWM instance
1163 * @retval Return value ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1164 */
ll_pwm_get_compare_a1(pwm_regs_t * PWMx)1165 __STATIC_INLINE uint32_t ll_pwm_get_compare_a1(pwm_regs_t *PWMx)
1166 {
1167 return (READ_REG(PWMx->CMPA1));
1168 }
1169
1170 /**
1171 * @brief Set the PWM compare counter B0.
1172 *
1173 * Register|BitsName
1174 * --------|--------
1175 * CMPB0 | CMPB0
1176 *
1177 * @param PWMx PWM instance
1178 * @param compare This parameter ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1179 * @retval None
1180 */
ll_pwm_set_compare_b0(pwm_regs_t * PWMx,uint32_t compare)1181 __STATIC_INLINE void ll_pwm_set_compare_b0(pwm_regs_t *PWMx, uint32_t compare)
1182 {
1183 WRITE_REG(PWMx->CMPB0, compare);
1184 }
1185
1186 /**
1187 * @brief Get the PWM compare counter B0.
1188 *
1189 * Register|BitsName
1190 * --------|--------
1191 * CMPB0 | CMPB0
1192 *
1193 * @param PWMx PWM instance
1194 * @retval Return value ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1195 */
ll_pwm_get_compare_b0(pwm_regs_t * PWMx)1196 __STATIC_INLINE uint32_t ll_pwm_get_compare_b0(pwm_regs_t *PWMx)
1197 {
1198 return (READ_REG(PWMx->CMPB0));
1199 }
1200
1201 /**
1202 * @brief Set the PWM compare counter B1.
1203 *
1204 * Register|BitsName
1205 * --------|--------
1206 * CMPB1 | CMPB1
1207 *
1208 * @param PWMx PWM instance
1209 * @param compare This parameter ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1210 * @retval None
1211 */
ll_pwm_set_compare_b1(pwm_regs_t * PWMx,uint32_t compare)1212 __STATIC_INLINE void ll_pwm_set_compare_b1(pwm_regs_t *PWMx, uint32_t compare)
1213 {
1214 WRITE_REG(PWMx->CMPB1, compare);
1215 }
1216
1217 /**
1218 * @brief Get the PWM compare counter B1.
1219 *
1220 * Register|BitsName
1221 * --------|--------
1222 * CMPB1 | CMPB1
1223 *
1224 * @param PWMx PWM instance
1225 * @retval Return value ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1226 */
ll_pwm_get_compare_b1(pwm_regs_t * PWMx)1227 __STATIC_INLINE uint32_t ll_pwm_get_compare_b1(pwm_regs_t *PWMx)
1228 {
1229 return (READ_REG(PWMx->CMPB1));
1230 }
1231
1232 /**
1233 * @brief Set the PWM compare counter C0.
1234 *
1235 * Register|BitsName
1236 * --------|--------
1237 * CMPC0 | CMPC0
1238 *
1239 * @param PWMx PWM instance
1240 * @param compare This parameter ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1241 * @retval None
1242 */
ll_pwm_set_compare_c0(pwm_regs_t * PWMx,uint32_t compare)1243 __STATIC_INLINE void ll_pwm_set_compare_c0(pwm_regs_t *PWMx, uint32_t compare)
1244 {
1245 WRITE_REG(PWMx->CMPC0, compare);
1246 }
1247
1248 /**
1249 * @brief Get the PWM compare counter C0.
1250 *
1251 * Register|BitsName
1252 * --------|--------
1253 * CMPC0 | CMPC0
1254 *
1255 * @param PWMx PWM instance
1256 * @retval Return value ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1257 */
ll_pwm_get_compare_c0(pwm_regs_t * PWMx)1258 __STATIC_INLINE uint32_t ll_pwm_get_compare_c0(pwm_regs_t *PWMx)
1259 {
1260 return (READ_REG(PWMx->CMPC0));
1261 }
1262
1263 /**
1264 * @brief Set the PWM compare counter C1.
1265 *
1266 * Register|BitsName
1267 * --------|--------
1268 * CMPC1 | CMPC1
1269 *
1270 * @param PWMx PWM instance
1271 * @param compare This parameter ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1272 * @retval None
1273 */
ll_pwm_set_compare_c1(pwm_regs_t * PWMx,uint32_t compare)1274 __STATIC_INLINE void ll_pwm_set_compare_c1(pwm_regs_t *PWMx, uint32_t compare)
1275 {
1276 WRITE_REG(PWMx->CMPC1, compare);
1277 }
1278
1279 /**
1280 * @brief Get the PWM compare counter C1.
1281 *
1282 * Register|BitsName
1283 * --------|--------
1284 * CMPC1 | CMPC1
1285 *
1286 * @param PWMx PWM instance
1287 * @retval Return value ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1288 */
ll_pwm_get_compare_c1(pwm_regs_t * PWMx)1289 __STATIC_INLINE uint32_t ll_pwm_get_compare_c1(pwm_regs_t *PWMx)
1290 {
1291 return (READ_REG(PWMx->CMPC1));
1292 }
1293
1294 /**
1295 * @brief Set the channel A0 action event when PWM counter value reaches compare counter A0.
1296 *
1297 * Register|BitsName
1298 * --------|--------
1299 * AQCTRL | A0
1300 *
1301 * @param PWMx PWM instance
1302 * @param action_event This parameter can be one of the following values:
1303 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1304 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1305 * @arg @ref LL_PWM_ACTIONEVENT_SET
1306 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1307 * @retval None
1308 */
ll_pwm_set_action_event_cmp_a0(pwm_regs_t * PWMx,uint32_t action_event)1309 __STATIC_INLINE void ll_pwm_set_action_event_cmp_a0(pwm_regs_t *PWMx, uint32_t action_event)
1310 {
1311 MODIFY_REG(PWMx->AQCTRL, PWM_AQCTRL_A0, action_event << PWM_AQCTRL_A0_Pos);
1312 }
1313
1314 /**
1315 * @brief Get the channel A0 action event when PWM counter value reaches compare counter A0.
1316 *
1317 * Register|BitsName
1318 * --------|--------
1319 * AQCTRL | A0
1320 *
1321 * @param PWMx PWM instance
1322 * @retval Return value can be one of the following values:
1323 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1324 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1325 * @arg @ref LL_PWM_ACTIONEVENT_SET
1326 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1327 */
ll_pwm_get_action_event_cmp_a0(pwm_regs_t * PWMx)1328 __STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_a0(pwm_regs_t *PWMx)
1329 {
1330 return (READ_BITS(PWMx->AQCTRL, PWM_AQCTRL_A0) >> PWM_AQCTRL_A0_Pos);
1331 }
1332
1333 /**
1334 * @brief Set the channel A1 action event when PWM counter value reaches compare counter A1.
1335 *
1336 * Register|BitsName
1337 * --------|--------
1338 * AQCTRL | A1
1339 *
1340 * @param PWMx PWM instance
1341 * @param action_event This parameter can be one of the following values:
1342 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1343 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1344 * @arg @ref LL_PWM_ACTIONEVENT_SET
1345 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1346 * @retval None
1347 */
ll_pwm_set_action_event_cmp_a1(pwm_regs_t * PWMx,uint32_t action_event)1348 __STATIC_INLINE void ll_pwm_set_action_event_cmp_a1(pwm_regs_t *PWMx, uint32_t action_event)
1349 {
1350 MODIFY_REG(PWMx->AQCTRL, PWM_AQCTRL_A1, action_event << PWM_AQCTRL_A1_Pos);
1351 }
1352
1353 /**
1354 * @brief Get the channel A1 action event when PWM counter value reaches compare counter A1.
1355 *
1356 * Register|BitsName
1357 * --------|--------
1358 * AQCTRL | A1
1359 *
1360 * @param PWMx PWM instance
1361 * @retval Return value can be one of the following values:
1362 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1363 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1364 * @arg @ref LL_PWM_ACTIONEVENT_SET
1365 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1366 */
ll_pwm_get_action_event_cmp_a1(pwm_regs_t * PWMx)1367 __STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_a1(pwm_regs_t *PWMx)
1368 {
1369 return (READ_BITS(PWMx->AQCTRL, PWM_AQCTRL_A1) >> PWM_AQCTRL_A1_Pos);
1370 }
1371
1372 /**
1373 * @brief Set the channel B0 action event when PWM counter value reaches compare counter B0.
1374 *
1375 * Register|BitsName
1376 * --------|--------
1377 * AQCTRL | B0
1378 *
1379 * @param PWMx PWM instance
1380 * @param action_event This parameter can be one of the following values:
1381 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1382 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1383 * @arg @ref LL_PWM_ACTIONEVENT_SET
1384 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1385 * @retval None
1386 */
ll_pwm_set_action_event_cmp_b0(pwm_regs_t * PWMx,uint32_t action_event)1387 __STATIC_INLINE void ll_pwm_set_action_event_cmp_b0(pwm_regs_t *PWMx, uint32_t action_event)
1388 {
1389 MODIFY_REG(PWMx->AQCTRL, PWM_AQCTRL_B0, action_event << PWM_AQCTRL_B0_Pos);
1390 }
1391
1392 /**
1393 * @brief Get the channel B0 action event when PWM counter value reaches compare counter B0.
1394 *
1395 * Register|BitsName
1396 * --------|--------
1397 * AQCTRL | B0
1398 *
1399 * @param PWMx PWM instance
1400 * @retval Return value can be one of the following values:
1401 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1402 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1403 * @arg @ref LL_PWM_ACTIONEVENT_SET
1404 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1405 */
ll_pwm_get_action_event_cmp_b0(pwm_regs_t * PWMx)1406 __STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_b0(pwm_regs_t *PWMx)
1407 {
1408 return (READ_BITS(PWMx->AQCTRL, PWM_AQCTRL_B0) >> PWM_AQCTRL_B0_Pos);
1409 }
1410
1411 /**
1412 * @brief Set the channel B1 action event when PWM counter value reaches compare counter B1.
1413 *
1414 * Register|BitsName
1415 * --------|--------
1416 * AQCTRL | B1
1417 *
1418 * @param PWMx PWM instance
1419 * @param action_event This parameter can be one of the following values:
1420 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1421 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1422 * @arg @ref LL_PWM_ACTIONEVENT_SET
1423 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1424 * @retval None
1425 */
ll_pwm_set_action_event_cmp_b1(pwm_regs_t * PWMx,uint32_t action_event)1426 __STATIC_INLINE void ll_pwm_set_action_event_cmp_b1(pwm_regs_t *PWMx, uint32_t action_event)
1427 {
1428 MODIFY_REG(PWMx->AQCTRL, PWM_AQCTRL_B1, action_event << PWM_AQCTRL_B1_Pos);
1429 }
1430
1431 /**
1432 * @brief Get the channel B1 action event when PWM counter value reaches compare counter B1.
1433 *
1434 * Register|BitsName
1435 * --------|--------
1436 * AQCTRL | B1
1437 *
1438 * @param PWMx PWM instance
1439 * @retval Return value can be one of the following values:
1440 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1441 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1442 * @arg @ref LL_PWM_ACTIONEVENT_SET
1443 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1444 */
ll_pwm_get_action_event_cmp_b1(pwm_regs_t * PWMx)1445 __STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_b1(pwm_regs_t *PWMx)
1446 {
1447 return (READ_BITS(PWMx->AQCTRL, PWM_AQCTRL_B1) >> PWM_AQCTRL_B1_Pos);
1448 }
1449
1450 /**
1451 * @brief Set the channel C0 action event when PWM counter value reaches compare counter C0.
1452 *
1453 * Register|BitsName
1454 * --------|--------
1455 * AQCTRL | C0
1456 *
1457 * @param PWMx PWM instance
1458 * @param action_event This parameter can be one of the following values:
1459 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1460 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1461 * @arg @ref LL_PWM_ACTIONEVENT_SET
1462 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1463 * @retval None
1464 */
ll_pwm_set_action_event_cmp_c0(pwm_regs_t * PWMx,uint32_t action_event)1465 __STATIC_INLINE void ll_pwm_set_action_event_cmp_c0(pwm_regs_t *PWMx, uint32_t action_event)
1466 {
1467 MODIFY_REG(PWMx->AQCTRL, PWM_AQCTRL_C0, action_event << PWM_AQCTRL_C0_Pos);
1468 }
1469
1470 /**
1471 * @brief Get the channel C0 action event when PWM counter value reaches compare counter C0.
1472 *
1473 * Register|BitsName
1474 * --------|--------
1475 * AQCTRL | C0
1476 *
1477 * @param PWMx PWM instance
1478 * @retval Return value can be one of the following values:
1479 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1480 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1481 * @arg @ref LL_PWM_ACTIONEVENT_SET
1482 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1483 */
ll_pwm_get_action_event_cmp_c0(pwm_regs_t * PWMx)1484 __STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_c0(pwm_regs_t *PWMx)
1485 {
1486 return (READ_BITS(PWMx->AQCTRL, PWM_AQCTRL_C0) >> PWM_AQCTRL_C0_Pos);
1487 }
1488
1489 /**
1490 * @brief Set the channel C1 action event when PWM counter value reaches compare counter C1.
1491 *
1492 * Register|BitsName
1493 * --------|--------
1494 * AQCTRL | C1
1495 *
1496 * @param PWMx PWM instance
1497 * @param action_event This parameter can be one of the following values:
1498 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1499 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1500 * @arg @ref LL_PWM_ACTIONEVENT_SET
1501 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1502 * @retval None
1503 */
ll_pwm_set_action_event_cmp_c1(pwm_regs_t * PWMx,uint32_t action_event)1504 __STATIC_INLINE void ll_pwm_set_action_event_cmp_c1(pwm_regs_t *PWMx, uint32_t action_event)
1505 {
1506 MODIFY_REG(PWMx->AQCTRL, PWM_AQCTRL_C1, action_event << PWM_AQCTRL_C1_Pos);
1507 }
1508
1509 /**
1510 * @brief Get the channel C1 action event when PWM counter value reaches compare counter C1.
1511 *
1512 * Register|BitsName
1513 * --------|--------
1514 * AQCTRL | C1
1515 *
1516 * @param PWMx PWM instance
1517 * @retval Return value can be one of the following values:
1518 * @arg @ref LL_PWM_ACTIONEVENT_NONE
1519 * @arg @ref LL_PWM_ACTIONEVENT_CLEAR
1520 * @arg @ref LL_PWM_ACTIONEVENT_SET
1521 * @arg @ref LL_PWM_ACTIONEVENT_TOGGLE
1522 */
ll_pwm_get_action_event_cmp_c1(pwm_regs_t * PWMx)1523 __STATIC_INLINE uint32_t ll_pwm_get_action_event_cmp_c1(pwm_regs_t *PWMx)
1524 {
1525 return (READ_BITS(PWMx->AQCTRL, PWM_AQCTRL_C1) >> PWM_AQCTRL_C1_Pos);
1526 }
1527
1528 /**
1529 * @brief Set the breath prescaler in breath mode.
1530 *
1531 * Register|BitsName
1532 * --------|--------
1533 * BRPRD | BRPRD
1534 *
1535 * @param PWMx PWM instance
1536 * @param bprescaler This parameter ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1537 * @retval None
1538 */
ll_pwm_set_breath_prescaler(pwm_regs_t * PWMx,uint32_t bprescaler)1539 __STATIC_INLINE void ll_pwm_set_breath_prescaler(pwm_regs_t *PWMx, uint32_t bprescaler)
1540 {
1541 MODIFY_REG(PWMx->BRPRD, PWM_BRPRD_BRPRD, bprescaler);
1542 }
1543
1544 /**
1545 * @brief Get the breath prescaler in breath mode.
1546 *
1547 * Register|BitsName
1548 * --------|--------
1549 * BRPRD | BRPRD
1550 *
1551 * @param PWMx PWM instance
1552 * @retval Return value ranges between Min_Data=0 and Max_Data=0xFFFFFFFF
1553 */
ll_pwm_get_breath_prescaler(pwm_regs_t * PWMx)1554 __STATIC_INLINE uint32_t ll_pwm_get_breath_prescaler(pwm_regs_t *PWMx)
1555 {
1556 return (READ_BITS(PWMx->BRPRD, PWM_BRPRD_BRPRD));
1557 }
1558
1559 /**
1560 * @brief Set the hold prescaler in breath mode.
1561 *
1562 * Register|BitsName
1563 * --------|--------
1564 * HOLD | HOLD
1565 *
1566 * @param PWMx PWM instance
1567 * @param hprescaler This parameter ranges between Min_Data=0 and Max_Data=0xFFFFFF
1568 * @retval None
1569 */
ll_pwm_set_hold_prescaler(pwm_regs_t * PWMx,uint32_t hprescaler)1570 __STATIC_INLINE void ll_pwm_set_hold_prescaler(pwm_regs_t *PWMx, uint32_t hprescaler)
1571 {
1572 MODIFY_REG(PWMx->HOLD, PWM_HOLD_HOLD, hprescaler);
1573 }
1574
1575 /**
1576 * @brief Get the hold prescaler in breath mode.
1577 *
1578 * Register|BitsName
1579 * --------|--------
1580 * HOLD | HOLD
1581 *
1582 * @param PWMx PWM instance
1583 * @retval Return value ranges between Min_Data=0 and Max_Data=0xFFFFFF
1584 */
ll_pwm_get_hold_prescaler(pwm_regs_t * PWMx)1585 __STATIC_INLINE uint32_t ll_pwm_get_hold_prescaler(pwm_regs_t *PWMx)
1586 {
1587 return (READ_BITS(PWMx->HOLD, PWM_HOLD_HOLD));
1588 }
1589
1590 /** @} */
1591
1592 /** @defgroup PWM_LL_EF_Init Initialization and de-initialization functions
1593 * @{
1594 */
1595
1596 /**
1597 * @brief De-initialize PWM registers (Registers restored to their default values).
1598 * @param PWMx PWM instance
1599 * @retval An error_status_t enumeration value:
1600 * - SUCCESS: PWM registers are de-initialized
1601 * - ERROR: PWM registers are not de-initialized
1602 */
1603 error_status_t ll_pwm_deinit(pwm_regs_t *PWMx);
1604
1605 /**
1606 * @brief Initialize PWM registers according to the specified
1607 * parameters in PWM_InitStruct.
1608 * @param PWMx PWM instance
1609 * @param p_pwm_init Pointer to a ll_pwm_init_t structure that contains the configuration
1610 * information for the specified PWM peripheral.
1611 * @retval An error_status_t enumeration value:
1612 * - SUCCESS: PWM registers are initialized according to p_pwm_init content
1613 * - ERROR: Problem occurred during PWM Registers initialization
1614 */
1615 error_status_t ll_pwm_init(pwm_regs_t *PWMx, ll_pwm_init_t *p_pwm_init);
1616
1617 /**
1618 * @brief Set each field of a @ref ll_pwm_init_t type structure to default value.
1619 * @param p_pwm_init Pointer to a @ref ll_pwm_init_t structure
1620 * whose fields will be set to default values.
1621 * @retval None
1622 */
1623 void ll_pwm_struct_init(ll_pwm_init_t *p_pwm_init);
1624
1625 /** @} */
1626
1627 /** @} */
1628
1629 #endif /* PWM0 || PWM1 */
1630
1631 #ifdef __cplusplus
1632 }
1633 #endif
1634
1635 #endif /* __GR55XX_LL_PWM_H__ */
1636
1637 /** @} */
1638
1639 /** @} */
1640
1641 /** @} */
1642