1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_spi.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of SPI LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_SPI SPI
47 * @brief SPI LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55xx_LL_SPI_H__
53 #define __GR55xx_LL_SPI_H__
54
55 /* Includes ------------------------------------------------------------------*/
56 #include "gr55xx.h"
57
58 #ifdef __cplusplus
59 extern "C" {
60 #endif
61
62 #if defined (SPIM) || defined (SPIS) || defined (QSPI0) || defined (QSPI1)
63
64 /** @defgroup LL_SPI_DRIVER_STRUCTURES Structures
65 * @{
66 */
67
68 /* Exported types ------------------------------------------------------------*/
69 /** @defgroup SPI_LL_ES_INIT SPI Exported init structure
70 * @{
71 */
72
73 /**
74 * @brief LL SPIM init structures definition
75 */
76 typedef struct _ll_spim_init_t {
77 uint32_t transfer_direction; /**< Specifies the SPI unidirectional or bidirectional data mode.
78 This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
79
80 This feature can be modified afterwards using unitary function
81 @ref ll_spi_set_transfer_direction(). */
82
83 uint32_t data_size; /**< Specifies the SPI data size.
84 This parameter can be a value of @ref SPI_LL_EC_DATASIZE.
85
86 This feature can be modified afterwards using unitary function
87 @ref ll_spi_set_data_size(). */
88
89 uint32_t clock_polarity; /**< Specifies the serial clock steady state.
90 This parameter can be a value of @ref SPI_LL_EC_POLARITY.
91
92 This feature can be modified afterwards using unitary function
93 @ref ll_spi_set_clock_polarity(). */
94
95 uint32_t clock_phase; /**< Specifies the clock active edge for the bit capture.
96 This parameter can be a value of @ref SPI_LL_EC_PHASE.
97
98 This feature can be modified afterwards using unitary function
99 @ref ll_spi_set_clock_phase(). */
100
101 uint32_t slave_select; /**< Specifies the SPI slave select.
102 This parameter can be a value of @ref SPI_LL_EC_SLAVESELECT.
103
104 This feature can be modified afterwards using unitary function
105 @ref ll_spi_enable_ss(). */
106
107 uint32_t baud_rate; /**< Specifies the BaudRate prescaler value which will be used to
108 configure the transmit and receive SCK clock.
109 This parameter can be one even value between 2 and 65534,
110 if the value is 0, the SCLK is disable.
111 @note The communication clock is derived from the master clock.
112 The slave clock does not need to be set.
113
114 This feature can be modified afterwards using unitary function
115 @ref ll_spi_set_baud_rate_prescaler(). */
116 } ll_spim_init_t;
117
118 /**
119 * @brief SPIS init structures definition
120 */
121 typedef struct _ll_spis_init_t {
122 uint32_t data_size; /**< Specifies the SPI data width.
123 This parameter can be a value of @ref SPI_LL_EC_DATASIZE.
124
125 This feature can be modified afterwards using unitary function
126 @ref ll_spi_set_data_size(). */
127
128 uint32_t clock_polarity; /**< Specifies the serial clock steady state.
129 This parameter can be a value of @ref SPI_LL_EC_POLARITY.
130
131 This feature can be modified afterwards using unitary function
132 @ref ll_spi_set_clock_polarity(). */
133
134 uint32_t clock_phase; /**< Specifies the clock active edge for the bit capture.
135 This parameter can be a value of @ref SPI_LL_EC_PHASE.
136
137 This feature can be modified afterwards using unitary function
138 @ref ll_spi_set_clock_phase(). */
139 } ll_spis_init_t;
140
141 /**
142 * @brief QSPI init structures definition
143 */
144 typedef struct _ll_qspi_init_t {
145 uint32_t transfer_direction; /**< Specifies the QSPI transfer or receive mode.
146 This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
147
148 This feature can be modified afterwards using unitary function
149 @ref ll_spi_set_transfer_direction(). */
150
151 uint32_t instruction_size; /**< Specifies the QSPI instruction width.
152 This parameter can be a value of @ref SPI_LL_EC_INSTRUCTIONSIZE.
153
154 This feature can be modified afterwards using unitary function
155 @ref ll_spi_set_instruction_size(). */
156
157 uint32_t address_size; /**< Specifies the QSPI address width.
158 This parameter can be a value of @ref SPI_LL_EC_ADDRESSSIZE.
159
160 This feature can be modified afterwards using unitary function
161 @ref ll_spi_set_address_size(). */
162
163 uint32_t inst_addr_transfer_format; /**< Specifies the QSPI instruction and address transfer format.
164 This parameter can be a value of
165 @ref SPI_LL_EC_ADDRINSTTRNASFERFORMAT.
166
167 This feature can be modified afterwards using unitary function
168 @ref ll_spi_set_add_inst_transfer_format(). */
169
170 uint32_t wait_cycles; /**< Specifies the QSPI dummy clock.
171 This parameter can be one of the following values: 0 ~ 31.
172
173 This feature can be modified afterwards using unitary function
174 @ref ll_spi_set_wait_cycles(). */
175
176 uint32_t data_size; /**< Specifies the SPI data width.
177 This parameter can be a value of @ref SPI_LL_EC_DATASIZE.
178
179 This feature can be modified afterwards using unitary function
180 @ref ll_spi_set_data_size(). */
181
182 uint32_t clock_polarity; /**< Specifies the serial clock steady state.
183 This parameter can be a value of @ref SPI_LL_EC_POLARITY.
184
185 This feature can be modified afterwards using unitary function
186 @ref ll_spi_set_clock_polarity(). */
187
188 uint32_t clock_phase; /**< Specifies the clock active edge for the bit capture.
189 This parameter can be a value of @ref SPI_LL_EC_PHASE.
190
191 This feature can be modified afterwards using unitary function
192 @ref ll_spi_set_clock_phase(). */
193
194 uint32_t baud_rate; /**< Specifies the BaudRate prescaler value which will be used to
195 configure the transmit and receive SCK clock.
196 This parameter can be one even value between 2 and 65534,
197 if the value is 0, the SCLK is disable.
198 @note The communication clock is derived from the master clock.
199 The slave clock does not need to be set.
200
201 This feature can be modified afterwards using unitary function
202 @ref ll_spi_set_baud_rate_prescaler(). */
203
204 uint32_t rx_sample_delay; /**< Specifies the RX sample delay.
205 It is used to delay the sample of the RX input port.
206 This parameter can be a number between 0 and 0x7 */
207 } ll_qspi_init_t;
208
209 /** @} */
210
211 /** @} */
212
213 /**
214 * @defgroup SPI_LL_MACRO Defines
215 * @{
216 */
217
218 /* Exported constants --------------------------------------------------------*/
219 /** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
220 * @{
221 */
222
223 /** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
224 * @brief Flags definitions which can be used with LL_SPI_ReadReg function
225 * @{
226 */
227 #define LL_SSI_SR_DCOL SSI_STAT_DCOL /**< Data collision error flag */
228 #define LL_SSI_SR_TXE SSI_STAT_TXE /**< Transmission error flag */
229 #define LL_SSI_SR_RFF SSI_STAT_RFF /**< Rx FIFO full flag */
230 #define LL_SSI_SR_RFNE SSI_STAT_RFNE /**< Rx FIFO not empty flag */
231 #define LL_SSI_SR_TFE SSI_STAT_TFE /**< Tx FIFO empty flag */
232 #define LL_SSI_SR_TFNF SSI_STAT_TFNF /**< Tx FIFO not full flag */
233 #define LL_SSI_SR_BUSY SSI_STAT_BUSY /**< Busy flag */
234 /** @} */
235
236 /** @defgroup SPI_LL_EC_IT IT Defines
237 * @brief Interrupt definitions which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
238 * @{
239 */
240 #define LL_SSI_IM_MST SSI_INTMASK_MSTIM /**< Multi-Master Contention Interrupt
241 enable */
242 #define LL_SSI_IM_RXF SSI_INTMASK_RXFIM /**< Receive FIFO Full Interrupt
243 enable */
244 #define LL_SSI_IM_RXO SSI_INTMASK_RXOIM /**< Receive FIFO Overflow Interrupt
245 enable */
246 #define LL_SSI_IM_RXU SSI_INTMASK_RXUIM /**< Receive FIFO Underflow Interrupt
247 enable */
248 #define LL_SSI_IM_TXO SSI_INTMASK_TXOIM /**< Transmit FIFO Overflow Interrupt
249 enable */
250 #define LL_SSI_IM_TXE SSI_INTMASK_TXEIM /**< Transmit FIFO Empty Interrupt
251 enable */
252
253 #define LL_SSI_IS_MST SSI_INTSTAT_MSTIS /**< Multi-Master Contention Interrupt
254 flag */
255 #define LL_SSI_IS_RXF SSI_INTSTAT_RXFIS /**< Receive FIFO Full Interrupt flag */
256 #define LL_SSI_IS_RXO SSI_INTSTAT_RXOIS /**< Receive FIFO Overflow Interrupt
257 flag */
258 #define LL_SSI_IS_RXU SSI_INTSTAT_RXUIS /**< Receive FIFO Underflow Interrupt
259 flag */
260 #define LL_SSI_IS_TXO SSI_INTSTAT_TXOIS /**< Transmit FIFO Overflow Interrupt
261 flag */
262 #define LL_SSI_IS_TXE SSI_INTSTAT_TXEIS /**< Transmit FIFO Empty Interrupt
263 flag */
264
265 #define LL_SSI_RIS_MST SSI_RAW_INTSTAT_MSTIR /**< Multi-Master Contention RAW Interrupt
266 flag */
267 #define LL_SSI_RIS_RXF SSI_RAW_INTSTAT_RXFIR /**< Receive FIFO Full RAW Interrupt
268 flag */
269 #define LL_SSI_RIS_RXO SSI_RAW_INTSTAT_RXOIR /**< Receive FIFO Overflow RAW Interrupt
270 flag */
271 #define LL_SSI_RIS_RXU SSI_RAW_INTSTAT_RXUIR /**< Receive FIFO Underflow RAW Interrupt
272 flag */
273 #define LL_SSI_RIS_TXO SSI_RAW_INTSTAT_TXOIR /**< Transmit FIFO Overflow RAW Interrupt
274 flag */
275 #define LL_SSI_RIS_TXE SSI_RAW_INTSTAT_TXEIR /**< Transmit FIFO Empty RAW Interrupt
276 flag */
277 /** @} */
278
279 /** @defgroup SPI_LL_EC_SPIFRAMEFORMAT SPI Frame Format
280 * @{
281 */
282 #define LL_SSI_FRF_SPI 0x00000000UL /**< SPI frame format for transfer */
283 #define LL_SSI_FRF_DUALSPI (1UL << SSI_CTRL0_SPIFRF_Pos) /**< Dual-SPI frame format for transfer */
284 #define LL_SSI_FRF_QUADSPI (2UL << SSI_CTRL0_SPIFRF_Pos) /**< Quad-SPI frame format for transfer */
285 /** @} */
286
287 /** @defgroup SPI_LL_EC_DATASIZE Datawidth
288 * @{
289 */
290 #define LL_SSI_DATASIZE_4BIT (3UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 4 bits */
291 #define LL_SSI_DATASIZE_5BIT (4UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 5 bits */
292 #define LL_SSI_DATASIZE_6BIT (5UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 6 bits */
293 #define LL_SSI_DATASIZE_7BIT (6UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 7 bits */
294 #define LL_SSI_DATASIZE_8BIT (7UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 8 bits */
295 #define LL_SSI_DATASIZE_9BIT (8UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 9 bits */
296 #define LL_SSI_DATASIZE_10BIT (9UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 10 bits */
297 #define LL_SSI_DATASIZE_11BIT (10UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 11 bits */
298 #define LL_SSI_DATASIZE_12BIT (11UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 12 bits */
299 #define LL_SSI_DATASIZE_13BIT (12UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 13 bits */
300 #define LL_SSI_DATASIZE_14BIT (13UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 14 bits */
301 #define LL_SSI_DATASIZE_15BIT (14UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 15 bits */
302 #define LL_SSI_DATASIZE_16BIT (15UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 16 bits */
303 #define LL_SSI_DATASIZE_17BIT (16UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 17 bits */
304 #define LL_SSI_DATASIZE_18BIT (17UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 18 bits */
305 #define LL_SSI_DATASIZE_19BIT (18UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 19 bits */
306 #define LL_SSI_DATASIZE_20BIT (19UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 20 bits */
307 #define LL_SSI_DATASIZE_21BIT (20UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 21 bits */
308 #define LL_SSI_DATASIZE_22BIT (21UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 22 bits */
309 #define LL_SSI_DATASIZE_23BIT (22UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 23 bits */
310 #define LL_SSI_DATASIZE_24BIT (23UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 24 bits */
311 #define LL_SSI_DATASIZE_25BIT (24UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 25 bits */
312 #define LL_SSI_DATASIZE_26BIT (25UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 26 bits */
313 #define LL_SSI_DATASIZE_27BIT (26UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 27 bits */
314 #define LL_SSI_DATASIZE_28BIT (27UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 28 bits */
315 #define LL_SSI_DATASIZE_29BIT (28UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 29 bits */
316 #define LL_SSI_DATASIZE_30BIT (29UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 30 bits */
317 #define LL_SSI_DATASIZE_31BIT (30UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 31 bits */
318 #define LL_SSI_DATASIZE_32BIT (31UL << SSI_CTRL0_DFS32_Pos) /**< Data length for SPI transfer: 32 bits */
319 /** @} */
320
321 /** @defgroup SPI_LL_EC_MICROWIRECOMMANDSIZE MicroWire CommandSize
322 * @{
323 */
324 #define LL_SSI_MW_CMDSIZE_1BIT 0x00000000UL /**< CMD length for Microwire
325 transfer: 1 bits */
326 #define LL_SSI_MW_CMDSIZE_2BIT (1UL << SSI_CTRL0_CFS_Pos) /**< CMD length for Microwire
327 transfer: 2 bits */
328 #define LL_SSI_MW_CMDSIZE_3BIT (2UL << SSI_CTRL0_CFS_Pos) /**< CMD length for Microwire
329 transfer: 3 bits */
330 #define LL_SSI_MW_CMDSIZE_4BIT (3UL << SSI_CTRL0_CFS_Pos) /**< CMD length for Microwire
331 transfer: 4 bits */
332 #define LL_SSI_MW_CMDSIZE_5BIT (4UL << SSI_CTRL0_CFS_Pos) /**< CMD length for Microwire
333 transfer: 5 bits */
334 #define LL_SSI_MW_CMDSIZE_6BIT (5UL << SSI_CTRL0_CFS_Pos) /**< CMD length for Microwire
335 transfer: 6 bits */
336 #define LL_SSI_MW_CMDSIZE_7BIT (6UL << SSI_CTRL0_CFS_Pos) /**< CMD length for Microwire
337 transfer: 7 bits */
338 #define LL_SSI_MW_CMDSIZE_8BIT (7UL << SSI_CTRL0_CFS_Pos) /**< CMD length for Microwire
339 transfer: 8 bits */
340 #define LL_SSI_MW_CMDSIZE_9BIT (8UL << SSI_CTRL0_CFS_Pos) /**< CMD length for Microwire
341 transfer: 9 bits */
342 #define LL_SSI_MW_CMDSIZE_10BIT (9UL << SSI_CTRL0_CFS_Pos) /**< CMD length for Microwire
343 transfer: 10 bits */
344 #define LL_SSI_MW_CMDSIZE_11BIT (10UL << SSI_CTRL0_CFS_Pos) /**< CMD length for Microwire
345 transfer: 11 bits */
346 #define LL_SSI_MW_CMDSIZE_12BIT (11UL << SSI_CTRL0_CFS_Pos) /**< CMD length for Microwire
347 transfer: 12 bits */
348 #define LL_SSI_MW_CMDSIZE_13BIT (12UL << SSI_CTRL0_CFS_Pos) /**< CMD length for Microwire
349 transfer: 13 bits */
350 #define LL_SSI_MW_CMDSIZE_14BIT (13UL << SSI_CTRL0_CFS_Pos) /**< CMD length for Microwire
351 transfer: 14 bits */
352 #define LL_SSI_MW_CMDSIZE_15BIT (14UL << SSI_CTRL0_CFS_Pos) /**< CMD length for Microwire
353 transfer: 15 bits */
354 #define LL_SSI_MW_CMDSIZE_16BIT (15UL << SSI_CTRL0_CFS_Pos) /**< CMD length for Microwire
355 transfer: 16 bits */
356 /** @} */
357
358 /** @defgroup SPI_LL_EC_TEST_MODE Test Mode
359 * @{
360 */
361 #define LL_SSI_NORMAL_MODE 0x00000000UL /**< Normal mode for SPI transfer */
362 #define LL_SSI_TEST_MODE (1UL << SSI_CTRL0_SRL_Pos) /**< Test mode for SPI transfer:
363 Rx and Tx connected inside */
364 /** @} */
365
366 /** @defgroup SPI_LL_EC_SLAVEOUT_ENABLE Slave Out Enable
367 * @{
368 */
369 #define LL_SSI_SLAVE_OUTDIS 0x00000000UL /**< Output enable for SPI transfer
370 as slave */
371 #define LL_SSI_SLAVE_OUTEN (1UL << SSI_CTRL0_SLVOE_Pos) /**< Output disable for SPI transfer
372 as slave */
373 /** @} */
374
375 /** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
376 * @{
377 */
378 #define LL_SSI_FULL_DUPLEX 0x00000000UL /**< Full-Duplex mode.
379 Rx and Tx transfer on 2 lines */
380 #define LL_SSI_SIMPLEX_TX (1UL << SSI_CTRL0_TMOD_Pos) /**< Simplex Tx mode.
381 Tx transfer only on 1 line */
382 #define LL_SSI_SIMPLEX_RX (2UL << SSI_CTRL0_TMOD_Pos) /**< Simplex Rx mode.
383 Rx transfer only on 1 line */
384 #define LL_SSI_READ_EEPROM (3UL << SSI_CTRL0_TMOD_Pos) /**< Read EEPROM mode.
385 Rx transfer only on 1 line */
386 /** @} */
387
388 /** @defgroup SPI_LL_EC_PHASE Clock Phase
389 * @{
390 */
391 #define LL_SSI_SCPHA_1EDGE 0x00000000UL /**< First clock transition is
392 the first data capture edge */
393 #define LL_SSI_SCPHA_2EDGE (1UL << SSI_CTRL0_SCPHA_Pos) /**< Second clock transition is
394 the first data capture edge */
395 /** @} */
396
397 /** @defgroup SPI_LL_EC_POLARITY Clock Polarity
398 * @{
399 */
400 #define LL_SSI_SCPOL_LOW 0x00000000UL /**< Clock to 0 when idle */
401 #define LL_SSI_SCPOL_HIGH (1UL << SSI_CTRL0_SCPOL_Pos) /**< Clock to 1 when idle */
402 /** @} */
403
404 /** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
405 * @{
406 */
407 #define LL_SSI_PROTOCOL_MOTOROLA 0x00000000UL /**< Motorola mode. Used as default value */
408 #define LL_SSI_PROTOCOL_TI (1UL << SSI_CTRL0_FRF_Pos) /**< TI mode */
409 #define LL_SSI_PROTOCOL_MICROWIRE (2UL << SSI_CTRL0_FRF_Pos) /**< Microwire mode */
410 /** @} */
411
412 /** @defgroup SPI_LL_EC_MICROWIRECONTROL MicroWire Control
413 * @{
414 */
415 #define LL_SSI_MICROWIRE_HANDSHAKE_DIS 0x00000000UL /**< Enable Handshake for Microwire
416 transfer */
417 #define LL_SSI_MICROWIRE_HANDSHAKE_EN (1UL << SSI_MWC_MHS_Pos) /**< Disable Handshake for Microwire
418 transfer */
419
420 #define LL_SSI_MICROWIRE_RX 0x00000000UL /**< Rx mode. Rx transfer at Microwire mode */
421 #define LL_SSI_MICROWIRE_TX (1UL << SSI_MWC_MDD_Pos) /**< Tx mode. Tx transfer at Microwire mode */
422
423 #define LL_SSI_MICROWIRE_NON_SEQUENTIAL 0x00000000UL /**< Non-sequential for Microwire transfer */
424 #define LL_SSI_MICROWIRE_SEQUENTIAL (1UL << SSI_MWC_MWMOD_Pos) /**< Sequential for Microwire transfer */
425 /** @} */
426
427 /** @defgroup SPI_LL_EC_SLAVESELECT Slave Select
428 * @{
429 */
430 #define LL_SSI_SLAVE1 SSI_SE_SLAVE1 /**< Enable slave1 select pin for SPI
431 transfer */
432 #define LL_SSI_SLAVE0 SSI_SE_SLAVE0 /**< Enable slave0 select pin for SPI
433 transfer */
434 /** @} */
435
436 /** @defgroup SPI_LL_EC_DMA DMA Defines
437 * @{
438 */
439 #define LL_SSI_DMA_TX_DIS 0x00000000UL /**< Disable the transmit FIFO DMA channel */
440 #define LL_SSI_DMA_TX_EN SSI_DMAC_TDMAE /**< Enable the transmit FIFO DMA channel */
441
442 #define LL_SSI_DMA_RX_DIS 0x00000000UL /**< Disable the receive FIFO DMA channel */
443 #define LL_SSI_DMA_RX_EN SSI_DMAC_RDMAE /**< Enable the receive FIFO DMA channel */
444 /** @} */
445
446 /** @defgroup SPI_LL_EC_INSTRUCTIONSIZE QSPI Instruction Size
447 * @{
448 */
449 #define LL_SSI_INSTSIZE_0BIT 0x00000000UL /**< Instruction length for QSPI
450 transfer: 0 bits */
451 #define LL_SSI_INSTSIZE_4BIT (1UL << SSI_SCTRL0_INSTL_Pos) /**< Instructoin length for QSPI
452 transfer: 4 bits */
453 #define LL_SSI_INSTSIZE_8BIT (2UL << SSI_SCTRL0_INSTL_Pos) /**< Instructoin length for QSPI
454 transfer: 8 bits */
455 #define LL_SSI_INSTSIZE_16BIT (3UL << SSI_SCTRL0_INSTL_Pos) /**< Instructoin length for QSPI
456 transfer: 16 bits */
457 /** @} */
458
459 /** @defgroup SPI_LL_EC_ADDRESSSIZE QSPI Address Size
460 * @{
461 */
462 #define LL_SSI_ADDRSIZE_0BIT 0x00000000UL /**< Address length for QSPI
463 transfer: 0 bits */
464 #define LL_SSI_ADDRSIZE_4BIT (1UL << SSI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI
465 transfer: 4 bits */
466 #define LL_SSI_ADDRSIZE_8BIT (2UL << SSI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI
467 transfer: 8 bits */
468 #define LL_SSI_ADDRSIZE_12BIT (3UL << SSI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI
469 transfer: 12 bits */
470 #define LL_SSI_ADDRSIZE_16BIT (4UL << SSI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI
471 transfer: 16 bits */
472 #define LL_SSI_ADDRSIZE_20BIT (5UL << SSI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI
473 transfer: 20 bits */
474 #define LL_SSI_ADDRSIZE_24BIT (6UL << SSI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI
475 transfer: 24 bits */
476 #define LL_SSI_ADDRSIZE_28BIT (7UL << SSI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI
477 transfer: 28 bits */
478 #define LL_SSI_ADDRSIZE_32BIT (8UL << SSI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI
479 transfer: 32 bits */
480 #define LL_SSI_ADDRSIZE_36BIT (9UL << SSI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI
481 transfer: 36 bits */
482 #define LL_SSI_ADDRSIZE_40BIT (10UL << SSI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI
483 transfer: 40 bits */
484 #define LL_SSI_ADDRSIZE_44BIT (11UL << SSI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI
485 transfer: 44 bits */
486 #define LL_SSI_ADDRSIZE_48BIT (12UL << SSI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI
487 transfer: 48 bits */
488 #define LL_SSI_ADDRSIZE_52BIT (13UL << SSI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI
489 transfer: 52 bits */
490 #define LL_SSI_ADDRSIZE_56BIT (14UL << SSI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI
491 transfer: 56 bits */
492 #define LL_SSI_ADDRSIZE_60BIT (15UL << SSI_SCTRL0_ADDRL_Pos) /**< Address length for QSPI
493 transfer: 60 bits */
494 /** @} */
495
496 /** @defgroup SPI_LL_EC_ADDRINSTTRNASFERFORMAT QSPI Address and Instruction Transfer Format
497 * @{
498 */
499 #define LL_SSI_INST_ADDR_ALL_IN_SPI 0x00000000UL /**< Instruction and address are sent
500 in SPI mode */
501 #define LL_SSI_INST_IN_SPI_ADDR_IN_SPIFRF (1UL << SSI_SCTRL0_TRANSTYPE_Pos) /**< Instruction is in sent in SPI mode
502 and address is sent in Daul/Quad
503 SPI mode */
504 #define LL_SSI_INST_ADDR_ALL_IN_SPIFRF (2UL << SSI_SCTRL0_TRANSTYPE_Pos) /**< Instruction and address are sent
505 in Daul/Quad SPI mode */
506 /** @} */
507
508 /** @defgroup SPI_LL_EC_DEFAULT_CONFIG InitStrcut default configuartion
509 * @{
510 */
511
512 /**
513 * @brief LL SPIM InitStrcut default configuartion
514 */
515 #define LL_SPIM_DEFAULT_CONFIG \
516 { \
517 .transfer_direction = LL_SSI_FULL_DUPLEX, \
518 .data_size = LL_SSI_DATASIZE_8BIT, \
519 .clock_polarity = LL_SSI_SCPOL_LOW, \
520 .clock_phase = LL_SSI_SCPHA_1EDGE, \
521 .slave_select = LL_SSI_SLAVE0, \
522 .baud_rate = SystemCoreClock / 2000000, \
523 }
524
525 /**
526 * @brief LL SPIS InitStrcut default configuartion
527 */
528 #define LL_SPIS_DEFAULT_CONFIG \
529 { \
530 .data_size = LL_SSI_DATASIZE_8BIT, \
531 .clock_polarity = LL_SSI_SCPOL_LOW, \
532 .clock_phase = LL_SSI_SCPHA_1EDGE, \
533 }
534
535 /**
536 * @brief LL QSPI InitStrcut default configuartion
537 */
538 #define LL_QSPI_DEFAULT_CONFIG \
539 { \
540 .transfer_direction = LL_SSI_SIMPLEX_TX, \
541 .instruction_size = LL_SSI_INSTSIZE_8BIT, \
542 .address_size = LL_SSI_ADDRSIZE_24BIT, \
543 .inst_addr_transfer_format = LL_SSI_INST_ADDR_ALL_IN_SPI, \
544 .wait_cycles = 0, \
545 .data_size = LL_SSI_DATASIZE_8BIT, \
546 .clock_polarity = LL_SSI_SCPOL_LOW, \
547 .clock_phase = LL_SSI_SCPHA_1EDGE, \
548 .baud_rate = SystemCoreClock / 1000000, \
549 .rx_sample_delay = 0, \
550 }
551 /** @} */
552
553 /** @} */
554
555 /* Exported macro ------------------------------------------------------------*/
556 /** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
557 * @{
558 */
559
560 /** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
561 * @{
562 */
563
564 /**
565 * @brief Write a value in SPI register
566 * @param __instance__ SPI instance
567 * @param __REG__ Register to be written
568 * @param __VALUE__ Value to be written in the register
569 * @retval None
570 */
571 #define LL_SPI_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
572
573 /**
574 * @brief Read a value in SPI register
575 * @param __instance__ SPI instance
576 * @param __REG__ Register to be read
577 * @retval Register value
578 */
579 #define LL_SPI_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
580
581 /** @} */
582
583 /** @} */
584
585 /** @} */
586
587 /* Exported functions --------------------------------------------------------*/
588 /** @defgroup SPI_LL_DRIVER_FUNCTIONS Functions
589 * @{
590 */
591
592 /** @defgroup SPI_LL_EF_Configuration Configuration functions
593 * @{
594 */
595
596 /**
597 * @brief Enable slave select toggle
598 * @note This bit should not be changed when communication is ongoing.
599 *
600 * Register|BitsName
601 * --------|--------
602 * CTRL0 | SSTEN
603 *
604 * @param SPIx SPI instance
605 * @retval None
606 */
ll_spi_enable_ss_toggle(ssi_regs_t * SPIx)607 __STATIC_INLINE void ll_spi_enable_ss_toggle(ssi_regs_t *SPIx)
608 {
609 SET_BITS(SPIx->CTRL0, SSI_CTRL0_SSTEN);
610 }
611
612 /**
613 * @brief Disable slave select toggle
614 * @note This bit should not be changed when communication is ongoing.
615 *
616 * Register|BitsName
617 * --------|--------
618 * CTRL0 | SSTEN
619 *
620 * @param SPIx SPI instance
621 * @retval None
622 */
ll_spi_disable_ss_toggle(ssi_regs_t * SPIx)623 __STATIC_INLINE void ll_spi_disable_ss_toggle(ssi_regs_t *SPIx)
624 {
625 CLEAR_BITS(SPIx->CTRL0, SSI_CTRL0_SSTEN);
626 }
627
628 /**
629 * @brief Check if slave select toggle is enabled
630 * @note This bit should not be changed when communication is ongoing.
631 *
632 * Register|BitsName
633 * --------|--------
634 * CTRL0 | SSTEN
635 *
636 * @param SPIx SPI instance
637 * @retval State of bit (1 or 0).
638 */
ll_spi_is_enabled_ss_toggle(ssi_regs_t * SPIx)639 __STATIC_INLINE uint32_t ll_spi_is_enabled_ss_toggle(ssi_regs_t *SPIx)
640 {
641 return (READ_BITS(SPIx->CTRL0, SSI_CTRL0_SSTEN) == (SSI_CTRL0_SSTEN));
642 }
643
644 /**
645 * @brief Set data frame format for transmitting/receiving the data
646 * @note This bit should be written only when SPI is disabled (SSI_EN = 0) for correct operation.
647 *
648 * Register|BitsName
649 * --------|--------
650 * CTRL0 | SPIFRF
651 *
652 * @param SPIx SPI instance
653 * @param frf This parameter can be one of the following values:
654 * @arg @ref LL_SSI_FRF_SPI
655 * @arg @ref LL_SSI_FRF_DUALSPI
656 * @arg @ref LL_SSI_FRF_QUADSPI
657 * @retval None
658 */
ll_spi_set_frame_format(ssi_regs_t * SPIx,uint32_t frf)659 __STATIC_INLINE void ll_spi_set_frame_format(ssi_regs_t *SPIx, uint32_t frf)
660 {
661 MODIFY_REG(SPIx->CTRL0, SSI_CTRL0_SPIFRF, frf);
662 }
663
664 /**
665 * @brief Get data frame format for transmitting/receiving the data
666 * @note This bit should be written only when SPI is disabled (SSI_EN = 0) for correct operation.
667 *
668 * Register|BitsName
669 * --------|--------
670 * CTRL0 | SPIFRF
671 *
672 * @param SPIx SPI instance
673 * @retval Returned value can be one of the following values:
674 * @arg @ref LL_SSI_FRF_SPI
675 * @arg @ref LL_SSI_FRF_DUALSPI
676 * @arg @ref LL_SSI_FRF_QUADSPI
677 */
ll_spi_get_frame_format(ssi_regs_t * SPIx)678 __STATIC_INLINE uint32_t ll_spi_get_frame_format(ssi_regs_t *SPIx)
679 {
680 return (uint32_t)(READ_BITS(SPIx->CTRL0, SSI_CTRL0_SPIFRF));
681 }
682
683 /**
684 * @brief Set frame data size
685 *
686 * Register|BitsName
687 * --------|--------
688 * CTRL0 | DFS32
689 *
690 * @param SPIx SPI instance
691 * @param size This parameter can be one of the following values:
692 * @arg @ref LL_SSI_DATASIZE_4BIT
693 * @arg @ref LL_SSI_DATASIZE_5BIT
694 * @arg @ref LL_SSI_DATASIZE_6BIT
695 * @arg @ref LL_SSI_DATASIZE_7BIT
696 * @arg @ref LL_SSI_DATASIZE_8BIT
697 * @arg @ref LL_SSI_DATASIZE_9BIT
698 * @arg @ref LL_SSI_DATASIZE_10BIT
699 * @arg @ref LL_SSI_DATASIZE_11BIT
700 * @arg @ref LL_SSI_DATASIZE_12BIT
701 * @arg @ref LL_SSI_DATASIZE_13BIT
702 * @arg @ref LL_SSI_DATASIZE_14BIT
703 * @arg @ref LL_SSI_DATASIZE_15BIT
704 * @arg @ref LL_SSI_DATASIZE_16BIT
705 * @arg @ref LL_SSI_DATASIZE_17BIT
706 * @arg @ref LL_SSI_DATASIZE_18BIT
707 * @arg @ref LL_SSI_DATASIZE_19BIT
708 * @arg @ref LL_SSI_DATASIZE_20BIT
709 * @arg @ref LL_SSI_DATASIZE_21BIT
710 * @arg @ref LL_SSI_DATASIZE_22BIT
711 * @arg @ref LL_SSI_DATASIZE_23BIT
712 * @arg @ref LL_SSI_DATASIZE_24BIT
713 * @arg @ref LL_SSI_DATASIZE_25BIT
714 * @arg @ref LL_SSI_DATASIZE_26BIT
715 * @arg @ref LL_SSI_DATASIZE_27BIT
716 * @arg @ref LL_SSI_DATASIZE_28BIT
717 * @arg @ref LL_SSI_DATASIZE_29BIT
718 * @arg @ref LL_SSI_DATASIZE_30BIT
719 * @arg @ref LL_SSI_DATASIZE_31BIT
720 * @arg @ref LL_SSI_DATASIZE_32BIT
721 * @retval None
722 */
ll_spi_set_data_size(ssi_regs_t * SPIx,uint32_t size)723 __STATIC_INLINE void ll_spi_set_data_size(ssi_regs_t *SPIx, uint32_t size)
724 {
725 MODIFY_REG(SPIx->CTRL0, SSI_CTRL0_DFS32, size);
726 }
727
728 /**
729 * @brief Get frame data size
730 *
731 * Register|BitsName
732 * --------|--------
733 * CTRL0 | DFS32
734 *
735 * @param SPIx SPI instance
736 * @retval Returned value can be one of the following values:
737 * @arg @ref LL_SSI_DATASIZE_4BIT
738 * @arg @ref LL_SSI_DATASIZE_5BIT
739 * @arg @ref LL_SSI_DATASIZE_6BIT
740 * @arg @ref LL_SSI_DATASIZE_7BIT
741 * @arg @ref LL_SSI_DATASIZE_8BIT
742 * @arg @ref LL_SSI_DATASIZE_9BIT
743 * @arg @ref LL_SSI_DATASIZE_10BIT
744 * @arg @ref LL_SSI_DATASIZE_11BIT
745 * @arg @ref LL_SSI_DATASIZE_12BIT
746 * @arg @ref LL_SSI_DATASIZE_13BIT
747 * @arg @ref LL_SSI_DATASIZE_14BIT
748 * @arg @ref LL_SSI_DATASIZE_15BIT
749 * @arg @ref LL_SSI_DATASIZE_16BIT
750 * @arg @ref LL_SSI_DATASIZE_17BIT
751 * @arg @ref LL_SSI_DATASIZE_18BIT
752 * @arg @ref LL_SSI_DATASIZE_19BIT
753 * @arg @ref LL_SSI_DATASIZE_20BIT
754 * @arg @ref LL_SSI_DATASIZE_21BIT
755 * @arg @ref LL_SSI_DATASIZE_22BIT
756 * @arg @ref LL_SSI_DATASIZE_23BIT
757 * @arg @ref LL_SSI_DATASIZE_24BIT
758 * @arg @ref LL_SSI_DATASIZE_25BIT
759 * @arg @ref LL_SSI_DATASIZE_26BIT
760 * @arg @ref LL_SSI_DATASIZE_27BIT
761 * @arg @ref LL_SSI_DATASIZE_28BIT
762 * @arg @ref LL_SSI_DATASIZE_29BIT
763 * @arg @ref LL_SSI_DATASIZE_30BIT
764 * @arg @ref LL_SSI_DATASIZE_31BIT
765 * @arg @ref LL_SSI_DATASIZE_32BIT
766 */
ll_spi_get_data_size(ssi_regs_t * SPIx)767 __STATIC_INLINE uint32_t ll_spi_get_data_size(ssi_regs_t *SPIx)
768 {
769 return (uint32_t)(READ_BITS(SPIx->CTRL0, SSI_CTRL0_DFS32));
770 }
771
772 /**
773 * @brief Set the length of the control word for the Microwire frame format
774 * @note This bit should be written only when SPI is disabled (SSI_EN = 0) for correct operation.
775 *
776 * Register|BitsName
777 * --------|--------
778 * CTRL0 | CFS
779 *
780 * @param SPIx SPI instance
781 * @param size This parameter can be one of the following values:
782 * @arg @ref LL_SSI_MW_CMDSIZE_1BIT
783 * @arg @ref LL_SSI_MW_CMDSIZE_2BIT
784 * @arg @ref LL_SSI_MW_CMDSIZE_3BIT
785 * @arg @ref LL_SSI_MW_CMDSIZE_4BIT
786 * @arg @ref LL_SSI_MW_CMDSIZE_5BIT
787 * @arg @ref LL_SSI_MW_CMDSIZE_6BIT
788 * @arg @ref LL_SSI_MW_CMDSIZE_7BIT
789 * @arg @ref LL_SSI_MW_CMDSIZE_8BIT
790 * @arg @ref LL_SSI_MW_CMDSIZE_9BIT
791 * @arg @ref LL_SSI_MW_CMDSIZE_10BIT
792 * @arg @ref LL_SSI_MW_CMDSIZE_11BIT
793 * @arg @ref LL_SSI_MW_CMDSIZE_12BIT
794 * @arg @ref LL_SSI_MW_CMDSIZE_13BIT
795 * @arg @ref LL_SSI_MW_CMDSIZE_14BIT
796 * @arg @ref LL_SSI_MW_CMDSIZE_15BIT
797 * @arg @ref LL_SSI_MW_CMDSIZE_16BIT
798 * @retval None
799 */
ll_spi_set_control_frame_size(ssi_regs_t * SPIx,uint32_t size)800 __STATIC_INLINE void ll_spi_set_control_frame_size(ssi_regs_t *SPIx, uint32_t size)
801 {
802 MODIFY_REG(SPIx->CTRL0, SSI_CTRL0_CFS, size);
803 }
804
805 /**
806 * @brief Get the length of the control word for the Microwire frame format
807 * @note This bit should be written only when SPI is disabled (SSI_EN = 0) for correct operation.
808 *
809 * Register|BitsName
810 * --------|--------
811 * CTRL0 | CFS
812 *
813 * @param SPIx SPI instance
814 * @retval Returned value can be one of the following values:
815 * @arg @ref LL_SSI_MW_CMDSIZE_1BIT
816 * @arg @ref LL_SSI_MW_CMDSIZE_2BIT
817 * @arg @ref LL_SSI_MW_CMDSIZE_3BIT
818 * @arg @ref LL_SSI_MW_CMDSIZE_4BIT
819 * @arg @ref LL_SSI_MW_CMDSIZE_5BIT
820 * @arg @ref LL_SSI_MW_CMDSIZE_6BIT
821 * @arg @ref LL_SSI_MW_CMDSIZE_7BIT
822 * @arg @ref LL_SSI_MW_CMDSIZE_8BIT
823 * @arg @ref LL_SSI_MW_CMDSIZE_9BIT
824 * @arg @ref LL_SSI_MW_CMDSIZE_10BIT
825 * @arg @ref LL_SSI_MW_CMDSIZE_11BIT
826 * @arg @ref LL_SSI_MW_CMDSIZE_12BIT
827 * @arg @ref LL_SSI_MW_CMDSIZE_13BIT
828 * @arg @ref LL_SSI_MW_CMDSIZE_14BIT
829 * @arg @ref LL_SSI_MW_CMDSIZE_15BIT
830 * @arg @ref LL_SSI_MW_CMDSIZE_16BIT
831 */
ll_spi_get_control_frame_size(ssi_regs_t * SPIx)832 __STATIC_INLINE uint32_t ll_spi_get_control_frame_size(ssi_regs_t *SPIx)
833 {
834 return (uint32_t)(READ_BITS(SPIx->CTRL0, SSI_CTRL0_CFS));
835 }
836
837 /**
838 * @brief Enable SPI test mode
839 *
840 * Register|BitsName
841 * --------|--------
842 * CTRL0 | SRL
843 *
844 * @param SPIx SPI instance
845 * @retval None
846 */
ll_spi_enable_test_mode(ssi_regs_t * SPIx)847 __STATIC_INLINE void ll_spi_enable_test_mode(ssi_regs_t *SPIx)
848 {
849 SET_BITS(SPIx->CTRL0, SSI_CTRL0_SRL);
850 }
851
852 /**
853 * @brief Disable SPI test mode
854 *
855 * Register|BitsName
856 * --------|--------
857 * CTRL0 | SRL
858 *
859 * @param SPIx SPI instance
860 * @retval None
861 */
ll_spi_disable_test_mode(ssi_regs_t * SPIx)862 __STATIC_INLINE void ll_spi_disable_test_mode(ssi_regs_t *SPIx)
863 {
864 CLEAR_BITS(SPIx->CTRL0, SSI_CTRL0_SRL);
865 }
866
867 /**
868 * @brief Check if SPI test mode is enabled
869 *
870 * Register|BitsName
871 * --------|--------
872 * CTRL0 | SRL
873 *
874 * @param SPIx SPI instance
875 * @retval State of bit (1 or 0).
876 */
ll_spi_is_enabled_test_mode(ssi_regs_t * SPIx)877 __STATIC_INLINE uint32_t ll_spi_is_enabled_test_mode(ssi_regs_t *SPIx)
878 {
879 return (READ_BITS(SPIx->CTRL0, SSI_CTRL0_SRL) == (SSI_CTRL0_SRL));
880 }
881
882 /**
883 * @brief Enable slave output
884 *
885 * Register|BitsName
886 * --------|--------
887 * CTRL0 | SLVOE
888 *
889 * @param SPIx SPI instance
890 * @retval None
891 */
ll_spi_enable_slave_out(ssi_regs_t * SPIx)892 __STATIC_INLINE void ll_spi_enable_slave_out(ssi_regs_t *SPIx)
893 {
894 CLEAR_BITS(SPIx->CTRL0, SSI_CTRL0_SLVOE);
895 }
896
897 /**
898 * @brief Disable slave output
899 *
900 * Register|BitsName
901 * --------|--------
902 * CTRL0 | SLVOE
903 *
904 * @param SPIx SPI instance
905 * @retval None
906 */
ll_spi_disable_salve_out(ssi_regs_t * SPIx)907 __STATIC_INLINE void ll_spi_disable_salve_out(ssi_regs_t *SPIx)
908 {
909 SET_BITS(SPIx->CTRL0, SSI_CTRL0_SLVOE);
910 }
911
912 /**
913 * @brief Check if slave output is enabled
914 *
915 * Register|BitsName
916 * --------|--------
917 * CTRL0 | SLVOE
918 *
919 * @param SPIx SPI instance
920 * @retval State of bit (1 or 0).
921 */
ll_spi_is_enabled_slave_out(ssi_regs_t * SPIx)922 __STATIC_INLINE uint32_t ll_spi_is_enabled_slave_out(ssi_regs_t *SPIx)
923 {
924 return (READ_BITS(SPIx->CTRL0, SSI_CTRL0_SLVOE) != (SSI_CTRL0_SLVOE));
925 }
926
927 /**
928 * @brief Set transfer direction mode
929 *
930 * Register|BitsName
931 * --------|--------
932 * CTRL0 | TMOD
933 *
934 * @param SPIx SPI instance
935 * @param transfer_direction This parameter can be one of the following values:
936 * @arg @ref LL_SSI_FULL_DUPLEX
937 * @arg @ref LL_SSI_SIMPLEX_TX
938 * @arg @ref LL_SSI_SIMPLEX_RX
939 * @arg @ref LL_SSI_READ_EEPROM
940 * @retval None
941 */
ll_spi_set_transfer_direction(ssi_regs_t * SPIx,uint32_t transfer_direction)942 __STATIC_INLINE void ll_spi_set_transfer_direction(ssi_regs_t *SPIx, uint32_t transfer_direction)
943 {
944 MODIFY_REG(SPIx->CTRL0, SSI_CTRL0_TMOD, transfer_direction);
945 }
946
947 /**
948 * @brief Get transfer direction mode
949 *
950 * Register|BitsName
951 * --------|--------
952 * CTRL0 | TMOD
953 *
954 * @param SPIx SPI instance
955 * @retval Returned value can be one of the following values:
956 * @arg @ref LL_SSI_FULL_DUPLEX
957 * @arg @ref LL_SSI_SIMPLEX_TX
958 * @arg @ref LL_SSI_SIMPLEX_RX
959 * @arg @ref LL_SSI_READ_EEPROM
960 */
ll_spi_get_transfer_direction(ssi_regs_t * SPIx)961 __STATIC_INLINE uint32_t ll_spi_get_transfer_direction(ssi_regs_t *SPIx)
962 {
963 return (uint32_t)(READ_BITS(SPIx->CTRL0, SSI_CTRL0_TMOD));
964 }
965
966 /**
967 * @brief Set clock polarity
968 * @note This bit should not be changed when communication is ongoing.
969 * This bit is not used in SPI TI mode.
970 *
971 * Register|BitsName
972 * --------|--------
973 * CTRL0 | SCPOL
974 *
975 * @param SPIx SPI instance
976 * @param clock_polarity This parameter can be one of the following values:
977 * @arg @ref LL_SSI_SCPOL_LOW
978 * @arg @ref LL_SSI_SCPOL_HIGH
979 * @retval None
980 */
ll_spi_set_clock_polarity(ssi_regs_t * SPIx,uint32_t clock_polarity)981 __STATIC_INLINE void ll_spi_set_clock_polarity(ssi_regs_t *SPIx, uint32_t clock_polarity)
982 {
983 MODIFY_REG(SPIx->CTRL0, SSI_CTRL0_SCPOL, clock_polarity);
984 }
985
986 /**
987 * @brief Get clock polarity
988 *
989 * Register|BitsName
990 * --------|--------
991 * CTRL0 | SCPOL
992 *
993 * @param SPIx SPI instance
994 * @retval Returned value can be one of the following values:
995 * @arg @ref LL_SSI_SCPOL_LOW
996 * @arg @ref LL_SSI_SCPOL_HIGH
997 */
ll_spi_get_clock_polarity(ssi_regs_t * SPIx)998 __STATIC_INLINE uint32_t ll_spi_get_clock_polarity(ssi_regs_t *SPIx)
999 {
1000 return (uint32_t)(READ_BITS(SPIx->CTRL0, SSI_CTRL0_SCPOL));
1001 }
1002
1003 /**
1004 * @brief Set clock phase
1005 * @note This bit should not be changed when communication is ongoing.
1006 * This bit is not used in SPI TI mode.
1007 *
1008 * Register|BitsName
1009 * --------|--------
1010 * CTRL0 | SCPHA
1011 *
1012 * @param SPIx SPI instance
1013 * @param clock_phase This parameter can be one of the following values:
1014 * @arg @ref LL_SSI_SCPHA_1EDGE
1015 * @arg @ref LL_SSI_SCPHA_2EDGE
1016 * @retval None
1017 */
ll_spi_set_clock_phase(ssi_regs_t * SPIx,uint32_t clock_phase)1018 __STATIC_INLINE void ll_spi_set_clock_phase(ssi_regs_t *SPIx, uint32_t clock_phase)
1019 {
1020 MODIFY_REG(SPIx->CTRL0, SSI_CTRL0_SCPHA, clock_phase);
1021 }
1022
1023 /**
1024 * @brief Get clock phase
1025 *
1026 * Register|BitsName
1027 * --------|--------
1028 * CTRL0 | SCPHA
1029 *
1030 * @param SPIx SPI instance
1031 * @retval Returned value can be one of the following values:
1032 * @arg @ref LL_SSI_SCPHA_1EDGE
1033 * @arg @ref LL_SSI_SCPHA_2EDGE
1034 */
ll_spi_get_clock_phase(ssi_regs_t * SPIx)1035 __STATIC_INLINE uint32_t ll_spi_get_clock_phase(ssi_regs_t *SPIx)
1036 {
1037 return (uint32_t)(READ_BITS(SPIx->CTRL0, SSI_CTRL0_SCPHA));
1038 }
1039
1040 /**
1041 * @brief Set serial protocol used
1042 * @note This bit should be written only when SPI is disabled (SSI_EN = 0) for correct operation.
1043 *
1044 * Register|BitsName
1045 * --------|--------
1046 * CTRL0 | FRF
1047 *
1048 * @param SPIx SPI instance
1049 * @param standard This parameter can be one of the following values:
1050 * @arg @ref LL_SSI_PROTOCOL_MOTOROLA
1051 * @arg @ref LL_SSI_PROTOCOL_TI
1052 * @arg @ref LL_SSI_PROTOCOL_MICROWIRE
1053 * @retval None
1054 */
ll_spi_set_standard(ssi_regs_t * SPIx,uint32_t standard)1055 __STATIC_INLINE void ll_spi_set_standard(ssi_regs_t *SPIx, uint32_t standard)
1056 {
1057 MODIFY_REG(SPIx->CTRL0, SSI_CTRL0_FRF, standard);
1058 }
1059
1060 /**
1061 * @brief Get serial protocol used
1062 *
1063 * Register|BitsName
1064 * --------|--------
1065 * CTRL0 | FRF
1066 *
1067 * @param SPIx SPI instance
1068 * @retval Returned value can be one of the following values:
1069 * @arg @ref LL_SSI_PROTOCOL_MOTOROLA
1070 * @arg @ref LL_SSI_PROTOCOL_TI
1071 * @arg @ref LL_SSI_PROTOCOL_MICROWIRE
1072 */
ll_spi_get_standard(ssi_regs_t * SPIx)1073 __STATIC_INLINE uint32_t ll_spi_get_standard(ssi_regs_t *SPIx)
1074 {
1075 return (uint32_t)(READ_BITS(SPIx->CTRL0, SSI_CTRL0_FRF));
1076 }
1077
1078 /**
1079 * @brief Set the number of data frames to be continuously received
1080 * @note These bits should not be changed when communication is ongoing.
1081 This bits are effect when TMOD = 2b10 or 2b11.
1082 This bits are not effect in SPIS.
1083 *
1084 * Register|BitsName
1085 * --------|--------
1086 * CTRL1 | NDF
1087 *
1088 * @param SPIx SPI instance
1089 * @param size This parameter can be one of the following values: 0 ~ 65535
1090 * @retval None
1091 */
ll_spi_set_receive_size(ssi_regs_t * SPIx,uint32_t size)1092 __STATIC_INLINE void ll_spi_set_receive_size(ssi_regs_t *SPIx, uint32_t size)
1093 {
1094 MODIFY_REG(SPIx->CTRL1, SSI_CTRL1_NDF, size);
1095 }
1096
1097 /**
1098 * @brief Get the number of data frames to be continuously received
1099 * @note These bits should not be changed when communication is ongoing.
1100 This bits are effect when TMOD = 2b10 or 2b11.
1101 This bits are not effect in SPIS.
1102 *
1103 * Register|BitsName
1104 * --------|--------
1105 * CTRL1 | NDF
1106 *
1107 * @param SPIx SPI instance
1108 * @retval Returned value can be one of the following values: 0 ~ 65535
1109 */
ll_spi_get_receive_size(ssi_regs_t * SPIx)1110 __STATIC_INLINE uint32_t ll_spi_get_receive_size(ssi_regs_t *SPIx)
1111 {
1112 return (uint32_t)(READ_BITS(SPIx->CTRL1, SSI_CTRL1_NDF));
1113 }
1114
1115 /**
1116 * @brief Enable SPI peripheral
1117 *
1118 * Register|BitsName
1119 * --------|--------
1120 * SSI_EN | EN
1121 *
1122 * @param SPIx SPI instance
1123 * @retval None
1124 */
ll_spi_enable(ssi_regs_t * SPIx)1125 __STATIC_INLINE void ll_spi_enable(ssi_regs_t *SPIx)
1126 {
1127 SET_BITS(SPIx->SSI_EN, SSI_SSIEN_EN);
1128 }
1129
1130 /**
1131 * @brief Disable SPI peripheral
1132 * @note When disabling the SPI, follow the procedure described in the Reference Manual.
1133 *
1134 * Register|BitsName
1135 * --------|--------
1136 * SSI_EN | EN
1137 *
1138 * @param SPIx SPI instance
1139 * @retval None
1140 */
ll_spi_disable(ssi_regs_t * SPIx)1141 __STATIC_INLINE void ll_spi_disable(ssi_regs_t *SPIx)
1142 {
1143 CLEAR_BITS(SPIx->SSI_EN, SSI_SSIEN_EN);
1144 }
1145
1146 /**
1147 * @brief Check if SPI peripheral is enabled
1148 *
1149 * Register|BitsName
1150 * --------|--------
1151 * SSI_EN | EN
1152 *
1153 * @param SPIx SPI instance
1154 * @retval State of bit (1 or 0).
1155 */
ll_spi_is_enabled(ssi_regs_t * SPIx)1156 __STATIC_INLINE uint32_t ll_spi_is_enabled(ssi_regs_t *SPIx)
1157 {
1158 return (READ_BITS(SPIx->SSI_EN, SSI_SSIEN_EN) == (SSI_SSIEN_EN));
1159 }
1160
1161 /**
1162 * @brief Enable Handshake in Microwire mode
1163 *
1164 * Register|BitsName
1165 * --------|--------
1166 * MWC | MHS
1167 *
1168 * @param SPIx SPI instance
1169 * @retval None
1170 */
ll_spi_enable_micro_handshake(ssi_regs_t * SPIx)1171 __STATIC_INLINE void ll_spi_enable_micro_handshake(ssi_regs_t *SPIx)
1172 {
1173 SET_BITS(SPIx->MWC, SSI_MWC_MHS);
1174 }
1175
1176 /**
1177 * @brief Disable Handshake in Microwire mode
1178 *
1179 * Register|BitsName
1180 * --------|--------
1181 * MWC | MHS
1182 *
1183 * @param SPIx SPI instance
1184 * @retval None
1185 */
ll_spi_disable_micro_handshake(ssi_regs_t * SPIx)1186 __STATIC_INLINE void ll_spi_disable_micro_handshake(ssi_regs_t *SPIx)
1187 {
1188 CLEAR_BITS(SPIx->MWC, SSI_MWC_MHS);
1189 }
1190
1191 /**
1192 * @brief Check if Handshake in Microwire mode is enabled
1193 *
1194 * Register|BitsName
1195 * --------|--------
1196 * MWC | MHS
1197 *
1198 * @param SPIx SPI instance
1199 * @retval State of bit (1 or 0).
1200 */
ll_spi_is_enabled_micro_handshake(ssi_regs_t * SPIx)1201 __STATIC_INLINE uint32_t ll_spi_is_enabled_micro_handshake(ssi_regs_t *SPIx)
1202 {
1203 return (READ_BITS(SPIx->MWC, SSI_MWC_MHS) == (SSI_MWC_MHS));
1204 }
1205
1206 /**
1207 * @brief Set transfer direction mode in Microwire mode
1208 * @note This bit should not be changed when communication is ongoing.
1209 *
1210 * Register|BitsName
1211 * --------|--------
1212 * MWC | MDD
1213 *
1214 * @param SPIx SPI instance
1215 * @param transfer_direction This parameter can be one of the following values:
1216 * @arg @ref LL_SSI_MICROWIRE_RX
1217 * @arg @ref LL_SSI_MICROWIRE_TX
1218 * @retval None
1219 */
ll_spi_set_micro_transfer_direction(ssi_regs_t * SPIx,uint32_t transfer_direction)1220 __STATIC_INLINE void ll_spi_set_micro_transfer_direction(ssi_regs_t *SPIx, uint32_t transfer_direction)
1221 {
1222 MODIFY_REG(SPIx->MWC, SSI_MWC_MDD, transfer_direction);
1223 }
1224
1225 /**
1226 * @brief Get transfer direction mode in Microwire mode
1227 * @note This bit should not be changed when communication is ongoing.
1228 *
1229 * Register|BitsName
1230 * --------|--------
1231 * MWC | MDD
1232 *
1233 * @param SPIx SPI instance
1234 * @retval Returned value can be one of the following values:
1235 * @arg @ref LL_SSI_MICROWIRE_RX
1236 * @arg @ref LL_SSI_MICROWIRE_TX
1237 */
ll_spi_get_micro_transfer_direction(ssi_regs_t * SPIx)1238 __STATIC_INLINE uint32_t ll_spi_get_micro_transfer_direction(ssi_regs_t *SPIx)
1239 {
1240 return (uint32_t)(READ_BITS(SPIx->MWC, SSI_MWC_MDD));
1241 }
1242
1243 /**
1244 * @brief Set transfer mode in Microwire mode
1245 * @note This bit should not be changed when communication is ongoing.
1246 *
1247 * Register|BitsName
1248 * --------|--------
1249 * MWC | MWMOD
1250 *
1251 * @param SPIx SPI instance
1252 * @param transfer_mode This parameter can be one of the following values:
1253 * @arg @ref LL_SSI_MICROWIRE_NON_SEQUENTIAL
1254 * @arg @ref LL_SSI_MICROWIRE_SEQUENTIAL
1255 * @retval None
1256 */
ll_spi_set_micro_transfer_mode(ssi_regs_t * SPIx,uint32_t transfer_mode)1257 __STATIC_INLINE void ll_spi_set_micro_transfer_mode(ssi_regs_t *SPIx, uint32_t transfer_mode)
1258 {
1259 MODIFY_REG(SPIx->MWC, SSI_MWC_MWMOD, transfer_mode);
1260 }
1261
1262 /**
1263 * @brief Get transfer mode in Microwire mode
1264 * @note This bit should not be changed when communication is ongoing.
1265 *
1266 * Register|BitsName
1267 * --------|--------
1268 * MWC | MWMOD
1269 *
1270 * @param SPIx SPI instance
1271 * @retval Returned value can be one of the following values:
1272 * @arg @ref LL_SSI_MICROWIRE_NON_SEQUENTIAL
1273 * @arg @ref LL_SSI_MICROWIRE_SEQUENTIAL
1274 */
ll_spi_get_micro_transfer_mode(ssi_regs_t * SPIx)1275 __STATIC_INLINE uint32_t ll_spi_get_micro_transfer_mode(ssi_regs_t *SPIx)
1276 {
1277 return (uint32_t)(READ_BITS(SPIx->MWC, SSI_MWC_MWMOD));
1278 }
1279
1280 /**
1281 * @brief Enable slave select
1282 *
1283 * Register|BitsName
1284 * --------|--------
1285 * SE | SLAVE1
1286 * SE | SLAVE0
1287 *
1288 * @param SPIx SPI instance
1289 * @param ss This parameter can be one of the following values:
1290 * @arg @ref LL_SSI_SLAVE1
1291 * @arg @ref LL_SSI_SLAVE0
1292 * @retval None
1293 */
ll_spi_enable_ss(ssi_regs_t * SPIx,uint32_t ss)1294 __STATIC_INLINE void ll_spi_enable_ss(ssi_regs_t *SPIx, uint32_t ss)
1295 {
1296 SET_BITS(SPIx->SE, ss);
1297 }
1298
1299 /**
1300 * @brief Disable slave select
1301 *
1302 * Register|BitsName
1303 * --------|--------
1304 * SE | SLAVE1
1305 * SE | SLAVE0
1306 *
1307 * @param SPIx SPI instance
1308 * @param ss This parameter can be one of the following values:
1309 * @arg @ref LL_SSI_SLAVE1
1310 * @arg @ref LL_SSI_SLAVE0
1311 * @retval None
1312 */
ll_spi_disable_ss(ssi_regs_t * SPIx,uint32_t ss)1313 __STATIC_INLINE void ll_spi_disable_ss(ssi_regs_t *SPIx, uint32_t ss)
1314 {
1315 CLEAR_BITS(SPIx->SE, ss);
1316 }
1317
1318 /**
1319 * @brief Check if slave select is enabled
1320 *
1321 * Register|BitsName
1322 * --------|--------
1323 * SE | SLAVE1
1324 * SE | SLAVE0
1325 *
1326 * @param SPIx SPI instance
1327 * @param ss This parameter can be one of the following values:
1328 * @arg @ref LL_SSI_SLAVE1
1329 * @arg @ref LL_SSI_SLAVE0
1330 * @retval State of bit (1 or 0).
1331 */
ll_spi_is_enabled_ss(ssi_regs_t * SPIx,uint32_t ss)1332 __STATIC_INLINE uint32_t ll_spi_is_enabled_ss(ssi_regs_t *SPIx, uint32_t ss)
1333 {
1334 return (READ_BITS(SPIx->SE, ss) == ss);
1335 }
1336
1337 /**
1338 * @brief Set baud rate prescaler
1339 * @note These bits should not be changed when communication is
1340 * ongoing. SPI BaudRate = fPCLK/Prescaler.
1341 *
1342 * Register|BitsName
1343 * --------|--------
1344 * BAUD | SCKDIV
1345 *
1346 * @param SPIx SPI instance
1347 * @param baud_rate This parameter can be one even value between 2
1348 * and 65534, if the value is 0, the SCLK is disable.
1349 * @retval None
1350 */
ll_spi_set_baud_rate_prescaler(ssi_regs_t * SPIx,uint32_t baud_rate)1351 __STATIC_INLINE void ll_spi_set_baud_rate_prescaler(ssi_regs_t *SPIx, uint32_t baud_rate)
1352 {
1353 WRITE_REG(SPIx->BAUD, baud_rate);
1354 }
1355
1356 /**
1357 * @brief Get baud rate prescaler
1358 *
1359 * Register|BitsName
1360 * --------|--------
1361 * BAUD | SCKDIV
1362 *
1363 * @param SPIx SPI instance
1364 * @retval Returned value can be one even value between 2 and 65534.
1365 */
ll_spi_get_baud_rate_prescaler(ssi_regs_t * SPIx)1366 __STATIC_INLINE uint32_t ll_spi_get_baud_rate_prescaler(ssi_regs_t *SPIx)
1367 {
1368 return (uint32_t)(READ_BITS(SPIx->BAUD, SSI_BAUD_SCKDIV));
1369 }
1370
1371 /**
1372 * @brief Set threshold of TXFIFO that triggers an TXE event
1373 *
1374 * Register|BitsName
1375 * --------|--------
1376 * TXFTL | TFT
1377 *
1378 * @param SPIx SPI instance
1379 * @param threshold This parameter can be one of the following values: 0 ~ 7
1380 * @retval None
1381 */
ll_spi_set_tx_fifo_threshold(ssi_regs_t * SPIx,uint32_t threshold)1382 __STATIC_INLINE void ll_spi_set_tx_fifo_threshold(ssi_regs_t *SPIx, uint32_t threshold)
1383 {
1384 WRITE_REG(SPIx->TX_FTL, threshold);
1385 }
1386
1387 /**
1388 * @brief Get threshold of TXFIFO that triggers an TXE event
1389 *
1390 * Register|BitsName
1391 * --------|--------
1392 * TXFTL | TFT
1393 *
1394 * @param SPIx SPI instance
1395 * @retval Returned value can be one of the following values: 0 ~ 7
1396 */
ll_spi_get_tx_fifo_threshold(ssi_regs_t * SPIx)1397 __STATIC_INLINE uint32_t ll_spi_get_tx_fifo_threshold(ssi_regs_t *SPIx)
1398 {
1399 return (uint32_t)(READ_BITS(SPIx->TX_FTL, SSI_TXFTL_TFT));
1400 }
1401
1402 /**
1403 * @brief Set threshold of RXFIFO that triggers an RXNE event
1404 *
1405 * Register|BitsName
1406 * --------|--------
1407 * RXFTL | RFT
1408 *
1409 * @param SPIx SPI instance
1410 * @param threshold This parameter can be one of the following values: 0 ~ 7
1411 * @retval None
1412 */
ll_spi_set_rx_fifo_threshold(ssi_regs_t * SPIx,uint32_t threshold)1413 __STATIC_INLINE void ll_spi_set_rx_fifo_threshold(ssi_regs_t *SPIx, uint32_t threshold)
1414 {
1415 WRITE_REG(SPIx->RX_FTL, threshold);
1416 }
1417
1418 /**
1419 * @brief Get threshold of RXFIFO that triggers an RXNE event
1420 *
1421 * Register|BitsName
1422 * --------|--------
1423 * RXFTL | RFT
1424 *
1425 * @param SPIx SPI instance
1426 * @retval Returned value can be one of the following values: 0 ~ 7
1427 */
ll_spi_get_rx_fifo_threshold(ssi_regs_t * SPIx)1428 __STATIC_INLINE uint32_t ll_spi_get_rx_fifo_threshold(ssi_regs_t *SPIx)
1429 {
1430 return (uint32_t)(READ_BITS(SPIx->RX_FTL, SSI_RXFTL_RFT));
1431 }
1432
1433 /**
1434 * @brief Get FIFO Transmission Level
1435 *
1436 * Register|BitsName
1437 * --------|--------
1438 * TXFL | TXTFL
1439 *
1440 * @param SPIx SPI instance
1441 * @retval Returned value can be one of the following values: 0 ~ 8
1442 */
ll_spi_get_tx_fifo_level(ssi_regs_t * SPIx)1443 __STATIC_INLINE uint32_t ll_spi_get_tx_fifo_level(ssi_regs_t *SPIx)
1444 {
1445 return (uint32_t)(READ_BITS(SPIx->TX_FL, SSI_TXFL_TXTFL));
1446 }
1447
1448 /**
1449 * @brief Get FIFO reception Level
1450 *
1451 * Register|BitsName
1452 * --------|--------
1453 * RXFL | RXTFL
1454 *
1455 * @param SPIx SPI instance
1456 * @retval Returned value can be one of the following values: 0 ~ 8
1457 */
ll_spi_get_rx_fifo_level(ssi_regs_t * SPIx)1458 __STATIC_INLINE uint32_t ll_spi_get_rx_fifo_level(ssi_regs_t *SPIx)
1459 {
1460 return (uint32_t)(READ_BITS(SPIx->RX_FL, SSI_RXFL_RXTFL));
1461 }
1462
1463 /**
1464 * @brief Get ID code
1465 *
1466 * Register|BitsName
1467 * --------|--------
1468 * IDCODE | ID
1469 *
1470 * @param SPIx SPI instance
1471 * @retval Returned value is const.
1472 */
ll_spi_get_id_code(ssi_regs_t * SPIx)1473 __STATIC_INLINE uint32_t ll_spi_get_id_code(ssi_regs_t *SPIx)
1474 {
1475 return (uint32_t)(READ_BITS(SPIx->ID, SSI_IDCODE_ID));
1476 }
1477
1478 /**
1479 * @brief Get IP version
1480 *
1481 * Register|BitsName
1482 * --------|--------
1483 * COMP | VERSION
1484 *
1485 * @param SPIx SPI instance
1486 * @retval Returned value is const.
1487 */
ll_spi_get_version(ssi_regs_t * SPIx)1488 __STATIC_INLINE uint32_t ll_spi_get_version(ssi_regs_t *SPIx)
1489 {
1490 return (uint32_t)(READ_BITS(SPIx->VERSION_ID, SSI_COMP_VERSION));
1491 }
1492
1493 /** @} */
1494
1495 /** @defgroup SPI_LL_EF_IT_Management IT_Management
1496 * @{
1497 */
1498
1499 /**
1500 * @brief Enable interrupt
1501 * @note This bit controls the generation of an interrupt when an event occurs.
1502 *
1503 * Register|BitsName
1504 * --------|--------
1505 * INTMASK | INTMASK
1506 *
1507 * @param SPIx SPI instance
1508 * @param mask This parameter can be one of the following values:
1509 * @arg @ref LL_SSI_IM_MST(not effect in SPIS)
1510 * @arg @ref LL_SSI_IM_RXF
1511 * @arg @ref LL_SSI_IM_RXO
1512 * @arg @ref LL_SSI_IM_RXU
1513 * @arg @ref LL_SSI_IM_TXO
1514 * @arg @ref LL_SSI_IM_TXE
1515 * @retval None
1516 */
ll_spi_enable_it(ssi_regs_t * SPIx,uint32_t mask)1517 __STATIC_INLINE void ll_spi_enable_it(ssi_regs_t *SPIx, uint32_t mask)
1518 {
1519 SET_BITS(SPIx->INTMASK, mask);
1520 }
1521
1522 /**
1523 * @brief Disable interrupt
1524 * @note This bit controls the generation of an interrupt when an event occurs.
1525 *
1526 * Register|BitsName
1527 * --------|--------
1528 * INTMASK | INTMASK
1529 *
1530 * @param SPIx SPI instance
1531 * @param mask This parameter can be one of the following values:
1532 * @arg @ref LL_SSI_IM_MST(not effect in SPIS)
1533 * @arg @ref LL_SSI_IM_RXF
1534 * @arg @ref LL_SSI_IM_RXO
1535 * @arg @ref LL_SSI_IM_RXU
1536 * @arg @ref LL_SSI_IM_TXO
1537 * @arg @ref LL_SSI_IM_TXE
1538 * @retval None
1539 */
ll_spi_disable_it(ssi_regs_t * SPIx,uint32_t mask)1540 __STATIC_INLINE void ll_spi_disable_it(ssi_regs_t *SPIx, uint32_t mask)
1541 {
1542 CLEAR_BITS(SPIx->INTMASK, mask);
1543 }
1544
1545 /**
1546 * @brief Check if interrupt is enabled
1547 *
1548 * Register|BitsName
1549 * --------|--------
1550 * INTMASK | INTMASK
1551 *
1552 * @param SPIx SPI instance
1553 * @param mask This parameter can be one of the following values:
1554 * @arg @ref LL_SSI_IM_MST(not effect in SPIS)
1555 * @arg @ref LL_SSI_IM_RXF
1556 * @arg @ref LL_SSI_IM_RXO
1557 * @arg @ref LL_SSI_IM_RXU
1558 * @arg @ref LL_SSI_IM_TXO
1559 * @arg @ref LL_SSI_IM_TXE
1560 * @retval State of bit (1 or 0).
1561 */
ll_spi_is_enabled_it(ssi_regs_t * SPIx,uint32_t mask)1562 __STATIC_INLINE uint32_t ll_spi_is_enabled_it(ssi_regs_t *SPIx, uint32_t mask)
1563 {
1564 return (READ_BITS(SPIx->INTMASK, mask) == mask);
1565 }
1566
1567 /** @} */
1568
1569 /** @defgroup SPI_LL_EF_FLAG_Management FLAG_Management
1570 * @{
1571 */
1572
1573 /**
1574 * @brief Get SPI status
1575 *
1576 * Register|BitsName
1577 * --------|--------
1578 * STAT | STAT
1579 *
1580 * @param SPIx SPI instance
1581 * @retval Returned value can be one or combination of the following values:
1582 * @arg @ref LL_SSI_SR_DCOL(no effect in SPIS)
1583 * @arg @ref LL_SSI_SR_TXE
1584 * @arg @ref LL_SSI_SR_RFF
1585 * @arg @ref LL_SSI_SR_RFNE
1586 * @arg @ref LL_SSI_SR_TFE
1587 * @arg @ref LL_SSI_SR_TFNF
1588 * @arg @ref LL_SSI_SR_BUSY
1589 */
ll_spi_get_status(ssi_regs_t * SPIx)1590 __STATIC_INLINE uint32_t ll_spi_get_status(ssi_regs_t *SPIx)
1591 {
1592 return (uint32_t)(READ_REG(SPIx->STAT));
1593 }
1594
1595 /**
1596 * @brief Check active flag
1597 *
1598 * Register|BitsName
1599 * --------|--------
1600 * STAT | DCOL
1601 * STAT | TXE
1602 * STAT | RFF
1603 * STAT | RFNE
1604 * STAT | TFE
1605 * STAT | TFNF
1606 * STAT | BUSY
1607 *
1608 * @param SPIx SPI instance
1609 * @param flag This parameter can be one of the following values:
1610 * @arg @ref LL_SSI_SR_DCOL(no effect in SPIS)
1611 * @arg @ref LL_SSI_SR_TXE
1612 * @arg @ref LL_SSI_SR_RFF
1613 * @arg @ref LL_SSI_SR_RFNE
1614 * @arg @ref LL_SSI_SR_TFE
1615 * @arg @ref LL_SSI_SR_TFNF
1616 * @arg @ref LL_SSI_SR_BUSY
1617 * @retval State of bit (1 or 0).
1618 */
ll_spi_is_active_flag(ssi_regs_t * SPIx,uint32_t flag)1619 __STATIC_INLINE uint32_t ll_spi_is_active_flag(ssi_regs_t *SPIx, uint32_t flag)
1620 {
1621 return (READ_BITS(SPIx->STAT, flag) == (flag));
1622 }
1623
1624 /**
1625 * @brief Get SPI interrupt flags
1626 *
1627 * Register|BitsName
1628 * --------|--------
1629 * INTSTAT | INTSTAT
1630 *
1631 * @param SPIx SPI instance
1632 * @retval Returned value can be one or combination of the following values:
1633 * @arg @ref LL_SSI_IS_MST(no effect in SPIS)
1634 * @arg @ref LL_SSI_IS_RXF
1635 * @arg @ref LL_SSI_IS_RXO
1636 * @arg @ref LL_SSI_IS_RXU
1637 * @arg @ref LL_SSI_IS_TXO
1638 * @arg @ref LL_SSI_IS_TXE
1639 */
ll_spi_get_it_flag(ssi_regs_t * SPIx)1640 __STATIC_INLINE uint32_t ll_spi_get_it_flag(ssi_regs_t *SPIx)
1641 {
1642 return (uint32_t)(READ_REG(SPIx->INTSTAT));
1643 }
1644
1645 /**
1646 * @brief Check interrupt flag
1647 *
1648 * Register|BitsName
1649 * --------|--------
1650 * INTSTAT | MSTIS
1651 * INTSTAT | RXFIS
1652 * INTSTAT | RXOIS
1653 * INTSTAT | RXUIS
1654 * INTSTAT | TXOIS
1655 * INTSTAT | TXEIS
1656 *
1657 * @param SPIx SPI instance
1658 * @param flag This parameter can be one of the following values:
1659 * @arg @ref LL_SSI_IS_MST(no effect in SPIS)
1660 * @arg @ref LL_SSI_IS_RXF
1661 * @arg @ref LL_SSI_IS_RXO
1662 * @arg @ref LL_SSI_IS_RXU
1663 * @arg @ref LL_SSI_IS_TXO
1664 * @arg @ref LL_SSI_IS_TXE
1665 * @retval State of bit (1 or 0).
1666 */
ll_spi_is_it_flag(ssi_regs_t * SPIx,uint32_t flag)1667 __STATIC_INLINE uint32_t ll_spi_is_it_flag(ssi_regs_t *SPIx, uint32_t flag)
1668 {
1669 return (READ_BITS(SPIx->INTSTAT, flag) == flag);
1670 }
1671
1672 /**
1673 * @brief Get SPI raw interrupt flags
1674 *
1675 * Register|BitsName
1676 * --------|--------
1677 * RAW_INTSTAT | RAW_INTSTAT
1678 *
1679 * @param SPIx SPI instance
1680 * @retval Returned value can be one or combination of the following values:
1681 * @arg @ref LL_SSI_RIS_MST(no effect in SPIS)
1682 * @arg @ref LL_SSI_RIS_RXF
1683 * @arg @ref LL_SSI_RIS_RXO
1684 * @arg @ref LL_SSI_RIS_RXU
1685 * @arg @ref LL_SSI_RIS_TXO
1686 * @arg @ref LL_SSI_RIS_TXE
1687 */
ll_spi_get_raw_if_flag(ssi_regs_t * SPIx)1688 __STATIC_INLINE uint32_t ll_spi_get_raw_if_flag(ssi_regs_t *SPIx)
1689 {
1690 return (uint32_t)(READ_REG(SPIx->RAW_INTSTAT));
1691 }
1692
1693 /**
1694 * @brief Clear transmit FIFO overflow error flag
1695 * @note Clearing this flag is done by reading TXOIC register
1696 *
1697 * Register|BitsName
1698 * --------|--------
1699 * TXOIC | TXOIC
1700 *
1701 * @param SPIx SPI instance
1702 * @retval None
1703 */
ll_spi_clear_flag_txo(ssi_regs_t * SPIx)1704 __STATIC_INLINE void ll_spi_clear_flag_txo(ssi_regs_t *SPIx)
1705 {
1706 __IOM uint32_t tmpreg;
1707 tmpreg = SPIx->TXOIC;
1708 (void) tmpreg;
1709 }
1710
1711 /**
1712 * @brief Clear receive FIFO overflow error flag
1713 * @note Clearing this flag is done by reading RXOIC register
1714 *
1715 * Register|BitsName
1716 * --------|--------
1717 * RXOIC | RXOIC
1718 *
1719 * @param SPIx SPI instance
1720 * @retval None
1721 */
ll_spi_clear_flag_rxo(ssi_regs_t * SPIx)1722 __STATIC_INLINE void ll_spi_clear_flag_rxo(ssi_regs_t *SPIx)
1723 {
1724 __IOM uint32_t tmpreg;
1725 tmpreg = SPIx->RXOIC;
1726 (void) tmpreg;
1727 }
1728
1729 /**
1730 * @brief Clear receive FIFO underflow error flag
1731 * @note Clearing this flag is done by reading RXUIC register
1732 *
1733 * Register|BitsName
1734 * --------|--------
1735 * RXUIC | RXUIC
1736 *
1737 * @param SPIx SPI instance
1738 * @retval None
1739 */
ll_spi_clear_flag_rxu(ssi_regs_t * SPIx)1740 __STATIC_INLINE void ll_spi_clear_flag_rxu(ssi_regs_t *SPIx)
1741 {
1742 __IOM uint32_t tmpreg;
1743 tmpreg = SPIx->RXUIC;
1744 (void) tmpreg;
1745 }
1746
1747 /**
1748 * @brief Clear multi-master error flag
1749 * @note Clearing this flag is done by reading MSTIC register
1750 *
1751 * Register|BitsName
1752 * --------|--------
1753 * MSTIC | MSTIC
1754 *
1755 * @param SPIx SPI instance
1756 * @retval None
1757 */
ll_spi_clear_flag_mst(ssi_regs_t * SPIx)1758 __STATIC_INLINE void ll_spi_clear_flag_mst(ssi_regs_t *SPIx)
1759 {
1760 __IOM uint32_t tmpreg;
1761 tmpreg = SPIx->MSTIC;
1762 (void) tmpreg;
1763 }
1764
1765 /**
1766 * @brief Clear all error flag
1767 * @note Clearing this flag is done by reading INTCLR register
1768 *
1769 * Register|BitsName
1770 * --------|--------
1771 * INTCLR | INTCLR
1772 *
1773 * @param SPIx SPI instance
1774 * @retval None
1775 */
ll_spi_clear_flag_all(ssi_regs_t * SPIx)1776 __STATIC_INLINE void ll_spi_clear_flag_all(ssi_regs_t *SPIx)
1777 {
1778 __IOM uint32_t tmpreg;
1779 tmpreg = SPIx->INTCLR;
1780 (void) tmpreg;
1781 }
1782
1783 /** @} */
1784
1785 /** @defgroup SPI_LL_EF_DMA_Management DMA_Management
1786 * @{
1787 */
1788
1789 /**
1790 * @brief Enable DMA Tx
1791 *
1792 * Register|BitsName
1793 * --------|--------
1794 * DMAC | TDMAE
1795 *
1796 * @param SPIx SPI instance
1797 * @retval None
1798 */
ll_spi_enable_dma_req_tx(ssi_regs_t * SPIx)1799 __STATIC_INLINE void ll_spi_enable_dma_req_tx(ssi_regs_t *SPIx)
1800 {
1801 SET_BITS(SPIx->DMAC, SSI_DMAC_TDMAE);
1802 }
1803
1804 /**
1805 * @brief Disable DMA Tx
1806 *
1807 * Register|BitsName
1808 * --------|--------
1809 * DMAC | TDMAE
1810 *
1811 * @param SPIx SPI instance
1812 * @retval None
1813 */
ll_spi_disable_dma_req_tx(ssi_regs_t * SPIx)1814 __STATIC_INLINE void ll_spi_disable_dma_req_tx(ssi_regs_t *SPIx)
1815 {
1816 CLEAR_BITS(SPIx->DMAC, SSI_DMAC_TDMAE);
1817 }
1818
1819 /**
1820 * @brief Check if DMA Tx is enabled
1821 *
1822 * Register|BitsName
1823 * --------|--------
1824 * DMAC | TDMAE
1825 *
1826 * @param SPIx SPI instance
1827 * @retval State of bit (1 or 0).
1828 */
ll_spi_is_enabled_dma_req_tx(ssi_regs_t * SPIx)1829 __STATIC_INLINE uint32_t ll_spi_is_enabled_dma_req_tx(ssi_regs_t *SPIx)
1830 {
1831 return (READ_BITS(SPIx->DMAC, SSI_DMAC_TDMAE) == (SSI_DMAC_TDMAE));
1832 }
1833
1834 /**
1835 * @brief Enable DMA Rx
1836 *
1837 * Register|BitsName
1838 * --------|--------
1839 * DMAC | RDMAE
1840 *
1841 * @param SPIx SPI instance
1842 * @retval None
1843 */
ll_spi_enable_dma_req_rx(ssi_regs_t * SPIx)1844 __STATIC_INLINE void ll_spi_enable_dma_req_rx(ssi_regs_t *SPIx)
1845 {
1846 SET_BITS(SPIx->DMAC, SSI_DMAC_RDMAE);
1847 }
1848
1849 /**
1850 * @brief Disable DMA Rx
1851 *
1852 * Register|BitsName
1853 * --------|--------
1854 * DMAC | RDMAE
1855 *
1856 * @param SPIx SPI instance
1857 * @retval None
1858 */
ll_spi_disable_dma_req_rx(ssi_regs_t * SPIx)1859 __STATIC_INLINE void ll_spi_disable_dma_req_rx(ssi_regs_t *SPIx)
1860 {
1861 CLEAR_BITS(SPIx->DMAC, SSI_DMAC_RDMAE);
1862 }
1863
1864 /**
1865 * @brief Check if DMA Rx is enabled
1866 *
1867 * Register|BitsName
1868 * --------|--------
1869 * DMAC | RDMAE
1870 *
1871 * @param SPIx SPI instance
1872 * @retval State of bit (1 or 0).
1873 */
ll_spi_is_enabled_dma_req_rx(ssi_regs_t * SPIx)1874 __STATIC_INLINE uint32_t ll_spi_is_enabled_dma_req_rx(ssi_regs_t *SPIx)
1875 {
1876 return (READ_BITS(SPIx->DMAC, SSI_DMAC_RDMAE) == (SSI_DMAC_RDMAE));
1877 }
1878
1879 /**
1880 * @brief Set threshold of TXFIFO that triggers an DMA Tx request event
1881 *
1882 * Register|BitsName
1883 * --------|--------
1884 * DMATDL | DMATDL
1885 *
1886 * @param SPIx SPI instance
1887 * @param threshold This parameter can be one of the following values: 0 ~ 7
1888 * @retval None
1889 */
ll_spi_set_dma_tx_fifo_threshold(ssi_regs_t * SPIx,uint32_t threshold)1890 __STATIC_INLINE void ll_spi_set_dma_tx_fifo_threshold(ssi_regs_t *SPIx, uint32_t threshold)
1891 {
1892 WRITE_REG(SPIx->DMA_TDL, threshold);
1893 }
1894
1895 /**
1896 * @brief Get threshold of TXFIFO that triggers an DMA Tx request event
1897 *
1898 * Register|BitsName
1899 * --------|--------
1900 * DMATDL | DMATDL
1901 *
1902 * @param SPIx SPI instance
1903 * @retval Returned value can be one of the following values: 0 ~ 7
1904 */
ll_spi_get_dma_tx_fifo_threshold(ssi_regs_t * SPIx)1905 __STATIC_INLINE uint32_t ll_spi_get_dma_tx_fifo_threshold(ssi_regs_t *SPIx)
1906 {
1907 return (uint32_t)(READ_BITS(SPIx->DMA_TDL, SSI_DMATDL_DMATDL));
1908 }
1909
1910 /**
1911 * @brief Set threshold of RXFIFO that triggers an DMA Rx request event
1912 *
1913 * Register|BitsName
1914 * --------|--------
1915 * DMARDL | DMARDL
1916 *
1917 * @param SPIx SPI instance
1918 * @param threshold This parameter can be one of the following values: 0 ~ 7
1919 * @retval None
1920 */
ll_spi_set_dma_rx_fifo_threshold(ssi_regs_t * SPIx,uint32_t threshold)1921 __STATIC_INLINE void ll_spi_set_dma_rx_fifo_threshold(ssi_regs_t *SPIx, uint32_t threshold)
1922 {
1923 WRITE_REG(SPIx->DMA_RDL, threshold);
1924 }
1925
1926 /**
1927 * @brief Get threshold of RXFIFO that triggers an DMA Rx request event
1928 *
1929 * Register|BitsName
1930 * --------|--------
1931 * DMARDL | DMARDL
1932 *
1933 * @param SPIx SPI instance
1934 * @retval Returned value can be one of the following values: 0 ~ 7
1935 */
ll_spi_get_dma_rx_fifo_threshold(ssi_regs_t * SPIx)1936 __STATIC_INLINE uint32_t ll_spi_get_dma_rx_fifo_threshold(ssi_regs_t *SPIx)
1937 {
1938 return (uint32_t)(READ_BITS(SPIx->DMA_RDL, SSI_DMARDL_DMARDL));
1939 }
1940
1941 /** @} */
1942
1943 /** @defgroup SPI_LL_EF_Data_Management Data_Management
1944 * @{
1945 */
1946
1947 /**
1948 * @brief Write 8-Bits in the data register
1949 *
1950 * Register|BitsName
1951 * --------|--------
1952 * DATA | DATA
1953 *
1954 * @param SPIx SPI instance
1955 * @param tx_data Value between Min_Data=0x00 and Max_Data=0xFF
1956 * @retval None
1957 */
ll_spi_transmit_data8(ssi_regs_t * SPIx,uint8_t tx_data)1958 __STATIC_INLINE void ll_spi_transmit_data8(ssi_regs_t *SPIx, uint8_t tx_data)
1959 {
1960 *((__IOM uint8_t *)&SPIx->DATA) = tx_data;
1961 }
1962
1963 /**
1964 * @brief Write 16-Bits in the data register
1965 *
1966 * Register|BitsName
1967 * --------|--------
1968 * DATA | DATA
1969 *
1970 * @param SPIx SPI instance
1971 * @param tx_data Value between Min_Data=0x0000 and Max_Data=0xFFFF
1972 * @retval None
1973 */
ll_spi_transmit_data16(ssi_regs_t * SPIx,uint16_t tx_data)1974 __STATIC_INLINE void ll_spi_transmit_data16(ssi_regs_t *SPIx, uint16_t tx_data)
1975 {
1976 *((__IOM uint16_t *)&SPIx->DATA) = tx_data;
1977 }
1978
1979 /**
1980 * @brief Write 32-Bits in the data register
1981 *
1982 * Register|BitsName
1983 * --------|--------
1984 * DATA | DATA
1985 *
1986 * @param SPIx SPI instance
1987 * @param tx_data Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
1988 * @retval None
1989 */
ll_spi_transmit_data32(ssi_regs_t * SPIx,uint32_t tx_data)1990 __STATIC_INLINE void ll_spi_transmit_data32(ssi_regs_t *SPIx, uint32_t tx_data)
1991 {
1992 *((__IOM uint32_t *)&SPIx->DATA) = tx_data;
1993 }
1994
1995 /**
1996 * @brief Read 8-Bits in the data register
1997 *
1998 * Register|BitsName
1999 * --------|--------
2000 * DATA | DATA
2001 *
2002 * @param SPIx SPI instance
2003 * @retval Rerturned Value between Min_Data=0x00 and Max_Data=0xFF
2004 */
ll_spi_receive_data8(ssi_regs_t * SPIx)2005 __STATIC_INLINE uint8_t ll_spi_receive_data8(ssi_regs_t *SPIx)
2006 {
2007 return (uint8_t)(READ_REG(SPIx->DATA));
2008 }
2009
2010 /**
2011 * @brief Read 16-Bits in the data register
2012 *
2013 * Register|BitsName
2014 * --------|--------
2015 * DATA | DATA
2016 *
2017 * @param SPIx SPI instance
2018 * @retval Returned Value between Min_Data=0x0000 and Max_Data=0xFFFF
2019 */
ll_spi_receive_data16(ssi_regs_t * SPIx)2020 __STATIC_INLINE uint16_t ll_spi_receive_data16(ssi_regs_t *SPIx)
2021 {
2022 return (uint16_t)(READ_REG(SPIx->DATA));
2023 }
2024
2025 /**
2026 * @brief Read 32-Bits in the data register
2027 *
2028 * Register|BitsName
2029 * --------|--------
2030 * DATA | DATA
2031 *
2032 * @param SPIx SPI instance
2033 * @retval Returned Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
2034 */
ll_spi_receive_data32(ssi_regs_t * SPIx)2035 __STATIC_INLINE uint32_t ll_spi_receive_data32(ssi_regs_t *SPIx)
2036 {
2037 return (uint32_t)(READ_REG(SPIx->DATA));
2038 }
2039
2040 /**
2041 * @brief Set Rx sample delay
2042 * @note This bit should not be changed when communication is ongoing.
2043 *
2044 * Register|BitsName
2045 * --------|--------
2046 * RX_SAMPLEDLY | RX_SAMPLEDLY
2047 *
2048 * @param SPIx SPI instance
2049 * @param delay This parameter can be one of the following values: 0 ~ 256
2050 * @retval None
2051 */
ll_spi_set_rx_sample_delay(ssi_regs_t * SPIx,uint32_t delay)2052 __STATIC_INLINE void ll_spi_set_rx_sample_delay(ssi_regs_t *SPIx, uint32_t delay)
2053 {
2054 WRITE_REG(SPIx->RX_SAMPLE_DLY, delay);
2055 }
2056
2057 /**
2058 * @brief Get Rx sample delay
2059 * @note This bit should not be changed when communication is ongoing.
2060 *
2061 * Register|BitsName
2062 * --------|--------
2063 * RX_SAMPLEDLY | RX_SAMPLEDLY
2064 *
2065 * @param SPIx SPI instance
2066 * @retval Returned value can be one of the following values: 0 ~ 256
2067 */
ll_spi_get_rx_sample_delay(ssi_regs_t * SPIx)2068 __STATIC_INLINE uint32_t ll_spi_get_rx_sample_delay(ssi_regs_t *SPIx)
2069 {
2070 return (uint32_t)(READ_REG(SPIx->RX_SAMPLE_DLY));
2071 }
2072
2073 /**
2074 * @brief Set number of wait cycles in Dual/Quad SPI mode
2075 * @note This bit should not be changed when communication is ongoing.
2076 *
2077 * Register|BitsName
2078 * --------|--------
2079 * SCTRL0 | WAITCYCLES
2080 *
2081 * @param SPIx SPI instance
2082 * @param wait_cycles This parameter can be one of the following values: 0 ~ 31
2083 * @retval None
2084 */
ll_spi_set_wait_cycles(ssi_regs_t * SPIx,uint32_t wait_cycles)2085 __STATIC_INLINE void ll_spi_set_wait_cycles(ssi_regs_t *SPIx, uint32_t wait_cycles)
2086 {
2087 MODIFY_REG(SPIx->SPI_CTRL0, SSI_SCTRL0_WAITCYCLES, wait_cycles << SSI_SCTRL0_WAITCYCLES_Pos);
2088 }
2089
2090 /**
2091 * @brief Get number of wait cycles in Dual/Quad SPI mode
2092 * @note This bit should not be changed when communication is ongoing.
2093 *
2094 * Register|BitsName
2095 * --------|--------
2096 * SCTRL0 | WAITCYCLES
2097 *
2098 * @param SPIx SPI instance
2099 * @retval Returned value can be one of the following values: 0 ~ 31
2100 */
ll_spi_get_wait_cycles(ssi_regs_t * SPIx)2101 __STATIC_INLINE uint32_t ll_spi_get_wait_cycles(ssi_regs_t *SPIx)
2102 {
2103 return (uint32_t)(READ_BITS(SPIx->SPI_CTRL0, SSI_SCTRL0_WAITCYCLES) >> SSI_SCTRL0_WAITCYCLES_Pos);
2104 }
2105
2106 /**
2107 * @brief Set Dual/Quad SPI mode instruction length in bits
2108 * @note This bit should not be changed when communication is ongoing.
2109 *
2110 * Register|BitsName
2111 * --------|--------
2112 * SCTRL0 | INSTL
2113 *
2114 * @param SPIx SPI instance
2115 * @param size This parameter can be one of the following values:
2116 * @arg @ref LL_SSI_INSTSIZE_0BIT
2117 * @arg @ref LL_SSI_INSTSIZE_4BIT
2118 * @arg @ref LL_SSI_INSTSIZE_8BIT
2119 * @arg @ref LL_SSI_INSTSIZE_16BIT
2120 * @retval None
2121 */
ll_spi_set_instruction_size(ssi_regs_t * SPIx,uint32_t size)2122 __STATIC_INLINE void ll_spi_set_instruction_size(ssi_regs_t *SPIx, uint32_t size)
2123 {
2124 MODIFY_REG(SPIx->SPI_CTRL0, SSI_SCTRL0_INSTL, size);
2125 }
2126
2127 /**
2128 * @brief Get Dual/Quad SPI mode instruction length in bits
2129 * @note This bit should not be changed when communication is ongoing.
2130 *
2131 * Register|BitsName
2132 * --------|--------
2133 * SCTRL0 | INSTL
2134 *
2135 * @param SPIx SPI instance
2136 * @retval Returned value can be one of the following values:
2137 * @arg @ref LL_SSI_INSTSIZE_0BIT
2138 * @arg @ref LL_SSI_INSTSIZE_4BIT
2139 * @arg @ref LL_SSI_INSTSIZE_8BIT
2140 * @arg @ref LL_SSI_INSTSIZE_16BIT
2141 */
ll_spi_get_instruction_size(ssi_regs_t * SPIx)2142 __STATIC_INLINE uint32_t ll_spi_get_instruction_size(ssi_regs_t *SPIx)
2143 {
2144 return (uint32_t)(READ_BITS(SPIx->SPI_CTRL0, SSI_SCTRL0_INSTL));
2145 }
2146
2147 /**
2148 * @brief Set Dual/Quad SPI mode address length in bits
2149 * @note This bit should not be changed when communication is ongoing.
2150 *
2151 * Register|BitsName
2152 * --------|--------
2153 * SCTRL0 | ADDRL
2154 *
2155 * @param SPIx SPI instance
2156 * @param size This parameter can be one of the following values:
2157 * @arg @ref LL_SSI_ADDRSIZE_0BIT
2158 * @arg @ref LL_SSI_ADDRSIZE_4BIT
2159 * @arg @ref LL_SSI_ADDRSIZE_8BIT
2160 * @arg @ref LL_SSI_ADDRSIZE_12BIT
2161 * @arg @ref LL_SSI_ADDRSIZE_16BIT
2162 * @arg @ref LL_SSI_ADDRSIZE_20BIT
2163 * @arg @ref LL_SSI_ADDRSIZE_24BIT
2164 * @arg @ref LL_SSI_ADDRSIZE_28BIT
2165 * @arg @ref LL_SSI_ADDRSIZE_32BIT
2166 * @arg @ref LL_SSI_ADDRSIZE_36BIT
2167 * @arg @ref LL_SSI_ADDRSIZE_40BIT
2168 * @arg @ref LL_SSI_ADDRSIZE_44BIT
2169 * @arg @ref LL_SSI_ADDRSIZE_48BIT
2170 * @arg @ref LL_SSI_ADDRSIZE_52BIT
2171 * @arg @ref LL_SSI_ADDRSIZE_56BIT
2172 * @arg @ref LL_SSI_ADDRSIZE_60BIT
2173 * @retval None
2174 */
ll_spi_set_address_size(ssi_regs_t * SPIx,uint32_t size)2175 __STATIC_INLINE void ll_spi_set_address_size(ssi_regs_t *SPIx, uint32_t size)
2176 {
2177 MODIFY_REG(SPIx->SPI_CTRL0, SSI_SCTRL0_ADDRL, size);
2178 }
2179
2180 /**
2181 * @brief Get Dual/Quad SPI mode address length in bits
2182 * @note This bit should not be changed when communication is ongoing.
2183 *
2184 * Register|BitsName
2185 * --------|--------
2186 * SCTRL0 | ADDRL
2187 *
2188 * @param SPIx SPI instance
2189 * @retval Returned value can be one of the following values:
2190 * @arg @ref LL_SSI_ADDRSIZE_0BIT
2191 * @arg @ref LL_SSI_ADDRSIZE_4BIT
2192 * @arg @ref LL_SSI_ADDRSIZE_8BIT
2193 * @arg @ref LL_SSI_ADDRSIZE_12BIT
2194 * @arg @ref LL_SSI_ADDRSIZE_16BIT
2195 * @arg @ref LL_SSI_ADDRSIZE_20BIT
2196 * @arg @ref LL_SSI_ADDRSIZE_24BIT
2197 * @arg @ref LL_SSI_ADDRSIZE_28BIT
2198 * @arg @ref LL_SSI_ADDRSIZE_32BIT
2199 * @arg @ref LL_SSI_ADDRSIZE_36BIT
2200 * @arg @ref LL_SSI_ADDRSIZE_40BIT
2201 * @arg @ref LL_SSI_ADDRSIZE_44BIT
2202 * @arg @ref LL_SSI_ADDRSIZE_48BIT
2203 * @arg @ref LL_SSI_ADDRSIZE_52BIT
2204 * @arg @ref LL_SSI_ADDRSIZE_56BIT
2205 * @arg @ref LL_SSI_ADDRSIZE_60BIT
2206 */
ll_spi_get_address_size(ssi_regs_t * SPIx)2207 __STATIC_INLINE uint32_t ll_spi_get_address_size(ssi_regs_t *SPIx)
2208 {
2209 return (uint32_t)(READ_BITS(SPIx->SPI_CTRL0, SSI_SCTRL0_ADDRL));
2210 }
2211
2212 /**
2213 * @brief Set Dual/Quad SPI mode address and instruction transfer format
2214 * @note This bit should not be changed when communication is ongoing.
2215 *
2216 * Register|BitsName
2217 * --------|--------
2218 * SCTRL0 | TRANSTYPE
2219 *
2220 * @param SPIx SPI instance
2221 * @param format This parameter can be one of the following values:
2222 * @arg @ref LL_SSI_INST_ADDR_ALL_IN_SPI
2223 * @arg @ref LL_SSI_INST_IN_SPI_ADDR_IN_SPIFRF
2224 * @arg @ref LL_SSI_INST_ADDR_ALL_IN_SPIFRF
2225 * @retval None
2226 */
ll_spi_set_add_inst_transfer_format(ssi_regs_t * SPIx,uint32_t format)2227 __STATIC_INLINE void ll_spi_set_add_inst_transfer_format(ssi_regs_t *SPIx, uint32_t format)
2228 {
2229 MODIFY_REG(SPIx->SPI_CTRL0, SSI_SCTRL0_TRANSTYPE, format);
2230 }
2231
2232 /**
2233 * @brief Get Dual/Quad SPI mode address and instruction transfer format
2234 * @note This bit should not be changed when communication is ongoing.
2235 *
2236 * Register|BitsName
2237 * --------|--------
2238 * SCTRL0 | TRANSTYPE
2239 *
2240 * @param SPIx SPI instance
2241 * @retval Returned value can be one of the following values:
2242 * @arg @ref LL_SSI_INST_ADDR_ALL_IN_SPI
2243 * @arg @ref LL_SSI_INST_IN_SPI_ADDR_IN_SPIFRF
2244 * @arg @ref LL_SSI_INST_ADDR_ALL_IN_SPIFRF
2245 */
ll_spi_get_addr_inst_transfer_format(ssi_regs_t * SPIx)2246 __STATIC_INLINE uint32_t ll_spi_get_addr_inst_transfer_format(ssi_regs_t *SPIx)
2247 {
2248 return (uint32_t)(READ_BITS(SPIx->SPI_CTRL0, SSI_SCTRL0_TRANSTYPE));
2249 }
2250
2251 /** @} */
2252
2253 /** @defgroup SPI_LL_EF_Init SPIM Initialization and de-initialization functions
2254 * @{
2255 */
2256
2257 /**
2258 * @brief De-initialize SSI registers (Registers restored to their default values).
2259 * @param SPIx SSI instance
2260 * @retval An error_status_t enumeration value:
2261 * - SUCCESS: SSI registers are de-initialized
2262 * - ERROR: SSI registers are not de-initialized
2263 */
2264 error_status_t ll_spim_deinit(ssi_regs_t *SPIx);
2265
2266 /**
2267 * @brief Initialize SPIM registers according to the specified
2268 * parameters in p_spi_init.
2269 * @param SPIx SSI instance
2270 * @param p_spi_init Pointer to a ll_spim_init_t structure that contains the configuration
2271 * information for the specified SPIM peripheral.
2272 * @retval An error_status_t enumeration value:
2273 * - SUCCESS: SSI registers are initialized according to p_spi_init content
2274 * - ERROR: Problem occurred during SSI Registers initialization
2275 */
2276 error_status_t ll_spim_init(ssi_regs_t *SPIx, ll_spim_init_t *p_spi_init);
2277
2278 /**
2279 * @brief Set each field of a @ref ll_spim_init_t type structure to default value.
2280 * @param p_spi_init Pointer to a @ref ll_spim_init_t structure
2281 * whose fields will be set to default values.
2282 * @retval None
2283 */
2284 void ll_spim_struct_init(ll_spim_init_t *p_spi_init);
2285
2286 /** @} */
2287
2288 /** @defgroup SPIS_LL_Init SPIS Initialization and de-initialization functions
2289 * @{
2290 */
2291
2292 /**
2293 * @brief De-initialize SSI registers (Registers restored to their default values).
2294 * @param SPIx SSI instance
2295 * @retval An error_status_t enumeration value:
2296 * - SUCCESS: SSI registers are de-initialized
2297 * - ERROR: SSI registers are not de-initialized
2298 */
2299 error_status_t ll_spis_deinit(ssi_regs_t *SPIx);
2300
2301 /**
2302 * @brief Initialize SSI registers according to the specified
2303 * parameters in p_spi_init.
2304 * @param SPIx SSI instance
2305 * @param p_spi_init Pointer to a ll_spis_init_t structure that contains the configuration
2306 * information for the specified SPIS peripheral.
2307 * @retval An error_status_t enumeration value:
2308 * - SUCCESS: SSI registers are initialized according to p_spi_init content
2309 * - ERROR: Problem occurred during SPI Registers initialization
2310 */
2311 error_status_t ll_spis_init(ssi_regs_t *SPIx, ll_spis_init_t *p_spi_init);
2312
2313 /**
2314 * @brief Set each field of a @ref ll_spis_init_t type structure to default value.
2315 * @param p_spi_init Pointer to a @ref ll_spis_init_t structure
2316 * whose fields will be set to default values.
2317 * @retval None
2318 */
2319 void ll_spis_struct_init(ll_spis_init_t *p_spi_init);
2320 /** @} */
2321
2322 /** @defgroup QSPI_LL_Init QSPI Initialization and de-initialization functions
2323 * @{
2324 */
2325
2326 /**
2327 * @brief De-initialize SSI registers (Registers restored to their default values).
2328 * @param SPIx SSI instance
2329 * @retval An error_status_t enumeration value:
2330 * - SUCCESS: SSI registers are de-initialized
2331 * - ERROR: SSI registers are not de-initialized
2332 */
2333 error_status_t ll_qspi_deinit(ssi_regs_t *SPIx);
2334
2335 /**
2336 * @brief Initialize SSI registers according to the specified
2337 * parameters in SPI_InitStruct.
2338 * @param SPIx SSI instance
2339 * @param p_spi_init Pointer to a ll_qspi_init_t structure that contains the configuration
2340 * information for the specified QSPI peripheral.
2341 * @retval An error_status_t enumeration value:
2342 * - SUCCESS: SPI registers are initialized according to p_spi_init content
2343 * - ERROR: Problem occurred during SPI Registers initialization
2344 */
2345 error_status_t ll_qspi_init(ssi_regs_t *SPIx, ll_qspi_init_t *p_spi_init);
2346
2347 /**
2348 * @brief Set each field of a @ref ll_qspi_init_t type structure to default value.
2349 * @param p_spi_init Pointer to a @ref ll_qspi_init_t structure
2350 * whose fields will be set to default values.
2351 * @retval None
2352 */
2353 void ll_qspi_struct_init(ll_qspi_init_t *p_spi_init);
2354
2355 /** @} */
2356
2357 /** @} */
2358
2359 #endif /* SPIM || SPIS || QSPI0 || QSPI1 */
2360
2361 #ifdef __cplusplus
2362 }
2363 #endif
2364
2365 #endif /* __GR55xx_LL_SPI_H__ */
2366
2367 /** @} */
2368
2369 /** @} */
2370
2371 /** @} */
2372