1 /* 2 * Copyright (c) 2021 Bestechnic (Shanghai) Co., Ltd. All rights reserved. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 #ifndef __HAL_CMU_H__ 16 #define __HAL_CMU_H__ 17 18 #ifdef __cplusplus 19 extern "C" { 20 #endif 21 22 #include "stdint.h" 23 #include "plat_addr_map.h" 24 #ifdef CHIP_SUBSYS_SENS 25 #include CHIP_SPECIFIC_HDR(hal_senscmu) 26 #elif defined(CHIP_SUBSYS_BTH) 27 #include CHIP_SPECIFIC_HDR(hal_bthcmu) 28 #else 29 #include CHIP_SPECIFIC_HDR(hal_cmu) 30 #endif 31 32 #ifndef HAL_CMU_DEFAULT_CRYSTAL_FREQ 33 #define HAL_CMU_DEFAULT_CRYSTAL_FREQ 26000000 34 #endif 35 36 #define LPU_TIMER_US(us) (((us) * 32 + 1000 - 1) / 1000) 37 38 enum HAL_CMU_CLK_STATUS_T { 39 HAL_CMU_CLK_DISABLED, 40 HAL_CMU_CLK_ENABLED, 41 }; 42 43 enum HAL_CMU_CLK_MODE_T { 44 HAL_CMU_CLK_AUTO, 45 HAL_CMU_CLK_MANUAL, 46 }; 47 48 enum HAL_CMU_RST_STATUS_T { 49 HAL_CMU_RST_SET, 50 HAL_CMU_RST_CLR, 51 }; 52 53 enum HAL_CMU_TIMER_ID_T { 54 HAL_CMU_TIMER_ID_00, 55 HAL_CMU_TIMER_ID_01, 56 HAL_CMU_TIMER_ID_10, 57 HAL_CMU_TIMER_ID_11, 58 HAL_CMU_TIMER_ID_20, 59 HAL_CMU_TIMER_ID_21, 60 }; 61 62 #ifndef HAL_CMU_FREQ_T 63 enum HAL_CMU_FREQ_T { 64 HAL_CMU_FREQ_32K, 65 HAL_CMU_FREQ_26M, 66 HAL_CMU_FREQ_52M, 67 HAL_CMU_FREQ_78M, 68 HAL_CMU_FREQ_104M, 69 HAL_CMU_FREQ_208M, 70 71 HAL_CMU_FREQ_QTY 72 }; 73 #endif 74 75 #ifndef HAL_CMU_PLL_T 76 enum HAL_CMU_PLL_T { 77 HAL_CMU_PLL_AUD, 78 HAL_CMU_PLL_USB, 79 80 HAL_CMU_PLL_QTY 81 }; 82 #endif 83 84 #ifndef HAL_CMU_PLL_USER_T 85 enum HAL_CMU_PLL_USER_T { 86 HAL_CMU_PLL_USER_SYS, 87 HAL_CMU_PLL_USER_AUD, 88 HAL_CMU_PLL_USER_USB, 89 90 HAL_CMU_PLL_USER_QTY, 91 HAL_CMU_PLL_USER_ALL = HAL_CMU_PLL_USER_QTY, 92 }; 93 #endif 94 95 enum HAL_CMU_PERIPH_FREQ_T { 96 HAL_CMU_PERIPH_FREQ_26M, 97 HAL_CMU_PERIPH_FREQ_52M, 98 99 HAL_CMU_PERIPH_FREQ_QTY 100 }; 101 102 enum HAL_CMU_LPU_CLK_CFG_T { 103 HAL_CMU_LPU_CLK_NONE, 104 HAL_CMU_LPU_CLK_26M, 105 HAL_CMU_LPU_CLK_PLL, 106 107 HAL_CMU_LPU_CLK_QTY 108 }; 109 110 enum HAL_CMU_LPU_SLEEP_MODE_T { 111 HAL_CMU_LPU_SLEEP_MODE_SYS, 112 HAL_CMU_LPU_SLEEP_MODE_CHIP, 113 HAL_CMU_LPU_SLEEP_MODE_POWER_DOWN, 114 115 HAL_CMU_LPU_SLEEP_MODE_QTY 116 }; 117 118 #ifndef HAL_PWM_ID_T 119 enum HAL_PWM_ID_T { 120 HAL_PWM_ID_0, 121 HAL_PWM_ID_1, 122 HAL_PWM_ID_2, 123 HAL_PWM_ID_3, 124 125 HAL_PWM_ID_QTY 126 }; 127 #endif 128 129 #ifndef HAL_I2S_ID_T 130 enum HAL_I2S_ID_T { 131 HAL_I2S_ID_0 = 0, 132 133 HAL_I2S_ID_QTY, 134 }; 135 #endif 136 137 #ifndef HAL_SPDIF_ID_T 138 enum HAL_SPDIF_ID_T { 139 HAL_SPDIF_ID_0 = 0, 140 141 HAL_SPDIF_ID_QTY, 142 }; 143 #endif 144 145 enum HAL_CMU_USB_CLOCK_SEL_T { 146 HAL_CMU_USB_CLOCK_SEL_PLL, 147 HAL_CMU_USB_CLOCK_SEL_24M_X2, 148 HAL_CMU_USB_CLOCK_SEL_48M, 149 HAL_CMU_USB_CLOCK_SEL_26M_X2, 150 HAL_CMU_USB_CLOCK_SEL_26M_X4, 151 }; 152 153 enum HAL_FLASH_ID_T { 154 HAL_FLASH_ID_0 = 0, 155 #ifdef FLASH1_CTRL_BASE 156 HAL_FLASH_ID_1 = 1, 157 #endif 158 HAL_FLASH_ID_NUM, 159 }; 160 161 void hal_cmu_set_crystal_freq_index(uint32_t index); 162 163 uint32_t hal_cmu_get_crystal_freq(void); 164 165 uint32_t hal_cmu_get_default_crystal_freq(void); 166 167 uint32_t hal_cmu_get_fast_timer_freq(void); 168 169 int hal_cmu_clock_enable(enum HAL_CMU_MOD_ID_T id); 170 171 int hal_cmu_clock_disable(enum HAL_CMU_MOD_ID_T id); 172 173 enum HAL_CMU_CLK_STATUS_T hal_cmu_clock_get_status(enum HAL_CMU_MOD_ID_T id); 174 175 int hal_cmu_clock_set_mode(enum HAL_CMU_MOD_ID_T id, enum HAL_CMU_CLK_MODE_T mode); 176 177 enum HAL_CMU_CLK_MODE_T hal_cmu_clock_get_mode(enum HAL_CMU_MOD_ID_T id); 178 179 int hal_cmu_reset_set(enum HAL_CMU_MOD_ID_T id); 180 181 int hal_cmu_reset_clear(enum HAL_CMU_MOD_ID_T id); 182 183 enum HAL_CMU_RST_STATUS_T hal_cmu_reset_get_status(enum HAL_CMU_MOD_ID_T id); 184 185 int hal_cmu_reset_pulse(enum HAL_CMU_MOD_ID_T id); 186 187 int hal_cmu_timer_set_div(enum HAL_CMU_TIMER_ID_T id, uint32_t div); 188 189 void hal_cmu_timer0_select_fast(void); 190 191 void hal_cmu_timer0_select_slow(void); 192 193 void hal_cmu_timer1_select_fast(void); 194 195 void hal_cmu_timer1_select_slow(void); 196 197 void hal_cmu_timer2_select_fast(void); 198 199 void hal_cmu_timer2_select_slow(void); 200 201 void hal_cmu_dsp_timer0_select_fast(void); 202 203 void hal_cmu_dsp_timer0_select_slow(void); 204 205 void hal_cmu_dsp_timer1_select_fast(void); 206 207 void hal_cmu_dsp_timer1_select_slow(void); 208 209 int hal_cmu_periph_set_div(uint32_t div); 210 211 int hal_cmu_uart0_set_div(uint32_t div); 212 213 int hal_cmu_uart1_set_div(uint32_t div); 214 215 int hal_cmu_uart2_set_div(uint32_t div); 216 217 int hal_cmu_uart3_set_div(uint32_t div); 218 219 int hal_cmu_spi_set_div(uint32_t div); 220 221 int hal_cmu_slcd_set_div(uint32_t div); 222 223 int hal_cmu_sdio_set_div(uint32_t div); 224 225 int hal_cmu_sdmmc_set_div(uint32_t div); 226 227 int hal_cmu_i2c_set_div(uint32_t div); 228 229 int hal_cmu_uart0_set_freq(enum HAL_CMU_PERIPH_FREQ_T freq); 230 231 int hal_cmu_uart1_set_freq(enum HAL_CMU_PERIPH_FREQ_T freq); 232 233 int hal_cmu_uart2_set_freq(enum HAL_CMU_PERIPH_FREQ_T freq); 234 235 int hal_cmu_uart3_set_freq(enum HAL_CMU_PERIPH_FREQ_T freq); 236 237 int hal_cmu_spi_set_freq(enum HAL_CMU_PERIPH_FREQ_T freq); 238 239 int hal_cmu_slcd_set_freq(enum HAL_CMU_PERIPH_FREQ_T freq); 240 241 int hal_cmu_sdio_set_freq(enum HAL_CMU_PERIPH_FREQ_T freq); 242 243 int hal_cmu_sdmmc_set_freq(enum HAL_CMU_PERIPH_FREQ_T freq); 244 245 int hal_cmu_i2c_set_freq(enum HAL_CMU_PERIPH_FREQ_T freq); 246 247 int hal_cmu_ispi_set_freq(enum HAL_CMU_PERIPH_FREQ_T freq); 248 249 int hal_cmu_pwm_set_freq(enum HAL_PWM_ID_T id, uint32_t freq); 250 251 int hal_cmu_flash_set_freq(enum HAL_CMU_FREQ_T freq); 252 253 int hal_cmu_flash1_set_freq(enum HAL_CMU_FREQ_T freq); 254 255 int hal_cmu_mem_set_freq(enum HAL_CMU_FREQ_T freq); 256 257 int hal_cmu_sys_set_freq(enum HAL_CMU_FREQ_T freq); 258 259 enum HAL_CMU_FREQ_T hal_cmu_sys_get_freq(void); 260 261 enum HAL_CMU_FREQ_T hal_cmu_flash_get_freq(void); 262 263 void hal_cmu_flash_all_reset_clear(int reset); 264 265 int hal_cmu_flash_all_select_pll(enum HAL_CMU_PLL_T pll); 266 267 int hal_cmu_flash_select_pll(enum HAL_CMU_PLL_T pll); 268 269 int hal_cmu_flash1_select_pll(enum HAL_CMU_PLL_T pll); 270 271 int hal_cmu_mem_select_pll(enum HAL_CMU_PLL_T pll); 272 273 int hal_cmu_sys_select_pll(enum HAL_CMU_PLL_T pll); 274 275 int hal_cmu_get_pll_status(enum HAL_CMU_PLL_T pll); 276 277 int hal_cmu_pll_enable(enum HAL_CMU_PLL_T pll, enum HAL_CMU_PLL_USER_T user); 278 279 int hal_cmu_pll_disable(enum HAL_CMU_PLL_T pll, enum HAL_CMU_PLL_USER_T user); 280 281 void hal_cmu_audio_resample_enable(void); 282 283 void hal_cmu_audio_resample_disable(void); 284 285 int hal_cmu_get_audio_resample_status(void); 286 287 int hal_cmu_codec_adc_set_div(uint32_t div); 288 289 uint32_t hal_cmu_codec_adc_get_div(void); 290 291 int hal_cmu_codec_dac_set_div(uint32_t div); 292 293 uint32_t hal_cmu_codec_dac_get_div(void); 294 295 void hal_cmu_codec_clock_enable(void); 296 297 void hal_cmu_codec_clock_disable(void); 298 299 void hal_cmu_codec_vad_clock_enable(int type); 300 301 void hal_cmu_codec_vad_clock_disable(int type); 302 303 void hal_cmu_codec_reset_set(void); 304 305 void hal_cmu_codec_reset_clear(void); 306 307 void hal_cmu_codec_iir_enable(uint32_t speed); 308 309 void hal_cmu_codec_iir_disable(void); 310 311 int hal_cmu_codec_iir_set_div(uint32_t div); 312 313 void hal_cmu_codec_iir_eq_enable(uint32_t speed); 314 315 void hal_cmu_codec_iir_eq_disable(void); 316 317 void hal_cmu_codec_psap_enable(uint32_t speed); 318 319 void hal_cmu_codec_psap_disable(void); 320 321 void hal_cmu_codec_fir_enable(uint32_t speed); 322 323 void hal_cmu_codec_fir_disable(void); 324 325 int hal_cmu_codec_fir_set_div(uint32_t div); 326 327 void hal_cmu_codec_fir_select_sys_clock(void); 328 329 void hal_cmu_codec_fir_select_own_clock(void); 330 331 void hal_cmu_codec_rs_enable(uint32_t speed); 332 333 void hal_cmu_codec_rs_disable(void); 334 335 int hal_cmu_codec_rs_set_div(uint32_t div); 336 337 void hal_cmu_codec_rs_adc_enable(uint32_t speed); 338 339 void hal_cmu_codec_rs_adc_disable(void); 340 341 int hal_cmu_codec_rs_adc_set_div(uint32_t div); 342 343 void hal_cmu_codec_set_fault_mask(uint32_t msk); 344 345 void hal_cmu_i2s_clock_out_enable(enum HAL_I2S_ID_T id); 346 347 void hal_cmu_i2s_clock_out_disable(enum HAL_I2S_ID_T id); 348 349 void hal_cmu_i2s_set_slave_mode(enum HAL_I2S_ID_T id); 350 351 void hal_cmu_i2s_set_master_mode(enum HAL_I2S_ID_T id); 352 353 void hal_cmu_i2s_clock_enable(enum HAL_I2S_ID_T id); 354 355 void hal_cmu_i2s_clock_disable(enum HAL_I2S_ID_T id); 356 357 int hal_cmu_i2s_set_div(enum HAL_I2S_ID_T id, uint32_t div); 358 359 void hal_cmu_i2s_resample_enable(enum HAL_I2S_ID_T id); 360 361 void hal_cmu_i2s_resample_disable(enum HAL_I2S_ID_T id); 362 363 int hal_cmu_i2s_mclk_enable(enum HAL_CMU_I2S_MCLK_ID_T id); 364 365 void hal_cmu_i2s_mclk_disable(void); 366 367 void hal_cmu_pcm_clock_out_enable(void); 368 369 void hal_cmu_pcm_clock_out_disable(void); 370 371 void hal_cmu_pcm_set_slave_mode(int clk_pol); 372 373 void hal_cmu_pcm_set_master_mode(void); 374 375 void hal_cmu_pcm_clock_enable(void); 376 377 void hal_cmu_pcm_clock_disable(void); 378 379 int hal_cmu_pcm_set_div(uint32_t div); 380 381 int hal_cmu_spdif_clock_enable(enum HAL_SPDIF_ID_T id); 382 383 int hal_cmu_spdif_clock_disable(enum HAL_SPDIF_ID_T id); 384 385 int hal_cmu_spdif_set_div(enum HAL_SPDIF_ID_T id, uint32_t div); 386 387 void hal_cmu_usb_set_device_mode(void); 388 389 void hal_cmu_usb_set_host_mode(void); 390 391 enum HAL_CMU_USB_CLOCK_SEL_T hal_cmu_usb_rom_select_clock_source(int pll_en, unsigned int crystal); 392 393 void hal_cmu_usb_rom_set_clock_source(enum HAL_CMU_USB_CLOCK_SEL_T sel); 394 395 void hal_cmu_usb_clock_enable(void); 396 397 void hal_cmu_usb_clock_disable(void); 398 399 void hal_cmu_bt_clock_enable(void); 400 401 void hal_cmu_bt_clock_disable(void); 402 403 void hal_cmu_bt_reset_set(void); 404 405 void hal_cmu_bt_reset_clear(void); 406 407 void hal_cmu_bt_module_init(void); 408 409 void hal_cmu_bt_sys_clock_force_on(void); 410 411 void hal_cmu_bt_sys_clock_auto(void); 412 413 void hal_cmu_bt_sys_force_ram_on(void); 414 415 void hal_cmu_bt_sys_force_ram_auto(void); 416 417 void hal_cmu_bt_sys_set_freq(enum HAL_CMU_FREQ_T freq); 418 419 int hal_cmu_clock_out_enable(enum HAL_CMU_CLOCK_OUT_ID_T id); 420 421 void hal_cmu_clock_out_disable(void); 422 423 void hal_cmu_write_lock(void); 424 425 void hal_cmu_write_unlock(void); 426 427 void hal_cmu_sys_reboot(void); 428 429 void hal_cmu_jtag_enable(void); 430 431 void hal_cmu_jtag_disable(void); 432 433 void hal_cmu_jtag_clock_enable(void); 434 435 void hal_cmu_jtag_clock_disable(void); 436 437 void hal_cmu_simu_init(void); 438 439 void hal_cmu_simu_pass(void); 440 441 void hal_cmu_simu_fail(void); 442 443 void hal_cmu_simu_tag(uint8_t shift); 444 445 void hal_cmu_simu_set_val(uint32_t val); 446 447 uint32_t hal_cmu_simu_get_val(void); 448 449 void hal_cmu_low_freq_mode_init(void); 450 451 void hal_cmu_low_freq_mode_enable(enum HAL_CMU_FREQ_T old_freq, enum HAL_CMU_FREQ_T new_freq); 452 453 void hal_cmu_low_freq_mode_disable(enum HAL_CMU_FREQ_T old_freq, enum HAL_CMU_FREQ_T new_freq); 454 455 void hal_cmu_rom_enable_pll(void); 456 457 void hal_cmu_programmer_enable_pll(void); 458 459 void hal_cmu_init_pll_selection(void); 460 461 void hal_cmu_rom_setup(void); 462 463 void hal_cmu_programmer_setup(void); 464 465 void hal_cmu_fpga_setup(void); 466 467 void hal_cmu_setup(void); 468 469 // Some internal functions 470 471 void hal_cmu_apb_init_div(void); 472 473 void hal_cmu_rom_clock_init(void); 474 475 void hal_cmu_init_chip_feature(uint16_t feature); 476 477 void hal_cmu_osc_x2_enable(void); 478 479 void hal_cmu_osc_x4_enable(void); 480 481 void hal_cmu_module_init_state(void); 482 483 void hal_cmu_ema_init(void); 484 485 void hal_cmu_lpu_wait_26m_ready(void); 486 487 int hal_cmu_lpu_busy(void); 488 489 int hal_cmu_lpu_init(enum HAL_CMU_LPU_CLK_CFG_T cfg); 490 491 int hal_cmu_lpu_sleep(enum HAL_CMU_LPU_SLEEP_MODE_T mode); 492 493 void hal_cmu_set_wakeup_pc(uint32_t pc); 494 495 void hal_cmu_dbg_set_val(uint8_t id, uint32_t val); 496 497 uint32_t hal_cmu_dbg_get_val(uint8_t id); 498 499 void hal_cmu_set_wakeup_vector(uint32_t vector); 500 501 void hal_cmu_wakeup_check(void); 502 503 #ifdef __cplusplus 504 } 505 #endif 506 507 #endif 508 509