1 /* 2 * Copyright (c) 2021 Bestechnic (Shanghai) Co., Ltd. All rights reserved. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 #ifndef __HAL_CODEC_H__ 16 #define __HAL_CODEC_H__ 17 18 #ifdef __cplusplus 19 extern "C" { 20 #endif 21 22 #include "plat_types.h" 23 #include "hal_aud.h" 24 25 #define DAC_DC_VALID_MARK (0xDAC0DC00) 26 27 #define DB_TO_QDB(n) ((n) * 4) 28 #define QDB_TO_DB(n) ((n) / 4) 29 30 enum HAL_CODEC_ID_T { 31 HAL_CODEC_ID_0 = 0, 32 HAL_CODEC_ID_NUM, 33 }; 34 35 enum HAL_CODEC_CONFIG_FLAG_T{ 36 HAL_CODEC_CONFIG_NULL = 0x00, 37 38 HAL_CODEC_CONFIG_BITS = 0x01, 39 HAL_CODEC_CONFIG_SAMPLE_RATE = 0x02, 40 HAL_CODEC_CONFIG_CHANNEL_NUM = 0x04, 41 HAL_CODEC_CONFIG_CHANNEL_MAP = 0x08, 42 HAL_CODEC_CONFIG_VOL = 0x10, 43 44 HAL_CODEC_CONFIG_ALL = 0xff, 45 }; 46 47 enum HAL_CODEC_DAC_RESET_STAGE_T { 48 HAL_CODEC_DAC_PRE_RESET, 49 HAL_CODEC_DAC_POST_RESET, 50 }; 51 52 enum HAL_CODEC_SYNC_TYPE_T { 53 HAL_CODEC_SYNC_TYPE_NONE, 54 HAL_CODEC_SYNC_TYPE_GPIO, 55 HAL_CODEC_SYNC_TYPE_BT, 56 HAL_CODEC_SYNC_TYPE_WIFI, 57 }; 58 59 enum HAL_CODEC_PERF_TEST_POWER_T { 60 HAL_CODEC_PERF_TEST_30MW, 61 HAL_CODEC_PERF_TEST_10MW, 62 HAL_CODEC_PERF_TEST_5MW, 63 HAL_CODEC_PERF_TEST_M60DB, 64 65 HAL_CODEC_PERF_TEST_QTY 66 }; 67 68 enum HAL_CODEC_TIMER_TRIG_MODE_T { 69 HAL_CODEC_TIMER_TRIG_MODE_DAC, 70 HAL_CODEC_TIMER_TRIG_MODE_ADC, 71 HAL_CODEC_TIMER_TRIG_MODE_ANY, 72 73 HAL_CODEC_TIMER_TRIG_MODE_QTY, 74 }; 75 76 enum HAL_CODEC_PSAP_MODE_T { 77 HAL_CODEC_PSAP_MODE_ADC = 0, 78 HAL_CODEC_PSAP_MODE_ADC_DAC, 79 HAL_CODEC_PSAP_MODE_DAC, 80 HAL_CODEC_PSAP_MODE_DRC_LIM, 81 }; 82 83 typedef enum { 84 HAL_CODEC_ECHO_PATH_DAC1_DAC2_PSAP = 0, 85 HAL_CODEC_ECHO_PATH_DAC1_ALONE = 1, 86 HAL_CODEC_ECHO_PATH_ALL = 2, 87 HAL_CODEC_ECHO_PATH_DAC2_ALONE = 3, 88 HAL_CODEC_ECHO_PATH_QTY 89 } HAL_CODEC_ECHO_PATH_T; 90 91 typedef void (*HAL_CODEC_DAC_RESET_CALLBACK)(enum HAL_CODEC_DAC_RESET_STAGE_T stage); 92 typedef void (*HAL_CODEC_SW_OUTPUT_COEF_CALLBACK)(float coef); 93 typedef void (*HAL_CODEC_BT_TRIGGER_CALLBACK)(void); 94 typedef void (*HAL_CODEC_EVENT_TRIGGER_CALLBACK)(void); 95 typedef void (*HAL_CODEC_TIMER_TRIGGER_CALLBACK)(void); 96 typedef void (*HAL_CODEC_IRQ_CALLBACK)(uint32_t status); 97 typedef void (*HAL_CODEC_IRQ_CALLBACK2)(uint32_t status1, uint32_t status2); 98 99 struct HAL_CODEC_CONFIG_T { 100 enum AUD_BITS_T bits; 101 enum AUD_SAMPRATE_T sample_rate; 102 enum AUD_CHANNEL_NUM_T channel_num; 103 enum AUD_CHANNEL_MAP_T channel_map; 104 105 uint32_t use_dma:1; 106 uint32_t vol:7; 107 108 enum AUD_IO_PATH_T io_path; 109 110 uint32_t set_flag; 111 }; 112 113 struct dac_classg_cfg { 114 uint8_t thd2; 115 uint8_t thd1; 116 uint8_t thd0; 117 uint8_t lr; 118 uint8_t step_4_3n; 119 uint8_t quick_down; 120 uint16_t wind_width; 121 }; 122 123 struct HAL_CODEC_PSAP_CFG_T { 124 enum HAL_CODEC_PSAP_MODE_T mode; 125 uint8_t din0_samp_delay; 126 float din0_gain; 127 uint8_t din1_sign; 128 }; 129 130 struct HAL_CODEC_DAC_DRE_CALIB_CFG_T { 131 uint32_t valid; 132 uint32_t dc_l; 133 uint32_t dc_r; 134 float gain_l; 135 float gain_r; 136 uint16_t ana_dc_l; 137 uint16_t ana_dc_r; 138 uint8_t ana_gain; 139 uint8_t ini_ana_gain; 140 uint8_t gain_offset; 141 uint8_t step_mode; 142 uint8_t top_gain; 143 uint8_t rsv[3]; 144 }; 145 146 uint32_t hal_codec_get_input_path_cfg(enum AUD_IO_PATH_T io_path); 147 uint32_t hal_codec_get_all_input_path_cfg(void); 148 uint32_t hal_codec_get_input_map_chan_num(uint32_t ch_map); 149 uint32_t hal_codec_get_input_path_chan_num(enum AUD_IO_PATH_T io_path); 150 void hal_codec_set_dac_volume_table(const struct CODEC_DAC_VOL_T *table_ptr, uint32_t table_num); 151 const struct CODEC_DAC_VOL_T *hal_codec_get_dac_volume(uint32_t index); 152 const CODEC_ADC_VOL_T *hal_codec_get_adc_volume(uint32_t index); 153 uint32_t hal_codec_get_mic_chan_volume_level(uint32_t map); 154 uint8_t hal_codec_get_digmic_hw_index(uint8_t chan); 155 uint32_t hal_codec_get_real_sample_rate(enum AUD_SAMPRATE_T rate, bool resamp); 156 157 int hal_codec_open(enum HAL_CODEC_ID_T id); 158 int hal_codec_close(enum HAL_CODEC_ID_T id); 159 void hal_codec_crash_mute(void); 160 void hal_codec_stop_playback_stream(enum HAL_CODEC_ID_T id); 161 void hal_codec_start_playback_stream(enum HAL_CODEC_ID_T id); 162 int hal_codec_start_stream(enum HAL_CODEC_ID_T id, enum AUD_STREAM_T stream); 163 int hal_codec_stop_stream(enum HAL_CODEC_ID_T id, enum AUD_STREAM_T stream); 164 int hal_codec_start_interface(enum HAL_CODEC_ID_T id, enum AUD_STREAM_T stream, int dma); 165 int hal_codec_stop_interface(enum HAL_CODEC_ID_T id, enum AUD_STREAM_T stream); 166 int hal_codec_setup_stream(enum HAL_CODEC_ID_T id, enum AUD_STREAM_T stream, const struct HAL_CODEC_CONFIG_T *cfg); 167 int hal_codec_anc_adc_enable(enum ANC_TYPE_T type); 168 int hal_codec_anc_adc_disable(enum ANC_TYPE_T type); 169 enum AUD_SAMPRATE_T hal_codec_anc_convert_rate(enum AUD_SAMPRATE_T rate); 170 int hal_codec_anc_dma_enable(enum HAL_CODEC_ID_T id); 171 int hal_codec_anc_dma_disable(enum HAL_CODEC_ID_T id); 172 void hal_codec_set_anc_boost_gain_attn(float attn); 173 void hal_codec_apply_anc_adc_gain_offset(enum ANC_TYPE_T type, int8_t offset_l, int8_t offset_r); 174 int hal_codec_aux_mic_dma_enable(enum HAL_CODEC_ID_T id); 175 int hal_codec_aux_mic_dma_disable(enum HAL_CODEC_ID_T id); 176 uint32_t hal_codec_get_alg_dac_shift(void); 177 void hal_codec_set_dac_reset_callback(HAL_CODEC_DAC_RESET_CALLBACK callback); 178 void hal_codec_set_sw_output_coef_callback(HAL_CODEC_SW_OUTPUT_COEF_CALLBACK callback); 179 void hal_codec_set_dac2_sw_output_coef_callback(HAL_CODEC_SW_OUTPUT_COEF_CALLBACK callback); 180 void hal_codec_dac_gain_m60db_check(enum HAL_CODEC_PERF_TEST_POWER_T type); 181 void hal_codec_set_noise_reduction(bool enable); 182 void hal_codec_classg_config(const struct dac_classg_cfg *cfg); 183 void hal_codec_set_dac_dc_gain_attn(float attn); 184 void hal_codec_set_dac_dc_offset(int16_t dc_l, int16_t dc_r); 185 void hal_codec_sidetone_enable(void); 186 void hal_codec_sidetone_disable(void); 187 int hal_codec_sidetone_gain_ramp_up(float step); 188 int hal_codec_sidetone_gain_ramp_down(float step); 189 void hal_codec_select_adc_iir_mic(uint32_t index, enum AUD_CHANNEL_MAP_T mic_map); 190 void hal_codec_dac_mute(bool mute); 191 void hal_codec_adc_mute(bool mute); 192 int hal_codec_set_chan_vol(enum AUD_STREAM_T stream, enum AUD_CHANNEL_MAP_T ch_map, uint8_t vol); 193 void hal_codec_sync_dac_enable(enum HAL_CODEC_SYNC_TYPE_T type); 194 void hal_codec_sync_dac_disable(void); 195 void hal_codec_sync_adc_enable(enum HAL_CODEC_SYNC_TYPE_T type); 196 void hal_codec_sync_adc_disable(void); 197 void hal_codec_sync_dac_resample_rate_enable(enum HAL_CODEC_SYNC_TYPE_T type); 198 void hal_codec_sync_dac_resample_rate_disable(void); 199 void hal_codec_sync_adc_resample_rate_enable(enum HAL_CODEC_SYNC_TYPE_T type); 200 void hal_codec_sync_adc_resample_rate_disable(void); 201 void hal_codec_sync_dac_gain_enable(enum HAL_CODEC_SYNC_TYPE_T type); 202 void hal_codec_sync_dac_gain_disable(void); 203 void hal_codec_sync_adc_gain_enable(enum HAL_CODEC_SYNC_TYPE_T type); 204 void hal_codec_sync_adc_gain_disable(void); 205 int hal_codec_dac_reset_set(void); 206 int hal_codec_dac_reset_clear(void); 207 int hal_codec_dac_sdm_reset_set(void); 208 int hal_codec_dac_sdm_reset_clear(void); 209 void hal_codec_dac_sdm_reset_pulse(void); 210 void hal_codec_tune_resample_rate(enum AUD_STREAM_T stream, float ratio); 211 void hal_codec_tune_both_resample_rate(float ratio); 212 void hal_codec_get_dac_gain(float *left_gain,float *right_gain); 213 int hal_codec_select_clock_out(uint32_t cfg); 214 int hal_codec_config_digmic_phase(uint8_t phase); 215 void hal_codec_mc_enable(void); 216 void hal_codec_mc_disable(void); 217 void hal_codec_setup_mc(enum AUD_CHANNEL_NUM_T channel_num, enum AUD_BITS_T bits); 218 void hal_codec_dsd_enable(void); 219 void hal_codec_dsd_disable(void); 220 void hal_codec_swap_output(bool swap); 221 222 uint32_t hal_codec_get_echo_path(void); 223 void hal_codec_set_echo_path(HAL_CODEC_ECHO_PATH_T path); 224 225 void hal_codec_gpio_trigger_debounce_enable(void); 226 void hal_codec_gpio_trigger_debounce_disable(void); 227 228 uint32_t hal_codec_timer_get(void); 229 uint32_t hal_codec_timer_ticks_to_us(uint32_t ticks); 230 void hal_codec_timer_trigger_read(void); 231 232 void hal_codec_anc_fb_check_set_irq_handler(HAL_CODEC_IRQ_CALLBACK cb); 233 234 int hal_codec_vad_open(const struct AUD_VAD_CONFIG_T *cfg); 235 int hal_codec_vad_close(void); 236 int hal_codec_vad_start(void); 237 int hal_codec_vad_stop(void); 238 uint32_t hal_codec_vad_recv_data(uint8_t *dst, uint32_t dst_size); 239 void hal_codec_get_vad_data_info(struct CODEC_VAD_BUF_INFO_T* vad_buf_info); 240 241 void hal_codec_set_bt_trigger_callback(HAL_CODEC_BT_TRIGGER_CALLBACK callback); 242 int hal_codec_bt_trigger_start(void); 243 int hal_codec_bt_trigger_stop(void); 244 void hal_codec_set_bt_trigger_ex_callback(uint32_t index, HAL_CODEC_BT_TRIGGER_CALLBACK callback); 245 int hal_codec_bt_trigger_ex_start(uint32_t index); 246 int hal_codec_bt_trigger_ex_stop(uint32_t index); 247 248 void hal_codec_min_phase_mode_enable(enum AUD_STREAM_T stream); 249 void hal_codec_min_phase_mode_disable(enum AUD_STREAM_T stream); 250 251 int hal_codec_timer_trig_i2s_enable(enum HAL_CODEC_TIMER_TRIG_MODE_T mode, uint32_t ticks, bool periodic); 252 int hal_codec_timer_trig_i2s_disable(void); 253 254 void hal_codec_iir_enable(uint32_t speed); 255 void hal_codec_iir_disable(void); 256 257 void hal_codec_iir_eq_enable(uint32_t speed); 258 void hal_codec_iir_eq_disable(void); 259 260 void hal_codec_fir_enable(uint32_t speed); 261 void hal_codec_fir_disable(void); 262 void hal_codec_fir_select_sys_clock(void); 263 void hal_codec_fir_select_own_clock(void); 264 265 void hal_codec_psap_enable(uint32_t speed); 266 void hal_codec_psap_disable(void); 267 void hal_codec_psap_setup(enum AUD_CHANNEL_MAP_T ch_map, const struct HAL_CODEC_PSAP_CFG_T *cfg); 268 269 int hal_codec_dac2_start_interface(enum HAL_CODEC_ID_T id, int dma); 270 int hal_codec_dac2_stop_interface(enum HAL_CODEC_ID_T id); 271 int hal_codec_dac2_setup_stream(enum HAL_CODEC_ID_T id, const struct HAL_CODEC_CONFIG_T *cfg); 272 void hal_codec_dac2_mute(bool mute); 273 int hal_codec_dac2_set_chan_vol(enum AUD_CHANNEL_MAP_T ch_map, uint8_t vol); 274 275 void hal_codec_sync_dac2_disable(void); 276 void hal_codec_sync_dac2_enable(enum HAL_CODEC_SYNC_TYPE_T type); 277 void hal_codec_sync_dac2_resample_rate_disable(void); 278 void hal_codec_sync_dac2_resample_rate_enable(enum HAL_CODEC_SYNC_TYPE_T type); 279 void hal_codec_sync_dac2_gain_disable(void); 280 void hal_codec_sync_dac2_gain_enable(enum HAL_CODEC_SYNC_TYPE_T type); 281 282 void hal_codec_tune_dac2_resample_rate(enum AUD_STREAM_T stream, float ratio); 283 284 void hal_codec_set_dac_bt_sync_source(uint32_t src); 285 void hal_codec_set_adc_bt_sync_source(uint32_t src); 286 void hal_codec_set_dac2_bt_sync_source(uint32_t src); 287 void hal_codec_pll_bt_sync_source(uint32_t src); 288 289 void hal_codec_dac_dre_init_calib_cfg(void); 290 struct HAL_CODEC_DAC_DRE_CALIB_CFG_T *hal_codec_dac_dre_get_calib_cfg(uint32_t *nr); 291 int hal_codec_dac_dre_check_calib_cfg(struct HAL_CODEC_DAC_DRE_CALIB_CFG_T *cfg); 292 void hal_codec_set_dac_calib_status(bool status); 293 void hal_codec_set_dac_ana_gain(uint8_t ini_ana_gain, uint8_t gain_offset); 294 bool hal_codec_get_dig_dc_calib_value_high_dre_gain(int32_t *dc_l, int32_t *dc_r); 295 int hal_codec_dac_dc_auto_calib_enable(void); 296 int hal_codec_dac_dc_auto_calib_disable(void); 297 void hal_codec_dac_dc_offset_enable(int32_t dc_l, int32_t dc_r); 298 void hal_codec_set_dig_dac_gain_dr(enum AUD_CHANNEL_MAP_T map, int32_t gain); 299 int hal_codec_trigger_en(HAL_CODEC_IRQ_CALLBACK cb); 300 int hal_codec_timer_trigger_en(HAL_CODEC_IRQ_CALLBACK cb); 301 302 #ifdef __cplusplus 303 } 304 #endif 305 306 #endif 307