1 /* 2 * Copyright (c) 2021 Bestechnic (Shanghai) Co., Ltd. All rights reserved. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 #ifndef __HAL_DMA_H__ 16 #define __HAL_DMA_H__ 17 18 #ifdef __cplusplus 19 extern "C" { 20 #endif 21 22 #include "stdint.h" 23 #include "stdbool.h" 24 25 #define HAL_DMA_CHAN_NONE 0xFF 26 27 #define HAL_DMA_MAX_DESC_XFER_SIZE 0xFFF 28 29 enum HAL_DMA_RET_T { 30 HAL_DMA_OK, 31 HAL_DMA_ERR, 32 }; 33 34 enum HAL_DMA_GET_CHAN_T { 35 HAL_DMA_HIGH_PRIO, 36 HAL_DMA_LOW_PRIO, 37 HAL_DMA_LOW_PRIO_ONLY 38 }; 39 40 // DMA Type of DMA controller 41 enum HAL_DMA_FLOW_CONTROL_T { 42 HAL_DMA_FLOW_M2M_DMA = 0, /* Memory to memory - DMA control */ 43 HAL_DMA_FLOW_M2P_DMA = 1, /* Memory to peripheral - DMA control */ 44 HAL_DMA_FLOW_P2M_DMA = 2, /* Peripheral to memory - DMA control */ 45 HAL_DMA_FLOW_P2P_DMA = 3, /* Source peripheral to destination peripheral - DMA control */ 46 HAL_DMA_FLOW_P2P_DSTPERIPH = 4, /* Source peripheral to destination peripheral - destination peripheral control */ 47 HAL_DMA_FLOW_M2P_PERIPH = 5, /* Memory to peripheral - peripheral control */ 48 HAL_DMA_FLOW_P2M_PERIPH = 6, /* Peripheral to memory - peripheral control */ 49 HAL_DMA_FLOW_P2P_SRCPERIPH = 7, /* Source peripheral to destination peripheral - source peripheral control */ 50 51 HAL_DMA_FLOW_FLAG_SI = 0x40, 52 HAL_DMA_FLOW_FLAG_DI = 0x80, 53 HAL_DMA_FLOW_FLAG_MASK = (HAL_DMA_FLOW_FLAG_SI | HAL_DMA_FLOW_FLAG_DI), 54 55 HAL_DMA_FLOW_M2P_DI_DMA = HAL_DMA_FLOW_M2P_DMA | HAL_DMA_FLOW_FLAG_DI, 56 HAL_DMA_FLOW_P2M_SI_DMA = HAL_DMA_FLOW_P2M_DMA | HAL_DMA_FLOW_FLAG_SI, 57 HAL_DMA_FLOW_P2P_DI_DMA = HAL_DMA_FLOW_P2P_DMA | HAL_DMA_FLOW_FLAG_DI, 58 HAL_DMA_FLOW_P2P_SI_DMA = HAL_DMA_FLOW_P2P_DMA | HAL_DMA_FLOW_FLAG_SI, 59 }; 60 61 // DMA Burst size in Source and Destination definitions 62 enum HAL_DMA_BSIZE_T { 63 HAL_DMA_BSIZE_1 = 0, /* Burst size = 1 */ 64 HAL_DMA_BSIZE_4 = 1, /* Burst size = 4 */ 65 HAL_DMA_BSIZE_8 = 2, /* Burst size = 8 */ 66 HAL_DMA_BSIZE_16 = 3, /* Burst size = 16 */ 67 HAL_DMA_BSIZE_32 = 4, /* Burst size = 32 */ 68 HAL_DMA_BSIZE_64 = 5, /* Burst size = 64 */ 69 HAL_DMA_BSIZE_128 = 6, /* Burst size = 128 */ 70 HAL_DMA_BSIZE_256 = 7, /* Burst size = 256 */ 71 }; 72 73 // Width in Source transfer width and Destination transfer width definitions 74 enum HAL_DMA_WDITH_T { 75 HAL_DMA_WIDTH_BYTE = 0, /* Width = 1 byte */ 76 HAL_DMA_WIDTH_HALFWORD = 1, /* Width = 2 bytes */ 77 HAL_DMA_WIDTH_WORD = 2, /* Width = 4 bytes */ 78 }; 79 80 enum HAL_DMA_PERIPH_T { 81 HAL_DMA_PERIPH_NULL = 0, 82 HAL_GPDMA_MEM = 1, 83 HAL_AUDMA_MEM = 2, 84 85 HAL_GPDMA_SDIO = 10, 86 HAL_GPDMA_SDMMC = 11, 87 HAL_GPDMA_I2C0_RX = 12, 88 HAL_GPDMA_I2C0_TX = 13, 89 HAL_GPDMA_SPI_RX = 14, 90 HAL_GPDMA_SPI_TX = 15, 91 HAL_GPDMA_SPILCD_RX = 16, 92 HAL_GPDMA_SPILCD_TX = 17, 93 HAL_GPDMA_UART0_RX = 18, 94 HAL_GPDMA_UART0_TX = 19, 95 HAL_GPDMA_UART1_RX = 20, 96 HAL_GPDMA_UART1_TX = 21, 97 HAL_GPDMA_ISPI_RX = 22, 98 HAL_GPDMA_ISPI_TX = 23, 99 HAL_GPDMA_UART2_RX = 24, 100 HAL_GPDMA_UART2_TX = 25, 101 HAL_GPDMA_FLASH0 = 26, 102 HAL_GPDMA_FLASH1 = 27, 103 HAL_GPDMA_I2C1_RX = 28, 104 HAL_GPDMA_I2C1_TX = 29, 105 HAL_GPDMA_I2C2_RX = 30, 106 HAL_GPDMA_I2C2_TX = 31, 107 HAL_GPDMA_I2C3_RX = 32, 108 HAL_GPDMA_I2C3_TX = 33, 109 HAL_GPDMA_UART3_RX = 34, 110 HAL_GPDMA_UART3_TX = 35, 111 HAL_GPDMA_IR_RX = 36, 112 HAL_GPDMA_IR_TX = 37, 113 114 HAL_AUDMA_CODEC_RX = 50, 115 HAL_AUDMA_CODEC_TX = 51, 116 HAL_AUDMA_BTPCM_RX = 52, 117 HAL_AUDMA_BTPCM_TX = 53, 118 HAL_AUDMA_I2S0_RX = 54, 119 HAL_AUDMA_I2S0_TX = 55, 120 HAL_AUDMA_DPD_RX = 56, 121 HAL_AUDMA_DPD_TX = 57, 122 HAL_AUDMA_SPDIF0_RX = 58, 123 HAL_AUDMA_SPDIF0_TX = 59, 124 HAL_AUDMA_SPDIF1_RX = 60, 125 HAL_AUDMA_SPDIF1_TX = 61, 126 HAL_AUDMA_DSD_RX = 62, 127 HAL_AUDMA_DSD_TX = 63, 128 HAL_AUDMA_MC_RX = 64, 129 HAL_AUDMA_FFT_RX = 65, 130 HAL_AUDMA_FFT_TX = 66, 131 HAL_AUDMA_FIR_RX = 67, 132 HAL_AUDMA_FIR_TX = 68, 133 HAL_AUDMA_IIR_RX = 69, 134 HAL_AUDMA_IIR_TX = 70, 135 HAL_AUDMA_BTDUMP = 71, 136 HAL_AUDMA_I2S1_RX = 72, 137 HAL_AUDMA_I2S1_TX = 73, 138 HAL_AUDMA_FM_RX = 74, 139 HAL_AUDMA_FMDUMP0 = 75, 140 HAL_AUDMA_FMDUMP1 = 76, 141 HAL_AUDMA_CODEC_RX2 = 77, 142 HAL_AUDMA_CODEC_TX2 = 78, 143 HAL_AUDMA_CODEC_TX3 = 79, 144 HAL_AUDMA_CAP_SENS = 80, 145 146 HAL_DMA_PERIPH_QTY, 147 }; 148 149 struct HAL_DMA_DESC_T; 150 151 typedef void (*HAL_DMA_IRQ_HANDLER_T)(uint8_t chan, uint32_t remain_tsize, uint32_t error, struct HAL_DMA_DESC_T *lli); 152 153 typedef void (*HAL_DMA_START_CALLBACK_T)(uint8_t chan); 154 155 typedef void (*HAL_DMA_DELAY_FUNC)(uint32_t ms); 156 157 // DMA structure using for DMA configuration 158 struct HAL_DMA_CH_CFG_T { 159 uint8_t ch; /* DMA channel number */ 160 uint8_t try_burst; 161 uint16_t src_tsize; /* Length/Size of transfer */ 162 enum HAL_DMA_WDITH_T src_width; 163 enum HAL_DMA_WDITH_T dst_width; 164 enum HAL_DMA_BSIZE_T src_bsize; 165 enum HAL_DMA_BSIZE_T dst_bsize; 166 enum HAL_DMA_FLOW_CONTROL_T type; /* Transfer Type */ 167 enum HAL_DMA_PERIPH_T src_periph; 168 enum HAL_DMA_PERIPH_T dst_periph; 169 uint32_t src; /* Physical Source Address */ 170 uint32_t dst; /* Physical Destination Address */ 171 HAL_DMA_IRQ_HANDLER_T handler; 172 HAL_DMA_START_CALLBACK_T start_cb; 173 }; 174 175 // Transfer Descriptor structure typedef 176 struct HAL_DMA_DESC_T { 177 uint32_t src; /* Source address */ 178 uint32_t dst; /* Destination address */ 179 uint32_t lli; /* Pointer to next descriptor structure */ 180 uint32_t ctrl; /* Control word that has transfer size, type etc. */ 181 }; 182 183 // DMA 2D configuration structure 184 struct HAL_DMA_2D_CFG_T { 185 int16_t xmodify; 186 uint16_t xcount; 187 int16_t ymodify; 188 uint16_t ycount; 189 }; 190 191 struct HAL_DMA_BURST_ADDR_INC_T { 192 bool src_inc_en; 193 bool dst_inc_en; 194 int16_t src_inc_val; 195 int16_t dst_inc_val; 196 }; 197 198 //============================================================= 199 200 void hal_dma_open(void); 201 202 void hal_dma_close(void); 203 204 void hal_dma_sleep(void); 205 206 void hal_dma_wakeup(void); 207 208 bool hal_dma_chan_busy(uint8_t ch); 209 210 uint8_t hal_dma_get_chan(enum HAL_DMA_PERIPH_T periph, enum HAL_DMA_GET_CHAN_T policy); 211 212 void hal_dma_free_chan(uint8_t ch); 213 214 void hal_dma_cancel(uint8_t ch); 215 216 void hal_dma_stop(uint8_t ch); 217 218 enum HAL_DMA_RET_T hal_dma_init_desc(struct HAL_DMA_DESC_T *desc, 219 const struct HAL_DMA_CH_CFG_T *cfg, 220 const struct HAL_DMA_DESC_T *next, 221 int tc_irq); 222 223 enum HAL_DMA_RET_T hal_dma_sg_start(const struct HAL_DMA_DESC_T *desc, 224 const struct HAL_DMA_CH_CFG_T *cfg); 225 226 enum HAL_DMA_RET_T hal_dma_sg_2d_start(const struct HAL_DMA_DESC_T *desc, 227 const struct HAL_DMA_CH_CFG_T *cfg, 228 const struct HAL_DMA_2D_CFG_T *src_2d, 229 const struct HAL_DMA_2D_CFG_T *dst_2d); 230 231 enum HAL_DMA_RET_T hal_dma_start(const struct HAL_DMA_CH_CFG_T *cfg); 232 233 uint32_t hal_dma_get_cur_src_addr(uint8_t ch); 234 235 uint32_t hal_dma_get_cur_dst_addr(uint8_t ch); 236 237 void hal_dma_get_cur_src_remain_and_addr(uint8_t ch, uint32_t *remain, uint32_t *src); 238 239 uint32_t hal_dma_get_sg_remain_size(uint8_t ch); 240 241 enum HAL_DMA_RET_T hal_dma_irq_run_chan(uint8_t ch); 242 243 bool hal_dma_busy(void); 244 245 HAL_DMA_DELAY_FUNC hal_dma_set_delay_func(HAL_DMA_DELAY_FUNC new_func); 246 247 void hal_dma_remap_periph(enum HAL_DMA_PERIPH_T periph, int enable); 248 249 void hal_dma_tc_irq_enable(uint8_t ch); 250 251 void hal_dma_tc_irq_disable(uint8_t ch); 252 253 void hal_dma_set_burst_addr_inc(uint8_t ch, const struct HAL_DMA_BURST_ADDR_INC_T *inc); 254 255 void hal_dma_clear_burst_addr_inc(uint8_t ch); 256 257 void hal_dma_set_desc_burst_addr_inc(struct HAL_DMA_DESC_T *desc, const struct HAL_DMA_BURST_ADDR_INC_T *inc); 258 259 void hal_dma_clear_desc_burst_addr_inc(struct HAL_DMA_DESC_T *desc); 260 261 void hal_dma_record_busy_chan(void); 262 263 void hal_dma_print_busy_chan(void); 264 265 //============================================================= 266 267 #define hal_audma_open hal_dma_open 268 #define hal_audma_close hal_dma_close 269 #define hal_audma_chan_busy hal_dma_chan_busy 270 #define hal_audma_get_chan hal_dma_get_chan 271 #define hal_audma_free_chan hal_dma_free_chan 272 #define hal_audma_cancel hal_dma_cancel 273 #define hal_audma_stop hal_dma_stop 274 #define hal_audma_init_desc hal_dma_init_desc 275 #define hal_audma_sg_start hal_dma_sg_start 276 #define hal_audma_start hal_dma_start 277 #define hal_audma_get_cur_src_addr hal_dma_get_cur_src_addr 278 #define hal_audma_get_cur_dst_addr hal_dma_get_cur_dst_addr 279 #define hal_audma_get_sg_remain_size hal_dma_get_sg_remain_size 280 #define hal_audma_irq_run_chan hal_dma_irq_run_chan 281 282 #define hal_gpdma_open hal_dma_open 283 #define hal_gpdma_close hal_dma_close 284 #define hal_gpdma_chan_busy hal_dma_chan_busy 285 #define hal_gpdma_get_chan hal_dma_get_chan 286 #define hal_gpdma_free_chan hal_dma_free_chan 287 #define hal_gpdma_cancel hal_dma_cancel 288 #define hal_gpdma_stop hal_dma_stop 289 #define hal_gpdma_init_desc hal_dma_init_desc 290 #define hal_gpdma_sg_start hal_dma_sg_start 291 #define hal_gpdma_start hal_dma_start 292 #define hal_gpdma_get_cur_src_addr hal_dma_get_cur_src_addr 293 #define hal_gpdma_get_cur_dst_addr hal_dma_get_cur_dst_addr 294 #define hal_gpdma_get_sg_remain_size hal_dma_get_sg_remain_size 295 #define hal_gpdma_irq_run_chan hal_dma_irq_run_chan 296 297 //============================================================= 298 299 #ifdef __cplusplus 300 } 301 #endif 302 303 #endif 304