1 /* 2 * Copyright (c) 2021 Bestechnic (Shanghai) Co., Ltd. All rights reserved. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 #ifndef __REG_DSI_H__ 16 #define __REG_DSI_H__ 17 18 #include "plat_types.h" 19 20 struct DSI_REG_T { 21 __IO uint32_t REG_000; 22 __IO uint32_t REG_004; 23 __IO uint32_t REG_008; 24 __IO uint32_t REG_00C; 25 __IO uint32_t REG_010; 26 __IO uint32_t REG_014; 27 __IO uint32_t REG_018; 28 __IO uint32_t REG_01C; 29 __IO uint32_t REG_020; 30 __IO uint32_t REG_024; 31 __IO uint32_t REG_028; 32 __IO uint32_t REG_02C; 33 __IO uint32_t REG_030; 34 __IO uint32_t REG_034; 35 __IO uint32_t REG_038; 36 __IO uint32_t REG_03C; 37 __IO uint32_t REG_040; 38 __IO uint32_t REG_044; 39 __IO uint32_t REG_048; 40 __IO uint32_t REG_RES[10]; 41 __IO uint32_t REG_074; 42 }; 43 44 // reg_00 45 #define DSI_R_LANE_NUM(n) (((n) & 0x3) << 0) 46 #define DSI_R_LANE_NUM_MASK (0x3 << 0) 47 #define DSI_R_LANE_NUM_SHIFT (0) 48 #define DSI_R_LPCD_EN (1 << 2) 49 #define DSI_R_LPCD_DLY(n) (((n) & 0x3) << 3) 50 #define DSI_R_LPCD_DLY_MASK (0x3 << 3) 51 #define DSI_R_LPCD_DLY_SHIFT (3) 52 #define DSI_R_HSA_LP (1 << 5) 53 #define DSI_R_HSE_EN (1 << 6) 54 #define DSI_R_HBP_LP (1 << 7) 55 #define DSI_R_HFP_LP (1 << 8) 56 #define DSI_R_EOTP_EN (1 << 9) 57 #define DSI_R_CLANE_LP_EN (1 << 10) 58 #define DSI_R_VIDEO_MODE (1 << 11) 59 #define DSI_R_T_BTA(n) (((n) & 0xF) << 12) 60 #define DSI_R_T_BTA_MASK (0xF << 12) 61 #define DSI_R_T_BTA_SHIFT (12) 62 #define DSI_R_T_LPX(n) (((n) & 0xF) << 16) 63 #define DSI_R_T_LPX_MASK (0xF << 16) 64 #define DSI_R_T_LPX_SHIFT (16) 65 #define DSI_R_CLK_T_LPX(n) (((n) & 0xF) << 20) 66 #define DSI_R_CLK_T_LPX_MASK (0xF << 20) 67 #define DSI_R_CLK_T_LPX_SHIFT (20) 68 #define DSI_R_CLK_PRE(n) (((n) & 0x3) << 24) 69 #define DSI_R_CLK_PRE_MASK (0x3 << 24) 70 #define DSI_R_CLK_PRE_SHIFT (24) 71 #define DSI_R_CLK_POST(n) (((n) & 0x3F) << 26) 72 #define DSI_R_CLK_POST_MASK (0x3F << 26) 73 #define DSI_R_CLK_POST_SHIFT (26) 74 75 // reg_04 76 #define DSI_R_HS_EXIT_TIME(n) (((n) & 0x3F) << 0) 77 #define DSI_R_HS_EXIT_TIME_MASK (0x3F << 0) 78 #define DSI_R_HS_EXIT_TIME_SHIFT (0) 79 #define DSI_R_HS_PRPR_TIME(n) (((n) & 0xF) << 6) 80 #define DSI_R_HS_PRPR_TIME_MASK (0xF << 6) 81 #define DSI_R_HS_PRPR_TIME_SHIFT (6) 82 #define DSI_R_HS_ZERO_TIME(n) (((n) & 0x3F) << 10) 83 #define DSI_R_HS_ZERO_TIME_MASK (0x3F << 10) 84 #define DSI_R_HS_ZERO_TIME_SHIFT (10) 85 #define DSI_R_HS_TRAIL_TIME(n) (((n) & 0x3F) << 16) 86 #define DSI_R_HS_TRAIL_TIME_MASK (0x3F << 16) 87 #define DSI_R_HS_TRAIL_TIME_SHIFT (16) 88 #define DSI_R_T_WAKEUP(n) (((n) & 0x3FF) << 22) 89 #define DSI_R_T_WAKEUP_MASK (0x3FF << 22) 90 #define DSI_R_T_WAKEUP_SHIFT (22) 91 92 // reg_08 93 #define DSI_R_CLK_EXIT_TIME(n) (((n) & 0x3F) << 0) 94 #define DSI_R_CLK_EXIT_TIME_MASK (0x3F << 0) 95 #define DSI_R_CLK_EXIT_TIME_SHIFT (0) 96 #define DSI_R_CLK_PRPR_TIME(n) (((n) & 0xF) << 6) 97 #define DSI_R_CLK_PRPR_TIME_MASK (0xF << 6) 98 #define DSI_R_CLK_PRPR_TIME_SHIFT (6) 99 #define DSI_R_CLK_ZERO_TIME(n) (((n) & 0x3F) << 10) 100 #define DSI_R_CLK_ZERO_TIME_MASK (0x3F << 10) 101 #define DSI_R_CLK_ZERO_TIME_SHIFT (10) 102 #define DSI_R_CLK_TRAIL_TIME(n) (((n) & 0x3F) << 16) 103 #define DSI_R_CLK_TRAIL_TIME_MASK (0x3F << 16) 104 #define DSI_R_CLK_TRAIL_TIME_SHIFT (16) 105 #define DSI_R_CLK_T_WAKEUP(n) (((n) & 0x3FF) << 22) 106 #define DSI_R_CLK_T_WAKEUP_MASK (0x3FF << 22) 107 #define DSI_R_CLK_T_WAKEUP_SHIFT (22) 108 109 // reg_0c 110 #define DSI_R_DTYPE(n) (((n) & 0x3F) << 0) 111 #define DSI_R_DTYPE_MASK (0x3F << 0) 112 #define DSI_R_DTYPE_SHIFT (0) 113 #define DSI_R_VC_CH_ID(n) (((n) & 0x3) << 6) 114 #define DSI_R_VC_CH_ID_MASK (0x3 << 6) 115 #define DSI_R_VC_CH_ID_SHIFT (6) 116 #define DSI_R_VIDEO_PACKET_LENTH(n) (((n) & 0xFFFF) << 8) 117 #define DSI_R_VIDEO_PACKET_LENTH_MASK (0xFFFF << 8) 118 #define DSI_R_VIDEO_PACKET_LENTH_SHIFT (8) 119 #define DSI_R_INPUT_TYPE(n) (((n) & 0x3) << 24) 120 #define DSI_R_INPUT_TYPE_MASK (0x3 << 24) 121 #define DSI_R_INPUT_TYPE_SHIFT (24) 122 #define DSI_R_DLANE_AD_TIME(n) (((n) & 0x3F) << 26) 123 #define DSI_R_DLANE_AD_TIME_MASK (0x3F << 26) 124 #define DSI_R_DLANE_AD_TIME_SHIFT (26) 125 126 // reg_10 127 #define DSI_LPRX_DATA(n) (((n) & 0xFF) << 0) 128 #define DSI_LPRX_DATA_MASK (0xFF << 0) 129 #define DSI_LPRX_DATA_SHIFT (0) 130 #define DSI_LPRX_SIZE(n) (((n) & 0x1F) << 8) 131 #define DSI_LPRX_SIZE_MASK (0x1F << 8) 132 #define DSI_LPRX_SIZE_SHIFT (8) 133 #define DSI_HS_CMD_RD_EN (1 << 14) 134 #define DSI_LPRX_RD_EN (1 << 15) 135 #define DSI_CMD_DONE_FLAG (1 << 16) 136 #define DSI_BTA_DONE_FLAG (1 << 17) 137 #define DSI_BTA_FAIL_FLAG (1 << 18) 138 #define DSI_LP_RX_DONE_FLAG (1 << 19) 139 #define DSI_RX_ERR_FLAG (1 << 20) 140 #define DSI_LPCD_FLAG (1 << 21) 141 #define DSI_RX_TIMEOUT_FLAG (1 << 22) 142 #define DSI_TE_INTR (1 << 23) 143 #define DSI_INTR_MASK(n) (((n) & 0xFF) << 24) 144 #define DSI_INTR_MASK_MASK (0xFF << 24) 145 #define DSI_INTR_MASK_SHIFT (24) 146 147 // reg_14 148 #define DSI_CMD_TYPE(n) (((n) & 0x7) << 0) 149 #define DSI_CMD_TYPE_MASK (0x7 << 0) 150 #define DSI_CMD_TYPE_SHIFT (0) 151 #define DSI_FLUSH_CMD_PRE (1 << 3) 152 #define DSI_LP_CMD_VALID (1 << 4) 153 #define DSI_HS_CMD_VALID (1 << 5) 154 #define DSI_BTA_VALID (1 << 6) 155 #define DSI_ESC_CMD(n) (((n) & 0xFF) << 8) 156 #define DSI_ESC_CMD_MASK (0xFF << 8) 157 #define DSI_ESC_CMD_SHIFT (8) 158 #define DSI_R_SOFT_CMD_LENGTH(n) (((n) & 0xFFF) << 16) 159 #define DSI_R_SOFT_CMD_LENGTH_MASK (0xFFF << 16) 160 #define DSI_R_SOFT_CMD_LENGTH_SHIFT (16) 161 162 // reg_30 163 #define DSI_OV_FLAG (1 << 0) 164 #define DSI_UN_FLAG (1 << 1) 165 #define DSI_CTRL_STX(n) (((n) & 0x1F) << 8) 166 #define DSI_CTRL_STX_MASK (0x1F << 8) 167 #define DSI_CTRL_STX_SHIFT (8) 168 #define DSI_CTRL_ST(n) (((n) & 0xF) << 13) 169 #define DSI_CTRL_ST_MASK (0xF << 13) 170 #define DSI_CTRL_ST_SHIFT (13) 171 #define DSI_HS_CTRL_ST(n) (((n) & 0xF) << 17) 172 #define DSI_HS_CTRL_ST_MASK (0xF << 17) 173 #define DSI_HS_CTRL_ST_SHIFT (17) 174 175 // reg_40 176 #define DSI_R_HTOTAL(n) (((n) & 0xFFF) << 0) 177 #define DSI_R_HTOTAL_MASK (0xFFF << 0) 178 #define DSI_R_HTOTAL_SHIFT (0) 179 #define DSI_R_HSTART(n) (((n) & 0xFF) << 12) 180 #define DSI_R_HSTART_MASK (0xFF << 12) 181 #define DSI_R_HSTART_SHIFT (12) 182 #define DSI_R_HWIDTH(n) (((n) & 0xFFF) << 20) 183 #define DSI_R_HWIDTH_MASK (0xFFF << 20) 184 #define DSI_R_HWIDTH_SHIFT (20) 185 186 // reg_44 187 #define DSI_R_VTOTAL(n) (((n) & 0xFFF) << 0) 188 #define DSI_R_VTOTAL_MASK (0xFFF << 0) 189 #define DSI_R_VTOTAL_SHIFT (0) 190 #define DSI_R_VSTART(n) (((n) & 0xFF) << 12) 191 #define DSI_R_VSTART_MASK (0xFF << 12) 192 #define DSI_R_VSTART_SHIFT (12) 193 #define DSI_R_VHEIGHT(n) (((n) & 0xFFF) << 20) 194 #define DSI_R_VHEIGHT_MASK (0xFFF << 20) 195 #define DSI_R_VHEIGHT_SHIFT (20) 196 197 // reg_48 198 #define DSI_R_CL_DATA_SEL (1 << 0) 199 #define DSI_R_TE_EDGE_SEL (1 << 1) 200 #define DSI_R_VIDEO_SEL (1 << 2) 201 #define DSI_R_VIDEO_BIST_EN (1 << 3) 202 #define DSI_R_VIDEO_BIST_PATTERN(n) (((n) & 0x7) << 4) 203 #define DSI_R_VIDEO_BIST_PATTERN_MASK (0x7 << 4) 204 #define DSI_R_VIDEO_BIST_PATTERN_SHIFT (4) 205 #define DSI_R_COLOR_BAR_WIDTH(n) (((n) & 0xFFF) << 8) 206 #define DSI_R_COLOR_BAR_WIDTH_MASK (0xFFF << 8) 207 #define DSI_R_COLOR_BAR_WIDTH_SHIFT (8) 208 #define DSI_R_HSYNC_DLY_NUM(n) (((n) & 0xFFF) << 20) 209 #define DSI_R_HSYNC_DLY_NUM_MASK (0xFFF << 20) 210 #define DSI_R_HSYNC_DLY_NUM_SHIFT (20) 211 212 // reg_60 213 #define DSI_REG_CK_LB_HS(n) (((n) & 0xFF) << 0) 214 #define DSI_REG_CK_LB_HS_MASK (0xFF << 0) 215 #define DSI_REG_CK_LB_HS_SHIFT (0) 216 #define DSI_REG_CK_LB_ZERO(n) (((n) & 0xFF) << 8) 217 #define DSI_REG_CK_LB_ZERO_MASK (0xFF << 8) 218 #define DSI_REG_CK_LB_ZERO_SHIFT (8) 219 #define DSI_REG_CK_LB_PRPR(n) (((n) & 0xFF) << 16) 220 #define DSI_REG_CK_LB_PRPR_MASK (0xFF << 16) 221 #define DSI_REG_CK_LB_PRPR_SHIFT (16) 222 #define DSI_REG_CK_LB_RQST(n) (((n) & 0xFF) << 24) 223 #define DSI_REG_CK_LB_RQST_MASK (0xFF << 24) 224 #define DSI_REG_CK_LB_RQST_SHIFT (24) 225 226 // reg_64 227 #define DSI_REG_DATA_LB_ZERO(n) (((n) & 0xFF) << 0) 228 #define DSI_REG_DATA_LB_ZERO_MASK (0xFF << 0) 229 #define DSI_REG_DATA_LB_ZERO_SHIFT (0) 230 #define DSI_REG_DATA_LB_PRPR(n) (((n) & 0xFF) << 8) 231 #define DSI_REG_DATA_LB_PRPR_MASK (0xFF << 8) 232 #define DSI_REG_DATA_LB_PRPR_SHIFT (8) 233 #define DSI_REG_DATA_LB_RQST(n) (((n) & 0xFF) << 16) 234 #define DSI_REG_DATA_LB_RQST_MASK (0xFF << 16) 235 #define DSI_REG_DATA_LB_RQST_SHIFT (16) 236 #define DSI_REG_CK_LB_DATA_SEL (1 << 24) 237 #define DSI_REG_LOOPBACK_TEST (1 << 25) 238 239 // reg_74 240 #define DSI_R_HSW(n) (((n) & 0x7F) << 0) 241 #define DSI_R_HSW_MASK (0x7F << 0) 242 #define DSI_R_HSW_SHIFT (0) 243 #define DSI_R_VSW(n) (((n) & 0x7F) << 7) 244 #define DSI_R_VSW_MASK (0x7F << 7) 245 #define DSI_R_VSW_SHIFT (7) 246 #define DSI_R_HS_TRAIL_TIME2(n) (((n) & 0x3F) << 16) 247 #define DSI_R_HS_TRAIL_TIME2_MASK (0x3F << 16) 248 #define DSI_R_HS_TRAIL_TIME2_SHIFT (16) 249 250 #endif 251 252