1 /* 2 * Copyright (c) 2021 Bestechnic (Shanghai) Co., Ltd. All rights reserved. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 #ifndef __REG_PSRAM_MC_V2_H__ 16 #define __REG_PSRAM_MC_V2_H__ 17 18 #include "plat_types.h" 19 20 struct PSRAM_MC_T { 21 __IO uint32_t REG_000; 22 __IO uint32_t REG_004; 23 __IO uint32_t REG_008; 24 __IO uint32_t REG_00C; 25 __IO uint32_t REG_010; 26 __IO uint32_t REG_014; 27 __IO uint32_t REG_018; 28 __IO uint32_t REG_01C; 29 __IO uint32_t REG_020; 30 __IO uint32_t REG_024; 31 __IO uint32_t REG_028; 32 __IO uint32_t REG_02C; 33 __IO uint32_t REG_030; 34 __IO uint32_t REG_034; 35 __IO uint32_t REG_038; 36 __IO uint32_t REG_03C; 37 __IO uint32_t REG_040; 38 __IO uint32_t REG_044; 39 __IO uint32_t REG_048; 40 __IO uint32_t REG_04C; 41 __IO uint32_t REG_050; 42 __IO uint32_t REG_054; 43 __IO uint32_t REG_058; 44 __IO uint32_t REG_05C; 45 __IO uint32_t REG_060; 46 __IO uint32_t REG_064; 47 __IO uint32_t REG_068; 48 __IO uint32_t REG_06C; 49 __IO uint32_t REG_070; 50 __IO uint32_t REG_074; 51 __IO uint32_t REG_078; 52 __IO uint32_t REG_07C; 53 __IO uint32_t REG_080; 54 __IO uint32_t REG_084; 55 __IO uint32_t REG_088; 56 __IO uint32_t REG_08C; 57 __IO uint32_t REG_090; 58 __IO uint32_t REG_094; 59 __IO uint32_t REG_098; 60 __IO uint32_t REG_09C; 61 __IO uint32_t REG_0A0; 62 __IO uint32_t REG_0A4; 63 __IO uint32_t REG_0A8; 64 __IO uint32_t REG_0AC; 65 __IO uint32_t REG_0B0; 66 __IO uint32_t REG_0B4; 67 __IO uint32_t REG_0B8; 68 __IO uint32_t REG_0BC; 69 __IO uint32_t REG_RESERVED_0C0[0x20]; 70 __IO uint32_t REG_140; 71 __IO uint32_t REG_144; 72 __IO uint32_t REG_148; 73 __IO uint32_t REG_14C; 74 __IO uint32_t REG_150; 75 __IO uint32_t REG_154; 76 __IO uint32_t REG_158; 77 __IO uint32_t REG_15C; 78 __IO uint32_t REG_160; 79 __IO uint32_t REG_RESERVED_164[7]; 80 __IO uint32_t REG_180; 81 __IO uint32_t REG_184; 82 __IO uint32_t REG_188; 83 __IO uint32_t REG_18C; 84 __IO uint32_t REG_190; 85 __IO uint32_t REG_194; 86 __IO uint32_t REG_RESERVED_198[0x1A]; 87 __IO uint32_t REG_200; 88 __IO uint32_t REG_RESERVED_204[0x7F]; 89 __IO uint32_t REG_400; 90 __IO uint32_t REG_404; 91 __IO uint32_t REG_RESERVED_408[0xE]; 92 __IO uint32_t REG_440; 93 __IO uint32_t REG_444; 94 __IO uint32_t REG_448; 95 __IO uint32_t REG_44C; 96 __IO uint32_t REG_450; 97 __IO uint32_t REG_454; 98 __IO uint32_t REG_458; 99 __IO uint32_t REG_45C; 100 __IO uint32_t REG_460; 101 __IO uint32_t REG_464; 102 __IO uint32_t REG_468; 103 __IO uint32_t REG_46C; 104 }; 105 106 // reg_00 107 #define PSRAM_ULP_MC_CHIP_BIT (1 << 0) 108 #define PSRAM_ULP_MC_CHIP_TYPE (1 << 1) 109 #define PSRAM_ULP_MC_CHIP_X16 (1 << 2) 110 #define PSRAM_ULP_MC_CHIP_CA_PATTERN(n) (((n) & 0x7) << 3) 111 #define PSRAM_ULP_MC_CHIP_CA_PATTERN_MASK (0x7 << 3) 112 #define PSRAM_ULP_MC_CHIP_CA_PATTERN_SHIFT (3) 113 #define PSRAM_ULP_MC_CHIP_SWITCH (1 << 6) 114 #define PSRAM_ULP_MC_SQPI_MODE (1 << 7) 115 #define PSRAM_ULP_MC_QPI_MODE (1 << 8) 116 #define PSRAM_ULP_MC_OPI_MODE (1 << 9) 117 #define PSRAM_ULP_MC_DTR_MODE(n) (((n) & 0x7) << 10) 118 #define PSRAM_ULP_MC_DTR_MODE_MASK (0x7 << 10) 119 #define PSRAM_ULP_MC_DTR_MODE_SHIFT (10) 120 #define PSRAM_ULP_MC_DQS_MODE (1 << 13) 121 #define PSRAM_ULP_MC_LATENCY_TYPE (1 << 14) 122 #define PSRAM_ULP_MC_SQPI_CMD_SEQ_DEFINE_EN (1 << 15) 123 124 // reg_04 125 #define PSRAM_ULP_MC_MGR_CMD(n) (((n) & 0xFF) << 0) 126 #define PSRAM_ULP_MC_MGR_CMD_MASK (0xFF << 0) 127 #define PSRAM_ULP_MC_MGR_CMD_SHIFT (0) 128 129 // reg_08 130 #define PSRAM_ULP_MC_MGR_ADDR(n) (((n) & 0xFFFFFFFF) << 0) 131 #define PSRAM_ULP_MC_MGR_ADDR_MASK (0xFFFFFFFF << 0) 132 #define PSRAM_ULP_MC_MGR_ADDR_SHIFT (0) 133 134 // reg_0c 135 #define PSRAM_ULP_MC_MGR_LEN(n) (((n) & 0xFF) << 0) 136 #define PSRAM_ULP_MC_MGR_LEN_MASK (0xFF << 0) 137 #define PSRAM_ULP_MC_MGR_LEN_SHIFT (0) 138 #define PSRAM_ULP_MC_MGR_LEN_BYPASS (1 << 8) 139 140 // reg_10 141 #define PSRAM_ULP_MC_MGR_WSTRB(n) (((n) & 0xFF) << 0) 142 #define PSRAM_ULP_MC_MGR_WSTRB_MASK (0xFF << 0) 143 #define PSRAM_ULP_MC_MGR_WSTRB_SHIFT (0) 144 145 // reg_14 146 #define PSRAM_ULP_MC_MGR_TX_FIFO(n) (((n) & 0xFFFFFFFF) << 0) 147 #define PSRAM_ULP_MC_MGR_TX_FIFO_MASK (0xFFFFFFFF << 0) 148 #define PSRAM_ULP_MC_MGR_TX_FIFO_SHIFT (0) 149 150 // reg_18 151 #define PSRAM_ULP_MC_MGR_RX_FIFO(n) (((n) & 0xFFFFFFFF) << 0) 152 #define PSRAM_ULP_MC_MGR_RX_FIFO_MASK (0xFFFFFFFF << 0) 153 #define PSRAM_ULP_MC_MGR_RX_FIFO_SHIFT (0) 154 155 // reg_1c 156 #define PSRAM_ULP_MC_MGR_TX_FIFO_CLR (1 << 0) 157 #define PSRAM_ULP_MC_MGR_RX_FIFO_CLR (1 << 1) 158 159 // reg_20 160 #define PSRAM_ULP_MC_REFRESH_MODE (1 << 0) 161 #define PSRAM_ULP_MC_BURST_REFRESH_EN (1 << 1) 162 163 // reg_24 164 #define PSRAM_ULP_MC_ENTRY_SLEEP_IDLE (1 << 0) 165 #define PSRAM_ULP_MC_ENTRY_SELF_REFRESH_IDLE (1 << 1) 166 #define PSRAM_ULP_MC_STOP_CLK_IDLE (1 << 2) 167 #define PSRAM_ULP_MC_AUTOWAKEUP_EN (1 << 3) 168 #define PSRAM_ULP_MC_RES_7_4_REG24(n) (((n) & 0xF) << 4) 169 #define PSRAM_ULP_MC_RES_7_4_REG24_MASK (0xF << 4) 170 #define PSRAM_ULP_MC_RES_7_4_REG24_SHIFT (4) 171 #define PSRAM_ULP_MC_PD_MR(n) (((n) & 0xFF) << 8) 172 #define PSRAM_ULP_MC_PD_MR_MASK (0xFF << 8) 173 #define PSRAM_ULP_MC_PD_MR_SHIFT (8) 174 #define PSRAM_ULP_MC_PD_CMD(n) (((n) & 0xFF) << 16) 175 #define PSRAM_ULP_MC_PD_CMD_MASK (0xFF << 16) 176 #define PSRAM_ULP_MC_PD_CMD_SHIFT (16) 177 178 // reg_28 179 #define PSRAM_ULP_MC_WRITE_LATENCY(n) (((n) & 0xFF) << 0) 180 #define PSRAM_ULP_MC_WRITE_LATENCY_MASK (0xFF << 0) 181 #define PSRAM_ULP_MC_WRITE_LATENCY_SHIFT (0) 182 183 // reg_2c 184 #define PSRAM_ULP_MC_READ_LATENCY(n) (((n) & 0xFF) << 0) 185 #define PSRAM_ULP_MC_READ_LATENCY_MASK (0xFF << 0) 186 #define PSRAM_ULP_MC_READ_LATENCY_SHIFT (0) 187 188 // reg_30 189 #define PSRAM_ULP_MC_MEMORY_WIDTH(n) (((n) & 0x3) << 0) 190 #define PSRAM_ULP_MC_MEMORY_WIDTH_MASK (0x3 << 0) 191 #define PSRAM_ULP_MC_MEMORY_WIDTH_SHIFT (0) 192 193 // reg_34 194 #define PSRAM_ULP_MC_BURST_LENGTH(n) (((n) & 0x7) << 0) 195 #define PSRAM_ULP_MC_BURST_LENGTH_MASK (0x7 << 0) 196 #define PSRAM_ULP_MC_BURST_LENGTH_SHIFT (0) 197 #define PSRAM_ULP_MC_RES_3_3_REG34 (1 << 3) 198 #define PSRAM_ULP_MC_PAGE_BOUNDARY(n) (((n) & 0x3) << 4) 199 #define PSRAM_ULP_MC_PAGE_BOUNDARY_MASK (0x3 << 4) 200 #define PSRAM_ULP_MC_PAGE_BOUNDARY_SHIFT (4) 201 #define PSRAM_ULP_MC_CMD_ENTER_QUAD(n) (((n) & 0xFF) << 6) 202 #define PSRAM_ULP_MC_CMD_ENTER_QUAD_MASK (0xFF << 6) 203 #define PSRAM_ULP_MC_CMD_ENTER_QUAD_SHIFT (6) 204 #define PSRAM_ULP_MC_CMD_EXIT_QUAD(n) (((n) & 0xFF) << 14) 205 #define PSRAM_ULP_MC_CMD_EXIT_QUAD_MASK (0xFF << 14) 206 #define PSRAM_ULP_MC_CMD_EXIT_QUAD_SHIFT (14) 207 208 // reg_38 209 #define PSRAM_ULP_MC_BUS_WIDTH (1 << 0) 210 211 // reg_3c 212 #define PSRAM_ULP_MC_HIGH_PRI_LEVEL(n) (((n) & 0x1F) << 0) 213 #define PSRAM_ULP_MC_HIGH_PRI_LEVEL_MASK (0x1F << 0) 214 #define PSRAM_ULP_MC_HIGH_PRI_LEVEL_SHIFT (0) 215 216 // reg_40 217 #define PSRAM_ULP_MC_CP_WRAP_EN (1 << 0) 218 #define PSRAM_ULP_MC_AUTO_PRECHARGE (1 << 1) 219 #define PSRAM_ULP_MC_WRAP_CRT_RET_EN (1 << 2) 220 #define PSRAM_ULP_MC_CROSS_BOUNDARY_EN (1 << 3) 221 #define PSRAM_ULP_MC_TOGGLE_BURST_LEN_EN (1 << 4) 222 #define PSRAM_ULP_MC_TOGGLE_BURST_LEN_SET(n) (((n) & 0x7) << 5) 223 #define PSRAM_ULP_MC_TOGGLE_BURST_LEN_SET_MASK (0x7 << 5) 224 #define PSRAM_ULP_MC_TOGGLE_BURST_LEN_SET_SHIFT (5) 225 #define PSRAM_ULP_MC_TOGGLE_BURST_LEN_CMD(n) (((n) & 0xFF) << 8) 226 #define PSRAM_ULP_MC_TOGGLE_BURST_LEN_CMD_MASK (0xFF << 8) 227 #define PSRAM_ULP_MC_TOGGLE_BURST_LEN_CMD_SHIFT (8) 228 #define PSRAM_ULP_MC_TOGGLE_WRAP_EN (1 << 16) 229 #define PSRAM_ULP_MC_TOGGLE_WRAP_SET (1 << 17) 230 231 // reg_44 232 #define PSRAM_ULP_MC_WB_DRAIN (1 << 0) 233 #define PSRAM_ULP_MC_WB_INVALID (1 << 1) 234 #define PSRAM_ULP_MC_RB_INVALID (1 << 2) 235 #define PSRAM_ULP_MC_SNP_DISABLE (1 << 3) 236 #define PSRAM_ULP_MC_BUFFERABLE_WB_EN (1 << 4) 237 #define PSRAM_ULP_MC_RD_CANCEL_EN (1 << 5) 238 239 // reg_48 240 #define PSRAM_ULP_MC_FRE_RATIO(n) (((n) & 0x3) << 0) 241 #define PSRAM_ULP_MC_FRE_RATIO_MASK (0x3 << 0) 242 #define PSRAM_ULP_MC_FRE_RATIO_SHIFT (0) 243 244 // reg_4c 245 #define PSRAM_ULP_MC_T_REFI(n) (((n) & 0xFFFF) << 0) 246 #define PSRAM_ULP_MC_T_REFI_MASK (0xFFFF << 0) 247 #define PSRAM_ULP_MC_T_REFI_SHIFT (0) 248 #define PSRAM_ULP_MC_NUM_OF_BURST_RFS(n) (((n) & 0xFFFF) << 16) 249 #define PSRAM_ULP_MC_NUM_OF_BURST_RFS_MASK (0xFFFF << 16) 250 #define PSRAM_ULP_MC_NUM_OF_BURST_RFS_SHIFT (16) 251 252 // reg_50 253 #define PSRAM_ULP_MC_T_RC(n) (((n) & 0xFF) << 0) 254 #define PSRAM_ULP_MC_T_RC_MASK (0xFF << 0) 255 #define PSRAM_ULP_MC_T_RC_SHIFT (0) 256 257 // reg_54 258 #define PSRAM_ULP_MC_T_RFC(n) (((n) & 0xFF) << 0) 259 #define PSRAM_ULP_MC_T_RFC_MASK (0xFF << 0) 260 #define PSRAM_ULP_MC_T_RFC_SHIFT (0) 261 262 // reg_58 263 #define PSRAM_ULP_MC_T_CPHR(n) (((n) & 0x3F) << 0) 264 #define PSRAM_ULP_MC_T_CPHR_MASK (0x3F << 0) 265 #define PSRAM_ULP_MC_T_CPHR_SHIFT (0) 266 267 // reg_5c 268 #define PSRAM_ULP_MC_T_CPHR_AP(n) (((n) & 0x3F) << 0) 269 #define PSRAM_ULP_MC_T_CPHR_AP_MASK (0x3F << 0) 270 #define PSRAM_ULP_MC_T_CPHR_AP_SHIFT (0) 271 272 // reg_60 273 #define PSRAM_ULP_MC_T_CPHW(n) (((n) & 0x3F) << 0) 274 #define PSRAM_ULP_MC_T_CPHW_MASK (0x3F << 0) 275 #define PSRAM_ULP_MC_T_CPHW_SHIFT (0) 276 277 // reg_64 278 #define PSRAM_ULP_MC_T_CPHW_AP(n) (((n) & 0x3F) << 0) 279 #define PSRAM_ULP_MC_T_CPHW_AP_MASK (0x3F << 0) 280 #define PSRAM_ULP_MC_T_CPHW_AP_SHIFT (0) 281 282 // reg_68 283 #define PSRAM_ULP_MC_T_MRR(n) (((n) & 0x3F) << 0) 284 #define PSRAM_ULP_MC_T_MRR_MASK (0x3F << 0) 285 #define PSRAM_ULP_MC_T_MRR_SHIFT (0) 286 287 // reg_6c 288 #define PSRAM_ULP_MC_T_MRS(n) (((n) & 0x3F) << 0) 289 #define PSRAM_ULP_MC_T_MRS_MASK (0x3F << 0) 290 #define PSRAM_ULP_MC_T_MRS_SHIFT (0) 291 292 // reg_70 293 #define PSRAM_ULP_MC_T_CEM(n) (((n) & 0xFFFF) << 0) 294 #define PSRAM_ULP_MC_T_CEM_MASK (0xFFFF << 0) 295 #define PSRAM_ULP_MC_T_CEM_SHIFT (0) 296 297 // reg_74 298 #define PSRAM_ULP_MC_T_RST(n) (((n) & 0xFFFF) << 0) 299 #define PSRAM_ULP_MC_T_RST_MASK (0xFFFF << 0) 300 #define PSRAM_ULP_MC_T_RST_SHIFT (0) 301 302 // reg_78 303 #define PSRAM_ULP_MC_T_SRF(n) (((n) & 0xFF) << 0) 304 #define PSRAM_ULP_MC_T_SRF_MASK (0xFF << 0) 305 #define PSRAM_ULP_MC_T_SRF_SHIFT (0) 306 307 // reg_7c 308 #define PSRAM_ULP_MC_T_XSR(n) (((n) & 0xFF) << 0) 309 #define PSRAM_ULP_MC_T_XSR_MASK (0xFF << 0) 310 #define PSRAM_ULP_MC_T_XSR_SHIFT (0) 311 312 // reg_80 313 #define PSRAM_ULP_MC_T_HS(n) (((n) & 0xFFFF) << 0) 314 #define PSRAM_ULP_MC_T_HS_MASK (0xFFFF << 0) 315 #define PSRAM_ULP_MC_T_HS_SHIFT (0) 316 317 // reg_84 318 #define PSRAM_ULP_MC_T_XPHS(n) (((n) & 0xFF) << 0) 319 #define PSRAM_ULP_MC_T_XPHS_MASK (0xFF << 0) 320 #define PSRAM_ULP_MC_T_XPHS_SHIFT (0) 321 322 // reg_88 323 #define PSRAM_ULP_MC_T_XHS(n) (((n) & 0xFFFFF) << 0) 324 #define PSRAM_ULP_MC_T_XHS_MASK (0xFFFFF << 0) 325 #define PSRAM_ULP_MC_T_XHS_SHIFT (0) 326 327 // reg_8c 328 #define PSRAM_ULP_MC_T_ZQCAL(n) (((n) & 0xFFFFF) << 0) 329 #define PSRAM_ULP_MC_T_ZQCAL_MASK (0xFFFFF << 0) 330 #define PSRAM_ULP_MC_T_ZQCAL_SHIFT (0) 331 332 // reg_90 333 #define PSRAM_ULP_MC_T_ZQCRST(n) (((n) & 0xFFFFF) << 0) 334 #define PSRAM_ULP_MC_T_ZQCRST_MASK (0xFFFFF << 0) 335 #define PSRAM_ULP_MC_T_ZQCRST_SHIFT (0) 336 337 // reg_94 338 #define PSRAM_ULP_MC_T_XCKD(n) (((n) & 0x3F) << 0) 339 #define PSRAM_ULP_MC_T_XCKD_MASK (0x3F << 0) 340 #define PSRAM_ULP_MC_T_XCKD_SHIFT (0) 341 342 // reg_98 343 #define PSRAM_ULP_MC_T_ECKD(n) (((n) & 0x3F) << 0) 344 #define PSRAM_ULP_MC_T_ECKD_MASK (0x3F << 0) 345 #define PSRAM_ULP_MC_T_ECKD_SHIFT (0) 346 347 // reg_9c 348 #define PSRAM_ULP_MC_WR_DMY_CYC(n) (((n) & 0xFF) << 0) 349 #define PSRAM_ULP_MC_WR_DMY_CYC_MASK (0xFF << 0) 350 #define PSRAM_ULP_MC_WR_DMY_CYC_SHIFT (0) 351 352 // reg_a0 353 #define PSRAM_ULP_MC_STOP_CLK_IN_NOP (1 << 0) 354 #define PSRAM_ULP_MC_NOP_DMY_CYC(n) (((n) & 0xFF) << 1) 355 #define PSRAM_ULP_MC_NOP_DMY_CYC_MASK (0xFF << 1) 356 #define PSRAM_ULP_MC_NOP_DMY_CYC_SHIFT (1) 357 #define PSRAM_ULP_MC_STOP_CLK_IN_TCPH (1 << 9) 358 359 // reg_a4 360 #define PSRAM_ULP_MC_QUEUE_IDLE_CYCLE(n) (((n) & 0xFFFFFFFF) << 0) 361 #define PSRAM_ULP_MC_QUEUE_IDLE_CYCLE_MASK (0xFFFFFFFF << 0) 362 #define PSRAM_ULP_MC_QUEUE_IDLE_CYCLE_SHIFT (0) 363 364 // reg_a8 365 #define PSRAM_ULP_MC_T_EXPANDRD(n) (((n) & 0x3F) << 0) 366 #define PSRAM_ULP_MC_T_EXPANDRD_MASK (0x3F << 0) 367 #define PSRAM_ULP_MC_T_EXPANDRD_SHIFT (0) 368 369 // reg_ac 370 #define PSRAM_ULP_MC_RX_SYNC_BYPASS (1 << 0) 371 372 // reg_b4 373 #define PSRAM_ULP_MC_T_ZQCAS(n) (((n) & 0xFFFFF) << 0) 374 #define PSRAM_ULP_MC_T_ZQCAS_MASK (0xFFFFF << 0) 375 #define PSRAM_ULP_MC_T_ZQCAS_SHIFT (0) 376 377 // reg_b8 378 #define PSRAM_ULP_MC_T_NEW_HOLD(n) (((n) & 0xFFFFFFFF) << 0) 379 #define PSRAM_ULP_MC_T_NEW_HOLD_MASK (0xFFFFFFFF << 0) 380 #define PSRAM_ULP_MC_T_NEW_HOLD_SHIFT (0) 381 382 // reg_bc 383 #define PSRAM_ULP_MC_NEW_CMD_OP(n) (((n) & 0x7) << 0) 384 #define PSRAM_ULP_MC_NEW_CMD_OP_MASK (0x7 << 0) 385 #define PSRAM_ULP_MC_NEW_CMD_OP_SHIFT (0) 386 387 // reg_c0 388 #define PSRAM_ULP_MC_T_REF_WIN(n) (((n) & 0xFFFFFFFF) << 0) 389 #define PSRAM_ULP_MC_T_REF_WIN_MASK (0xFFFFFFFF << 0) 390 #define PSRAM_ULP_MC_T_REF_WIN_SHIFT (0) 391 392 // reg_140 393 #define PSRAM_ULP_MC_CMD_TABLE_ARRAY_RD(n) (((n) & 0xFF) << 0) 394 #define PSRAM_ULP_MC_CMD_TABLE_ARRAY_RD_MASK (0xFF << 0) 395 #define PSRAM_ULP_MC_CMD_TABLE_ARRAY_RD_SHIFT (0) 396 397 // reg_144 398 #define PSRAM_ULP_MC_CMD_TABLE_ARRAY_WR(n) (((n) & 0xFF) << 0) 399 #define PSRAM_ULP_MC_CMD_TABLE_ARRAY_WR_MASK (0xFF << 0) 400 #define PSRAM_ULP_MC_CMD_TABLE_ARRAY_WR_SHIFT (0) 401 402 // reg_148 403 #define PSRAM_ULP_MC_CMD_TABLE_REG_RD(n) (((n) & 0xFF) << 0) 404 #define PSRAM_ULP_MC_CMD_TABLE_REG_RD_MASK (0xFF << 0) 405 #define PSRAM_ULP_MC_CMD_TABLE_REG_RD_SHIFT (0) 406 407 // reg_14c 408 #define PSRAM_ULP_MC_CMD_TABLE_REG_WR(n) (((n) & 0xFF) << 0) 409 #define PSRAM_ULP_MC_CMD_TABLE_REG_WR_MASK (0xFF << 0) 410 #define PSRAM_ULP_MC_CMD_TABLE_REG_WR_SHIFT (0) 411 412 // reg_150 413 #define PSRAM_ULP_MC_CMD_TABLE_AUTO_REFR(n) (((n) & 0xFF) << 0) 414 #define PSRAM_ULP_MC_CMD_TABLE_AUTO_REFR_MASK (0xFF << 0) 415 #define PSRAM_ULP_MC_CMD_TABLE_AUTO_REFR_SHIFT (0) 416 417 // reg_154 418 #define PSRAM_ULP_MC_CMD_TABLE_SELF_REFR(n) (((n) & 0xFF) << 0) 419 #define PSRAM_ULP_MC_CMD_TABLE_SELF_REFR_MASK (0xFF << 0) 420 #define PSRAM_ULP_MC_CMD_TABLE_SELF_REFR_SHIFT (0) 421 422 // reg_158 423 #define PSRAM_ULP_MC_CMD_TABLE_HSLP_ENTRY(n) (((n) & 0xFF) << 0) 424 #define PSRAM_ULP_MC_CMD_TABLE_HSLP_ENTRY_MASK (0xFF << 0) 425 #define PSRAM_ULP_MC_CMD_TABLE_HSLP_ENTRY_SHIFT (0) 426 427 // reg_15c 428 #define PSRAM_ULP_MC_CMD_TABLE_GLBRST(n) (((n) & 0xFF) << 0) 429 #define PSRAM_ULP_MC_CMD_TABLE_GLBRST_MASK (0xFF << 0) 430 #define PSRAM_ULP_MC_CMD_TABLE_GLBRST_SHIFT (0) 431 432 // reg_160 433 #define PSRAM_ULP_MC_CMD_TABLE_NOP(n) (((n) & 0xFF) << 0) 434 #define PSRAM_ULP_MC_CMD_TABLE_NOP_MASK (0xFF << 0) 435 #define PSRAM_ULP_MC_CMD_TABLE_NOP_SHIFT (0) 436 437 // reg_164 438 #define PSRAM_ULP_MC_CMD_TABLE_ORDER(n) (((n) & 0xFF) << 0) 439 #define PSRAM_ULP_MC_CMD_TABLE_ORDER_MASK (0xFF << 0) 440 #define PSRAM_ULP_MC_CMD_TABLE_ORDER_SHIFT (0) 441 442 // reg_168 443 #define PSRAM_ULP_MC_CMD_SEQ_DEFINE0(n) (((n) & 0x3FFFFFFF) << 0) 444 #define PSRAM_ULP_MC_CMD_SEQ_DEFINE0_MASK (0x3FFFFFFF << 0) 445 #define PSRAM_ULP_MC_CMD_SEQ_DEFINE0_SHIFT (0) 446 447 // reg_16c 448 #define PSRAM_ULP_MC_CMD_SEQ_DEFINE1(n) (((n) & 0x3FF) << 0) 449 #define PSRAM_ULP_MC_CMD_SEQ_DEFINE1_MASK (0x3FF << 0) 450 #define PSRAM_ULP_MC_CMD_SEQ_DEFINE1_SHIFT (0) 451 452 // reg_180 453 #define PSRAM_ULP_MC_CA_MAP_BIT0(n) (((n) & 0x1F) << 0) 454 #define PSRAM_ULP_MC_CA_MAP_BIT0_MASK (0x1F << 0) 455 #define PSRAM_ULP_MC_CA_MAP_BIT0_SHIFT (0) 456 #define PSRAM_ULP_MC_CA_MAP_BIT1(n) (((n) & 0x1F) << 5) 457 #define PSRAM_ULP_MC_CA_MAP_BIT1_MASK (0x1F << 5) 458 #define PSRAM_ULP_MC_CA_MAP_BIT1_SHIFT (5) 459 #define PSRAM_ULP_MC_CA_MAP_BIT2(n) (((n) & 0x1F) << 10) 460 #define PSRAM_ULP_MC_CA_MAP_BIT2_MASK (0x1F << 10) 461 #define PSRAM_ULP_MC_CA_MAP_BIT2_SHIFT (10) 462 #define PSRAM_ULP_MC_CA_MAP_BIT3(n) (((n) & 0x1F) << 15) 463 #define PSRAM_ULP_MC_CA_MAP_BIT3_MASK (0x1F << 15) 464 #define PSRAM_ULP_MC_CA_MAP_BIT3_SHIFT (15) 465 #define PSRAM_ULP_MC_CA_MAP_BIT4(n) (((n) & 0x1F) << 20) 466 #define PSRAM_ULP_MC_CA_MAP_BIT4_MASK (0x1F << 20) 467 #define PSRAM_ULP_MC_CA_MAP_BIT4_SHIFT (20) 468 #define PSRAM_ULP_MC_CA_MAP_BIT5(n) (((n) & 0x1F) << 25) 469 #define PSRAM_ULP_MC_CA_MAP_BIT5_MASK (0x1F << 25) 470 #define PSRAM_ULP_MC_CA_MAP_BIT5_SHIFT (25) 471 472 // reg_184 473 #define PSRAM_ULP_MC_CA_MAP_BIT6(n) (((n) & 0x1F) << 0) 474 #define PSRAM_ULP_MC_CA_MAP_BIT6_MASK (0x1F << 0) 475 #define PSRAM_ULP_MC_CA_MAP_BIT6_SHIFT (0) 476 #define PSRAM_ULP_MC_CA_MAP_BIT7(n) (((n) & 0x1F) << 5) 477 #define PSRAM_ULP_MC_CA_MAP_BIT7_MASK (0x1F << 5) 478 #define PSRAM_ULP_MC_CA_MAP_BIT7_SHIFT (5) 479 #define PSRAM_ULP_MC_CA_MAP_BIT8(n) (((n) & 0x1F) << 10) 480 #define PSRAM_ULP_MC_CA_MAP_BIT8_MASK (0x1F << 10) 481 #define PSRAM_ULP_MC_CA_MAP_BIT8_SHIFT (10) 482 #define PSRAM_ULP_MC_CA_MAP_BIT9(n) (((n) & 0x1F) << 15) 483 #define PSRAM_ULP_MC_CA_MAP_BIT9_MASK (0x1F << 15) 484 #define PSRAM_ULP_MC_CA_MAP_BIT9_SHIFT (15) 485 #define PSRAM_ULP_MC_CA_MAP_BIT10(n) (((n) & 0x1F) << 20) 486 #define PSRAM_ULP_MC_CA_MAP_BIT10_MASK (0x1F << 20) 487 #define PSRAM_ULP_MC_CA_MAP_BIT10_SHIFT (20) 488 #define PSRAM_ULP_MC_CA_MAP_BIT11(n) (((n) & 0x1F) << 25) 489 #define PSRAM_ULP_MC_CA_MAP_BIT11_MASK (0x1F << 25) 490 #define PSRAM_ULP_MC_CA_MAP_BIT11_SHIFT (25) 491 492 // reg_188 493 #define PSRAM_ULP_MC_CA_MAP_BIT12(n) (((n) & 0x1F) << 0) 494 #define PSRAM_ULP_MC_CA_MAP_BIT12_MASK (0x1F << 0) 495 #define PSRAM_ULP_MC_CA_MAP_BIT12_SHIFT (0) 496 #define PSRAM_ULP_MC_CA_MAP_BIT13(n) (((n) & 0x1F) << 5) 497 #define PSRAM_ULP_MC_CA_MAP_BIT13_MASK (0x1F << 5) 498 #define PSRAM_ULP_MC_CA_MAP_BIT13_SHIFT (5) 499 #define PSRAM_ULP_MC_CA_MAP_BIT14(n) (((n) & 0x1F) << 10) 500 #define PSRAM_ULP_MC_CA_MAP_BIT14_MASK (0x1F << 10) 501 #define PSRAM_ULP_MC_CA_MAP_BIT14_SHIFT (10) 502 #define PSRAM_ULP_MC_CA_MAP_BIT15(n) (((n) & 0x1F) << 15) 503 #define PSRAM_ULP_MC_CA_MAP_BIT15_MASK (0x1F << 15) 504 #define PSRAM_ULP_MC_CA_MAP_BIT15_SHIFT (15) 505 #define PSRAM_ULP_MC_CA_MAP_BIT16(n) (((n) & 0x1F) << 20) 506 #define PSRAM_ULP_MC_CA_MAP_BIT16_MASK (0x1F << 20) 507 #define PSRAM_ULP_MC_CA_MAP_BIT16_SHIFT (20) 508 #define PSRAM_ULP_MC_CA_MAP_BIT17(n) (((n) & 0x1F) << 25) 509 #define PSRAM_ULP_MC_CA_MAP_BIT17_MASK (0x1F << 25) 510 #define PSRAM_ULP_MC_CA_MAP_BIT17_SHIFT (25) 511 512 // reg_18c 513 #define PSRAM_ULP_MC_CA_MAP_BIT18(n) (((n) & 0x1F) << 0) 514 #define PSRAM_ULP_MC_CA_MAP_BIT18_MASK (0x1F << 0) 515 #define PSRAM_ULP_MC_CA_MAP_BIT18_SHIFT (0) 516 #define PSRAM_ULP_MC_CA_MAP_BIT19(n) (((n) & 0x1F) << 5) 517 #define PSRAM_ULP_MC_CA_MAP_BIT19_MASK (0x1F << 5) 518 #define PSRAM_ULP_MC_CA_MAP_BIT19_SHIFT (5) 519 #define PSRAM_ULP_MC_CA_MAP_BIT20(n) (((n) & 0x1F) << 10) 520 #define PSRAM_ULP_MC_CA_MAP_BIT20_MASK (0x1F << 10) 521 #define PSRAM_ULP_MC_CA_MAP_BIT20_SHIFT (10) 522 #define PSRAM_ULP_MC_CA_MAP_BIT21(n) (((n) & 0x1F) << 15) 523 #define PSRAM_ULP_MC_CA_MAP_BIT21_MASK (0x1F << 15) 524 #define PSRAM_ULP_MC_CA_MAP_BIT21_SHIFT (15) 525 #define PSRAM_ULP_MC_CA_MAP_BIT22(n) (((n) & 0x1F) << 20) 526 #define PSRAM_ULP_MC_CA_MAP_BIT22_MASK (0x1F << 20) 527 #define PSRAM_ULP_MC_CA_MAP_BIT22_SHIFT (20) 528 #define PSRAM_ULP_MC_CA_MAP_BIT23(n) (((n) & 0x1F) << 25) 529 #define PSRAM_ULP_MC_CA_MAP_BIT23_MASK (0x1F << 25) 530 #define PSRAM_ULP_MC_CA_MAP_BIT23_SHIFT (25) 531 532 // reg_190 533 #define PSRAM_ULP_MC_CA_MAP_BIT24(n) (((n) & 0x1F) << 0) 534 #define PSRAM_ULP_MC_CA_MAP_BIT24_MASK (0x1F << 0) 535 #define PSRAM_ULP_MC_CA_MAP_BIT24_SHIFT (0) 536 #define PSRAM_ULP_MC_CA_MAP_BIT25(n) (((n) & 0x1F) << 5) 537 #define PSRAM_ULP_MC_CA_MAP_BIT25_MASK (0x1F << 5) 538 #define PSRAM_ULP_MC_CA_MAP_BIT25_SHIFT (5) 539 #define PSRAM_ULP_MC_CA_MAP_BIT26(n) (((n) & 0x1F) << 10) 540 #define PSRAM_ULP_MC_CA_MAP_BIT26_MASK (0x1F << 10) 541 #define PSRAM_ULP_MC_CA_MAP_BIT26_SHIFT (10) 542 #define PSRAM_ULP_MC_CA_MAP_BIT27(n) (((n) & 0x1F) << 15) 543 #define PSRAM_ULP_MC_CA_MAP_BIT27_MASK (0x1F << 15) 544 #define PSRAM_ULP_MC_CA_MAP_BIT27_SHIFT (15) 545 #define PSRAM_ULP_MC_CA_MAP_BIT28(n) (((n) & 0x1F) << 20) 546 #define PSRAM_ULP_MC_CA_MAP_BIT28_MASK (0x1F << 20) 547 #define PSRAM_ULP_MC_CA_MAP_BIT28_SHIFT (20) 548 #define PSRAM_ULP_MC_CA_MAP_BIT29(n) (((n) & 0x1F) << 25) 549 #define PSRAM_ULP_MC_CA_MAP_BIT29_MASK (0x1F << 25) 550 #define PSRAM_ULP_MC_CA_MAP_BIT29_SHIFT (25) 551 552 // reg_194 553 #define PSRAM_ULP_MC_CA_MAP_BIT30(n) (((n) & 0x1F) << 0) 554 #define PSRAM_ULP_MC_CA_MAP_BIT30_MASK (0x1F << 0) 555 #define PSRAM_ULP_MC_CA_MAP_BIT30_SHIFT (0) 556 #define PSRAM_ULP_MC_CA_MAP_BIT31(n) (((n) & 0x1F) << 5) 557 #define PSRAM_ULP_MC_CA_MAP_BIT31_MASK (0x1F << 5) 558 #define PSRAM_ULP_MC_CA_MAP_BIT31_SHIFT (5) 559 #define PSRAM_ULP_MC_CA_MAP_BIT32(n) (((n) & 0x1F) << 10) 560 #define PSRAM_ULP_MC_CA_MAP_BIT32_MASK (0x1F << 10) 561 #define PSRAM_ULP_MC_CA_MAP_BIT32_SHIFT (10) 562 563 // reg_190 564 565 // reg_200 566 #define PSRAM_ULP_MC_RESERVED_0(n) (((n) & 0xFF) << 0) 567 #define PSRAM_ULP_MC_RESERVED_0_MASK (0xFF << 0) 568 #define PSRAM_ULP_MC_RESERVED_0_SHIFT (0) 569 570 // reg_400 571 #define PSRAM_ULP_MC_INIT_COMPLETE (1 << 0) 572 573 // reg_404 574 #define PSRAM_ULP_MC_BUSY (1 << 0) 575 #define PSRAM_ULP_MC_MGR_RXFIFO_R_EMPTY (1 << 1) 576 #define PSRAM_ULP_MC_MGR_RXFIFO_FULL_CNT(n) (((n) & 0xF) << 2) 577 #define PSRAM_ULP_MC_MGR_RXFIFO_FULL_CNT_MASK (0xF << 2) 578 #define PSRAM_ULP_MC_MGR_RXFIFO_FULL_CNT_SHIFT (2) 579 #define PSRAM_ULP_MC_MGR_TXFIFO_W_FULL (1 << 6) 580 #define PSRAM_ULP_MC_MGR_TXFIFO_EMPTY_CNT(n) (((n) & 0xF) << 7) 581 #define PSRAM_ULP_MC_MGR_TXFIFO_EMPTY_CNT_MASK (0xF << 7) 582 #define PSRAM_ULP_MC_MGR_TXFIFO_EMPTY_CNT_SHIFT (7) 583 #define PSRAM_ULP_MC_WB_FILL_LEVEL(n) (((n) & 0x1F) << 11) 584 #define PSRAM_ULP_MC_WB_FILL_LEVEL_MASK (0x1F << 11) 585 #define PSRAM_ULP_MC_WB_FILL_LEVEL_SHIFT (11) 586 #define PSRAM_ULP_MC_CP_FSM_STATE(n) (((n) & 0xF) << 16) 587 #define PSRAM_ULP_MC_CP_FSM_STATE_MASK (0xF << 16) 588 #define PSRAM_ULP_MC_CP_FSM_STATE_SHIFT (16) 589 #define PSRAM_ULP_MC_RD_FSM(n) (((n) & 0x3) << 20) 590 #define PSRAM_ULP_MC_RD_FSM_MASK (0x3 << 20) 591 #define PSRAM_ULP_MC_RD_FSM_SHIFT (20) 592 593 // reg_440 594 #define PSRAM_ULP_MC_PMU_MONITOR_START (1 << 0) 595 #define PSRAM_ULP_MC_PMU_MONITOR_END (1 << 1) 596 597 // reg_444 598 #define PSRAM_ULP_MC_PMU_TOL_MON_CLK_CYCLE0(n) (((n) & 0xFFFFFFFF) << 0) 599 #define PSRAM_ULP_MC_PMU_TOL_MON_CLK_CYCLE0_MASK (0xFFFFFFFF << 0) 600 #define PSRAM_ULP_MC_PMU_TOL_MON_CLK_CYCLE0_SHIFT (0) 601 602 // reg_448 603 #define PSRAM_ULP_MC_PMU_TOL_MON_CLK_CYCLE1(n) (((n) & 0xFFFFFFFF) << 0) 604 #define PSRAM_ULP_MC_PMU_TOL_MON_CLK_CYCLE1_MASK (0xFFFFFFFF << 0) 605 #define PSRAM_ULP_MC_PMU_TOL_MON_CLK_CYCLE1_SHIFT (0) 606 607 // reg_44c 608 #define PSRAM_ULP_MC_PMU_TOL_WR_DATA_BYTES0(n) (((n) & 0xFFFFFFFF) << 0) 609 #define PSRAM_ULP_MC_PMU_TOL_WR_DATA_BYTES0_MASK (0xFFFFFFFF << 0) 610 #define PSRAM_ULP_MC_PMU_TOL_WR_DATA_BYTES0_SHIFT (0) 611 612 // reg_450 613 #define PSRAM_ULP_MC_PMU_TOL_WR_DATA_BYTES1(n) (((n) & 0xFFFFFFFF) << 0) 614 #define PSRAM_ULP_MC_PMU_TOL_WR_DATA_BYTES1_MASK (0xFFFFFFFF << 0) 615 #define PSRAM_ULP_MC_PMU_TOL_WR_DATA_BYTES1_SHIFT (0) 616 617 // reg_454 618 #define PSRAM_ULP_MC_PMU_TOL_RD_DATA_BYTES0(n) (((n) & 0xFFFFFFFF) << 0) 619 #define PSRAM_ULP_MC_PMU_TOL_RD_DATA_BYTES0_MASK (0xFFFFFFFF << 0) 620 #define PSRAM_ULP_MC_PMU_TOL_RD_DATA_BYTES0_SHIFT (0) 621 622 // reg_458 623 #define PSRAM_ULP_MC_PMU_TOL_RD_DATA_BYTES1(n) (((n) & 0xFFFFFFFF) << 0) 624 #define PSRAM_ULP_MC_PMU_TOL_RD_DATA_BYTES1_MASK (0xFFFFFFFF << 0) 625 #define PSRAM_ULP_MC_PMU_TOL_RD_DATA_BYTES1_SHIFT (0) 626 627 // reg_45c 628 #define PSRAM_ULP_MC_PMU_TOL_RD_ACC_LATENCY0(n) (((n) & 0xFFFFFFFF) << 0) 629 #define PSRAM_ULP_MC_PMU_TOL_RD_ACC_LATENCY0_MASK (0xFFFFFFFF << 0) 630 #define PSRAM_ULP_MC_PMU_TOL_RD_ACC_LATENCY0_SHIFT (0) 631 632 // reg_460 633 #define PSRAM_ULP_MC_PMU_TOL_RD_ACC_LATENCY1(n) (((n) & 0xFFFFFFFF) << 0) 634 #define PSRAM_ULP_MC_PMU_TOL_RD_ACC_LATENCY1_MASK (0xFFFFFFFF << 0) 635 #define PSRAM_ULP_MC_PMU_TOL_RD_ACC_LATENCY1_SHIFT (0) 636 637 // reg_464 638 #define PSRAM_ULP_MC_PMU_TOL_RD_ACC_NUM0(n) (((n) & 0xFFFFFFFF) << 0) 639 #define PSRAM_ULP_MC_PMU_TOL_RD_ACC_NUM0_MASK (0xFFFFFFFF << 0) 640 #define PSRAM_ULP_MC_PMU_TOL_RD_ACC_NUM0_SHIFT (0) 641 642 // reg_468 643 #define PSRAM_ULP_MC_PMU_TOL_RD_ACC_NUM1(n) (((n) & 0xFFFFFFFF) << 0) 644 #define PSRAM_ULP_MC_PMU_TOL_RD_ACC_NUM1_MASK (0xFFFFFFFF << 0) 645 #define PSRAM_ULP_MC_PMU_TOL_RD_ACC_NUM1_SHIFT (0) 646 647 // reg_46c 648 #define PSRAM_ULP_MC_PMU_MAX_RD_ACC_LATENCY(n) (((n) & 0xFFFF) << 0) 649 #define PSRAM_ULP_MC_PMU_MAX_RD_ACC_LATENCY_MASK (0xFFFF << 0) 650 #define PSRAM_ULP_MC_PMU_MAX_RD_ACC_LATENCY_SHIFT (0) 651 652 // reg_470 653 #define PSRAM_ULP_MC_PMU_TOL_WR_ACC_NUM_TO_DIE(n) (((n) & 0xFFFFFFFF) << 0) 654 #define PSRAM_ULP_MC_PMU_TOL_WR_ACC_NUM_TO_DIE_MASK (0xFFFFFFFF << 0) 655 #define PSRAM_ULP_MC_PMU_TOL_WR_ACC_NUM_TO_DIE_SHIFT (0) 656 657 // reg_474 658 #define PSRAM_ULP_MC_PMU_TOL_WR_CYCS_IN_MCLK_0(n) (((n) & 0xFFFFFFFF) << 0) 659 #define PSRAM_ULP_MC_PMU_TOL_WR_CYCS_IN_MCLK_0_MASK (0xFFFFFFFF << 0) 660 #define PSRAM_ULP_MC_PMU_TOL_WR_CYCS_IN_MCLK_0_SHIFT (0) 661 662 // reg_478 663 #define PSRAM_ULP_MC_PMU_TOL_WR_CYCS_IN_MCLK_1(n) (((n) & 0xFFFFFFFF) << 0) 664 #define PSRAM_ULP_MC_PMU_TOL_WR_CYCS_IN_MCLK_1_MASK (0xFFFFFFFF << 0) 665 #define PSRAM_ULP_MC_PMU_TOL_WR_CYCS_IN_MCLK_1_SHIFT (0) 666 667 // reg_47c 668 #define PSRAM_ULP_MC_PMU_TOL_RD_ACC_NUM_TO_DIE(n) (((n) & 0xFFFFFFFF) << 0) 669 #define PSRAM_ULP_MC_PMU_TOL_RD_ACC_NUM_TO_DIE_MASK (0xFFFFFFFF << 0) 670 #define PSRAM_ULP_MC_PMU_TOL_RD_ACC_NUM_TO_DIE_SHIFT (0) 671 672 // reg_480 673 #define PSRAM_ULP_MC_PMU_TOL_RD_CYCS_IN_MCLK_0(n) (((n) & 0xFFFFFFFF) << 0) 674 #define PSRAM_ULP_MC_PMU_TOL_RD_CYCS_IN_MCLK_0_MASK (0xFFFFFFFF << 0) 675 #define PSRAM_ULP_MC_PMU_TOL_RD_CYCS_IN_MCLK_0_SHIFT (0) 676 677 // reg_484 678 #define PSRAM_ULP_MC_PMU_TOL_RD_CYCS_IN_MCLK_1(n) (((n) & 0xFFFFFFFF) << 0) 679 #define PSRAM_ULP_MC_PMU_TOL_RD_CYCS_IN_MCLK_1_MASK (0xFFFFFFFF << 0) 680 #define PSRAM_ULP_MC_PMU_TOL_RD_CYCS_IN_MCLK_1_SHIFT (0) 681 682 // reg_4cc 683 #define PSRAM_ULP_MC_DBG_RD_ADDRESS(n) (((n) & 0xFFFFFFFF) << 0) 684 #define PSRAM_ULP_MC_DBG_RD_ADDRESS_MASK (0xFFFFFFFF << 0) 685 #define PSRAM_ULP_MC_DBG_RD_ADDRESS_SHIFT (0) 686 687 // reg_4d0 688 #define PSRAM_ULP_MC_DBG_RD_VALID(n) (((n) & 0xFFFFFFFF) << 0) 689 #define PSRAM_ULP_MC_DBG_RD_VALID_MASK (0xFFFFFFFF << 0) 690 #define PSRAM_ULP_MC_DBG_RD_VALID_SHIFT (0) 691 692 // reg_4d4 693 #define PSRAM_ULP_MC_WRITE_UNLOCK_CLR (1 << 0) 694 695 // reg_4d8 696 #define PSRAM_ULP_MC_WRITE_UNLOCK_SET (1 << 0) 697 698 #endif 699