1 /* 2 * Copyright (c) 2021 Bestechnic (Shanghai) Co., Ltd. All rights reserved. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 #ifndef __REG_PSRAM_PHY_V2_H__ 16 #define __REG_PSRAM_PHY_V2_H__ 17 18 #include "plat_types.h" 19 20 struct PSRAM_PHY_T { 21 __IO uint32_t REG_000; 22 __IO uint32_t REG_004; 23 __IO uint32_t REG_008; 24 __IO uint32_t REG_00C; 25 __IO uint32_t REG_010; 26 __IO uint32_t REG_014; 27 __IO uint32_t REG_018; 28 __IO uint32_t REG_01C; 29 __IO uint32_t REG_020; 30 __IO uint32_t REG_024; 31 __IO uint32_t REG_028; 32 __IO uint32_t REG_02C; 33 __IO uint32_t REG_030; 34 __IO uint32_t REG_034; 35 __IO uint32_t REG_038; 36 __IO uint32_t REG_03C; 37 __IO uint32_t REG_040; 38 __IO uint32_t REG_044; 39 __IO uint32_t REG_048; 40 __IO uint32_t REG_04C; 41 __IO uint32_t REG_050; 42 __IO uint32_t REG_054; 43 __IO uint32_t REG_058; 44 __IO uint32_t REG_05C; 45 }; 46 47 // reg_00 48 #define PSRAM_ULP_PHY_CHIP_TYPE (1 << 0) 49 #define PSRAM_ULP_PHY_CHIP_BIT (1 << 1) 50 #define PSRAM_ULP_PHY_MEMORY_WIDTH(n) (((n) & 0x3) << 2) 51 #define PSRAM_ULP_PHY_MEMORY_WIDTH_MASK (0x3 << 2) 52 #define PSRAM_ULP_PHY_MEMORY_WIDTH_SHIFT (2) 53 #define PSRAM_ULP_PHY_FRE_RATIO(n) (((n) & 0x3) << 4) 54 #define PSRAM_ULP_PHY_FRE_RATIO_MASK (0x3 << 4) 55 #define PSRAM_ULP_PHY_FRE_RATIO_SHIFT (4) 56 57 // reg_04 58 #define PSRAM_ULP_PHY_CTRL_DELAY(n) (((n) & 0x3) << 0) 59 #define PSRAM_ULP_PHY_CTRL_DELAY_MASK (0x3 << 0) 60 #define PSRAM_ULP_PHY_CTRL_DELAY_SHIFT (0) 61 #define PSRAM_ULP_PHY_RX_DLY_EN (1 << 2) 62 #define PSRAM_ULP_PHY_ALIGN_BYPASS (1 << 3) 63 #define PSRAM_ULP_PHY_PHY_LOOPBACK_EN (1 << 4) 64 #define PSRAM_ULP_PHY_PHY_DUMMY_CYC_EN (1 << 5) 65 #define PSRAM_ULP_PHY_PHY_DLY_AUTO_EN (1 << 6) 66 #define PSRAM_ULP_PHY_SQPI_SAMPLE_SEL(n) (((n) & 0xF) << 7) 67 #define PSRAM_ULP_PHY_SQPI_SAMPLE_SEL_MASK (0xF << 7) 68 #define PSRAM_ULP_PHY_SQPI_SAMPLE_SEL_SHIFT (7) 69 #define PSRAM_ULP_PHY_IDLE_DQ_OEN (1 << 11) 70 #define PSRAM_ULP_PHY_PHY_TX_BYPASS (1 << 12) 71 #define PSRAM_ULP_PHY_ADDR_4BYTES_EN (1 << 13) 72 #define PSRAM_ULP_PHY_IDLE_DQS_OEN (1 << 14) 73 #define PSRAM_ULP_PHY_DQS_DM_MERGE_EN (1 << 15) 74 #define PSRAM_ULP_PHY_HYPER_TYPE (1 << 16) 75 76 // reg_08 77 #define PSRAM_ULP_PHY_T_WPST(n) (((n) & 0x7) << 0) 78 #define PSRAM_ULP_PHY_T_WPST_MASK (0x7 << 0) 79 #define PSRAM_ULP_PHY_T_WPST_SHIFT (0) 80 81 // reg_0c 82 #define PSRAM_ULP_PHY_RESERVED(n) (((n) & 0x3F) << 0) 83 #define PSRAM_ULP_PHY_RESERVED_MASK (0x3F << 0) 84 #define PSRAM_ULP_PHY_RESERVED_SHIFT (0) 85 86 // reg_00 87 88 // reg_10 89 #define PSRAM_ULP_PHY_CMD_CONFLICT_CLR (1 << 0) 90 91 // reg_14 92 #define PSRAM_ULP_PHY_SQPI_CMD_CONFLICT_CLR (1 << 0) 93 94 // reg_40 95 #define PSRAM_ULP_PHY_PHY_RX_BYPASS (1 << 0) 96 #define PSRAM_ULP_PHY_PHY_SAMP_WITH_CLK (1 << 1) 97 98 // reg_44 99 #define PSRAM_ULP_PHY_CMD_CONFLICT_STS (1 << 0) 100 #define PSRAM_ULP_PHY_PHY_FSM_STATE(n) (((n) & 0xF) << 1) 101 #define PSRAM_ULP_PHY_PHY_FSM_STATE_MASK (0xF << 1) 102 #define PSRAM_ULP_PHY_PHY_FSM_STATE_SHIFT (1) 103 #define PSRAM_ULP_PHY_SQPI_CMD_CONFLICT_STS (1 << 5) 104 #define PSRAM_ULP_PHY_SQPI_PHY_FSM_STATE(n) (((n) & 0xF) << 6) 105 #define PSRAM_ULP_PHY_SQPI_PHY_FSM_STATE_MASK (0xF << 6) 106 #define PSRAM_ULP_PHY_SQPI_PHY_FSM_STATE_SHIFT (6) 107 108 // reg_48 109 #define PSRAM_ULP_PHY_REG_LDO_PU (1 << 0) 110 #define PSRAM_ULP_PHY_REG_LDO_PRECHARGE (1 << 1) 111 #define PSRAM_ULP_PHY_REG_LDO_IEN1(n) (((n) & 0xF) << 2) 112 #define PSRAM_ULP_PHY_REG_LDO_IEN1_MASK (0xF << 2) 113 #define PSRAM_ULP_PHY_REG_LDO_IEN1_SHIFT (2) 114 #define PSRAM_ULP_PHY_REG_LDO_IEN2(n) (((n) & 0xF) << 6) 115 #define PSRAM_ULP_PHY_REG_LDO_IEN2_MASK (0xF << 6) 116 #define PSRAM_ULP_PHY_REG_LDO_IEN2_SHIFT (6) 117 #define PSRAM_ULP_PHY_REG_LDO_VTUNE(n) (((n) & 0x7) << 10) 118 #define PSRAM_ULP_PHY_REG_LDO_VTUNE_MASK (0x7 << 10) 119 #define PSRAM_ULP_PHY_REG_LDO_VTUNE_SHIFT (10) 120 121 // reg_4c 122 #define PSRAM_ULP_PHY_REG_PSRAM_PU (1 << 0) 123 #define PSRAM_ULP_PHY_REG_PSRAM_SWRC(n) (((n) & 0x3) << 1) 124 #define PSRAM_ULP_PHY_REG_PSRAM_SWRC_MASK (0x3 << 1) 125 #define PSRAM_ULP_PHY_REG_PSRAM_SWRC_SHIFT (1) 126 #define PSRAM_ULP_PHY_REG_PSRAM_TXDRV(n) (((n) & 0x7) << 3) 127 #define PSRAM_ULP_PHY_REG_PSRAM_TXDRV_MASK (0x7 << 3) 128 #define PSRAM_ULP_PHY_REG_PSRAM_TXDRV_SHIFT (3) 129 #define PSRAM_ULP_PHY_REG_PSRAM_LOOPBACK_EN (1 << 6) 130 131 // reg_50 132 #define PSRAM_ULP_PHY_REG_DLL_PU (1 << 0) 133 #define PSRAM_ULP_PHY_REG_DLL_SWRC(n) (((n) & 0x3) << 1) 134 #define PSRAM_ULP_PHY_REG_DLL_SWRC_MASK (0x3 << 1) 135 #define PSRAM_ULP_PHY_REG_DLL_SWRC_SHIFT (1) 136 #define PSRAM_ULP_PHY_REG_DLL_RANGE(n) (((n) & 0x3) << 3) 137 #define PSRAM_ULP_PHY_REG_DLL_RANGE_MASK (0x3 << 3) 138 #define PSRAM_ULP_PHY_REG_DLL_RANGE_SHIFT (3) 139 #define PSRAM_ULP_PHY_REG_DLL_DLY_INI(n) (((n) & 0xFF) << 5) 140 #define PSRAM_ULP_PHY_REG_DLL_DLY_INI_MASK (0xFF << 5) 141 #define PSRAM_ULP_PHY_REG_DLL_DLY_INI_SHIFT (5) 142 #define PSRAM_ULP_PHY_REG_DLL(n) (((n) & 0xFF) << 13) 143 #define PSRAM_ULP_PHY_REG_DLL_MASK (0xFF << 13) 144 #define PSRAM_ULP_PHY_REG_DLL_SHIFT (13) 145 #define PSRAM_ULP_PHY_REG_BYPASS_DECIMATION (1 << 16) 146 #define PSRAM_ULP_PHY_REG_DLL_RESETB (1 << 21) 147 #define PSRAM_ULP_PHY_REG_DLL_CK_RDY (1 << 22) 148 149 // reg_54 150 #define PSRAM_ULP_PHY_REG_PSRAM_TX_CEB_DLY(n) (((n) & 0x1F) << 0) 151 #define PSRAM_ULP_PHY_REG_PSRAM_TX_CEB_DLY_MASK (0x1F << 0) 152 #define PSRAM_ULP_PHY_REG_PSRAM_TX_CEB_DLY_SHIFT (0) 153 #define PSRAM_ULP_PHY_REG_PSRAM_TX_CLK_DLY(n) (((n) & 0x1F) << 5) 154 #define PSRAM_ULP_PHY_REG_PSRAM_TX_CLK_DLY_MASK (0x1F << 5) 155 #define PSRAM_ULP_PHY_REG_PSRAM_TX_CLK_DLY_SHIFT (5) 156 #define PSRAM_ULP_PHY_REG_PSRAM_TX_DQS_DLY(n) (((n) & 0x1F) << 10) 157 #define PSRAM_ULP_PHY_REG_PSRAM_TX_DQS_DLY_MASK (0x1F << 10) 158 #define PSRAM_ULP_PHY_REG_PSRAM_TX_DQS_DLY_SHIFT (10) 159 #define PSRAM_ULP_PHY_REG_PSRAM_RX_DQS_DLY(n) (((n) & 0x1F) << 15) 160 #define PSRAM_ULP_PHY_REG_PSRAM_RX_DQS_DLY_MASK (0x1F << 15) 161 #define PSRAM_ULP_PHY_REG_PSRAM_RX_DQS_DLY_SHIFT (15) 162 #define PSRAM_ULP_PHY_REG_PSRAM_RX_CLK_DLY(n) (((n) & 0x1F) << 20) 163 #define PSRAM_ULP_PHY_REG_PSRAM_RX_CLK_DLY_MASK (0x1F << 20) 164 #define PSRAM_ULP_PHY_REG_PSRAM_RX_CLK_DLY_SHIFT (20) 165 166 // reg_58 167 #define PSRAM_ULP_PHY_DLL_DLY_IN(n) (((n) & 0x3F) << 0) 168 #define PSRAM_ULP_PHY_DLL_DLY_IN_MASK (0x3F << 0) 169 #define PSRAM_ULP_PHY_DLL_DLY_IN_SHIFT (0) 170 #define PSRAM_ULP_PHY_DLL_LOCK (1 << 6) 171 #define PSRAM_ULP_PHY_DLL_ALL_ZERO (1 << 7) 172 #define PSRAM_ULP_PHY_DLL_ALL_ONE (1 << 8) 173 174 #endif 175