1 /* 2 * Copyright (c) 2021 Bestechnic (Shanghai) Co., Ltd. All rights reserved. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 #ifndef __REG_SPI_H__ 16 #define __REG_SPI_H__ 17 18 #include "plat_types.h" 19 20 struct SPI_T 21 { 22 __IO uint32_t SSPCR0; //0x00000000 23 __IO uint32_t SSPCR1; //0x00000004 24 __IO uint32_t SSPDR; //0x00000008 25 __I uint32_t SSPSR; //0x0000000C 26 __IO uint32_t SSPCPSR; //0x00000010 27 __IO uint32_t SSPIMSC; //0x00000014 28 __I uint32_t SSPRIS; //0x00000018 29 __I uint32_t SSPMIS; //0x0000001C 30 __O uint32_t SSPICR; //0x00000020 31 __IO uint32_t SSPDMACR; //0x00000024 32 uint32_t reserved[0x18]; //0x00000028 33 __IO uint32_t SSPRXCR; //0x00000088 34 }; 35 36 struct SAVED_SPI_REGS_T { 37 uint32_t SSPCR0; 38 uint16_t SSPCR1; 39 uint16_t SSPCPSR; 40 uint16_t SSPDMACR; 41 uint16_t SSPRXCR; 42 }; 43 44 #define MAX_SCR (0xFF) 45 #define MIN_SCR (0) 46 #define MAX_DATA_BITS (32) 47 #define MIN_DATA_BITS (4) 48 49 #define SPI_SSPCR0_DSS(n) (((n) & 0x1F) << 16) 50 #define SPI_SSPCR0_DSS_MASK (0x1F << 16) 51 #define SPI_SSPCR0_DSS_SHIFT (16) 52 #define SPI_SSPCR0_SCR(n) (((n) & 0xFF) << 8) 53 #define SPI_SSPCR0_SCR_MASK (0xFF << 8) 54 #define SPI_SSPCR0_SCR_SHIFT (8) 55 #define SPI_SSPCR0_SPH (1 << 7) 56 #define SPI_SSPCR0_SPO (1 << 6) 57 #define SPI_SSPCR0_FRF(n) (((n) & 3) << 4) 58 #define SPI_SSPCR0_FRF_MASK (3 << 4) 59 #define SPI_SSPCR0_FRF_SHIFT (4) 60 61 #if (CHIP_SPI_VER >= 4) 62 #define SPI_RX_SEL_EN (1 << 11) 63 #define SPI_SLAVE_ID_SHIFT (7) 64 #define SPI_SLAVE_ID_MASK (0xF << SPI_SLAVE_ID_SHIFT) 65 #define SPI_SLAVE_ID(n) BITFIELD_VAL(SPI_SLAVE_ID, n) 66 #else 67 #define SPI_RX_SEL_EN (1 << 9) 68 #define SPI_SLAVE_ID_SHIFT (7) 69 #define SPI_SLAVE_ID_MASK (3 << SPI_SLAVE_ID_SHIFT) 70 #define SPI_SLAVE_ID(n) BITFIELD_VAL(SPI_SLAVE_ID, n) 71 #endif 72 #define SPI_LCD_DC_DATA (1 << 4) 73 #define SPI_SSPCR1_SOD (1 << 3) 74 #define SPI_SSPCR1_MS (1 << 2) 75 #define SPI_SSPCR1_SSE (1 << 1) 76 #define SPI_SSPCR1_LBM (1 << 0) 77 78 #define SPI_SSPSR_BSY (1 << 4) 79 #define SPI_SSPSR_RFF (1 << 3) 80 #define SPI_SSPSR_RNE (1 << 2) 81 #define SPI_SSPSR_TNF (1 << 1) 82 #define SPI_SSPSR_TFE (1 << 0) 83 84 #define MAX_CPSDVSR (0xFE) 85 #define MIN_CPSDVSR (2) 86 87 #define SPI_SSPCPSR_CPSDVSR(n) (((n) & 0xFF) << 0) 88 #define SPI_SSPCPSR_CPSDVSR_MASK (0xFF << 0) 89 #define SPI_SSPCPSR_CPSDVSR_SHIFT (0) 90 91 #define SPI_SSPIMSC_TXIM (1 << 3) 92 #define SPI_SSPIMSC_RXIM (1 << 2) 93 #define SPI_SSPIMSC_RTIM (1 << 1) 94 #define SPI_SSPIMSC_RORIM (1 << 0) 95 96 #define SPI_SSPRIS_TXRIS (1 << 3) 97 #define SPI_SSPRIS_RXRIS (1 << 2) 98 #define SPI_SSPRIS_RTRIS (1 << 1) 99 #define SPI_SSPRIS_RORRIS (1 << 0) 100 101 #define SPI_SSPMIS_TXMIS (1 << 3) 102 #define SPI_SSPMIS_RXMIS (1 << 2) 103 #define SPI_SSPMIS_RTMIS (1 << 1) 104 #define SPI_SSPMIS_RORMIS (1 << 0) 105 106 #define SPI_SSPICR_RTIC (1 << 1) 107 #define SPI_SSPICR_RORIC (1 << 0) 108 109 #define SPI_SSPDMACR_TXDMAE (1 << 1) 110 #define SPI_SSPDMACR_RXDMAE (1 << 0) 111 112 #define SPI_SSPRXCR_EN (1 << 6) 113 #define SPI_SSPRXCR_OEN_POLARITY (1 << 5) 114 #define SPI_SSPRXCR_RXBITS(n) (((n) & 0x1F) << 0) 115 #define SPI_SSPRXCR_RXBITS_MASK (0x1F << 0) 116 #define SPI_SSPRXCR_RXBITS_SHIFT (0) 117 118 #endif 119 120