1 /* 2 * Copyright (c) 2021 Bestechnic (Shanghai) Co., Ltd. All rights reserved. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 #ifndef __REG_UART_H__ 16 #define __REG_UART_H__ 17 18 #include "plat_types.h" 19 20 // UART Registers 21 struct UART_T { 22 __IO uint32_t UARTDR; // 0x000 23 union { 24 __I uint32_t UARTRSR; // 0x004 25 __O uint32_t UARTECR; // 0x004 26 }; 27 uint32_t RESERVED_008[4]; // 0x008 28 __I uint32_t UARTFR; // 0x018 29 uint32_t RESERVED_01C; // 0x01C 30 __IO uint32_t UARTILPR; // 0x020 31 __IO uint32_t UARTIBRD; // 0x024 32 __IO uint32_t UARTFBRD; // 0x028 33 __IO uint32_t UARTLCR_H; // 0x02C 34 __IO uint32_t UARTCR; // 0x030 35 __IO uint32_t UARTIFLS; // 0x034 36 __IO uint32_t UARTIMSC; // 0x038 37 __I uint32_t UARTRIS; // 0x03C 38 __I uint32_t UARTMIS; // 0x040 39 __O uint32_t UARTICR; // 0x044 40 __IO uint32_t UARTDMACR; // 0x048 41 __IO uint32_t UARTOVSAMP; // 0x04C 42 __IO uint32_t UARTOVSAMPST; // 0x050 43 __IO uint32_t UARTRXEXT; // 0x054 44 uint32_t RESERVED_058[994]; // 0x058 45 __I uint32_t UARTPID0; // 0xFE0 46 __I uint32_t UARTPID1; // 0xFE4 47 __I uint32_t UARTPID2; // 0xFE8 48 __I uint32_t UARTPID3; // 0xFEC 49 __I uint32_t UARTPCID0; // 0xFF0 50 __I uint32_t UARTPCID1; // 0xFF4 51 __I uint32_t UARTPCID2; // 0xFF8 52 __I uint32_t UARTPCID3; // 0xFFC 53 }; 54 55 struct SAVED_UART_REGS_T { 56 uint32_t UARTILPR; 57 uint32_t UARTIBRD; 58 uint32_t UARTFBRD; 59 uint32_t UARTLCR_H; 60 uint32_t UARTCR; 61 uint32_t UARTIFLS; 62 uint32_t UARTIMSC; 63 uint32_t UARTDMACR; 64 }; 65 66 // Data status bits 67 #define UART_DATA_ERROR_MASK 0x0F00 68 69 // Status reg bits 70 #define UART_STATUS_ERROR_MASK 0x0F 71 72 // Flag reg bits 73 #define UARTFR_RI (1 << 8) // Ring indicator 74 #define UARTFR_TXFE (1 << 7) // Transmit FIFO empty 75 #define UARTFR_RXFF (1 << 6) // Receive FIFO full 76 #define UARTFR_TXFF (1 << 5) // Transmit FIFO full 77 #define UARTFR_RXFE (1 << 4) // Receive FIFO empty 78 #define UARTFR_BUSY (1 << 3) // UART busy 79 #define UARTFR_DCD (1 << 2) // Data carrier detect 80 #define UARTFR_DSR (1 << 1) // Data set ready 81 #define UARTFR_CTS (1 << 0) // Clear to send 82 83 // Flag reg bits - alternative names 84 #define UART_TX_EMPTY_FLAG_MASK UARTFR_TXFE 85 #define UART_RX_FULL_FLAG_MASK UARTFR_RXFF 86 #define UART_TX_FULL_FLAG_MASK UARTFR_TXFF 87 #define UART_RX_EMPTY_FLAG_MASK UARTFR_RXFE 88 #define UART_BUSY_FLAG_MASK UARTFR_BUSY 89 90 // Control reg bits 91 #define UARTCR_CTSEN (1 << 15) // CTS hardware flow control enable 92 #define UARTCR_RTSEN (1 << 14) // RTS hardware flow control enable 93 #define UARTCR_RTS (1 << 11) // Request to send 94 #define UARTCR_DTR (1 << 10) // Data transmit ready. 95 #define UARTCR_RXE (1 << 9) // Receive enable 96 #define UARTCR_TXE (1 << 8) // Transmit enable 97 #define UARTCR_LBE (1 << 7) // Loopback enable 98 #define UARTCR_UARTEN (1 << 0) // UART Enable 99 100 // Line Control Register Bits 101 #define UARTLCR_H_DMA_RT_EN (1 << 15) 102 #define UARTLCR_H_DMA_RT_CNT(n) (((n) & 0x7F) << 8) 103 #define UARTLCR_H_DMA_RT_CNT_MASK (0x7F << 8) 104 #define UARTLCR_H_DMA_RT_CNT_SHIFT (8) 105 #define UARTLCR_H_SPS (1 << 7) // Stick parity select 106 #define UARTLCR_H_WLEN_8 (3 << 5) 107 #define UARTLCR_H_WLEN_7 (2 << 5) 108 #define UARTLCR_H_WLEN_6 (1 << 5) 109 #define UARTLCR_H_WLEN_5 (0 << 5) 110 #define UARTLCR_H_FEN (1 << 4) // FIFOs Enable 111 #define UARTLCR_H_STP2 (1 << 3) // Two stop bits select 112 #define UARTLCR_H_EPS (1 << 2) // Even parity select 113 #define UARTLCR_H_PEN (1 << 1) // Parity Enable 114 #define UARTLCR_H_BRK (1 << 0) // Send break 115 116 // UARTIFLS reg bits 117 #define UARTIFLS_TXFIFO_LEVEL(n) (((n) & 7) << 0) 118 #define UARTIFLS_TXFIFO_LEVEL_MASK (7 << 0) 119 #define UARTIFLS_TXFIFO_LEVEL_SHIFT (0) 120 #define UARTIFLS_RXFIFO_LEVEL(n) (((n) & 7) << 3) 121 #define UARTIFLS_RXFIFO_LEVEL_MASK (7 << 3) 122 #define UARTIFLS_RXFIFO_LEVEL_SHIFT (3) 123 124 // Interrupt regs bits 125 #define UARTINTERRUPT_RIM (1 << 0) 126 #define UARTINTERRUPT_CTSM (1 << 1) 127 #define UARTINTERRUPT_DCDM (1 << 2) 128 #define UARTINTERRUPT_DSRM (1 << 3) 129 #define UARTINTERRUPT_RX (1 << 4) 130 #define UARTINTERRUPT_TX (1 << 5) 131 #define UARTINTERRUPT_RT (1 << 6) 132 #define UARTINTERRUPT_FE (1 << 7) 133 #define UARTINTERRUPT_PE (1 << 8) 134 #define UARTINTERRUPT_BE (1 << 9) 135 #define UARTINTERRUPT_OE (1 << 10) 136 137 // DMACR reg bits 138 #define UARTDMACR_RXDMAE (1 << 0) 139 #define UARTDMACR_TXDMAE (1 << 1) 140 #define UARTDMACR_DMAONERR (1 << 2) 141 142 // UARTOVSAMP 143 #define UARTOVSAMP_RATIO_SHIFT 0 144 #define UARTOVSAMP_RATIO_MASK (0xF << UARTOVSAMP_RATIO_SHIFT) 145 #define UARTOVSAMP_RATIO(n) BITFIELD_VAL(UARTOVSAMP_RATIO, n) 146 147 // UARTOVSAMPST 148 #define UARTOVSAMPST_START_SHIFT 0 149 #define UARTOVSAMPST_START_MASK (0xF << UARTOVSAMPST_START_SHIFT) 150 #define UARTOVSAMPST_START(n) BITFIELD_VAL(UARTOVSAMPST_START, n) 151 152 // UARTRXEXT 153 #define UARTRXEXT_BYPASS_HANDSHAKE (1 << 0) 154 #define UARTRXEXT_USE_RXD_REG (1 << 1) 155 156 #endif 157