1 /* 2 * Copyright (c) 2021 Bestechnic (Shanghai) Co., Ltd. All rights reserved. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 #ifndef __NORFLASH_CFG_H__ 16 #define __NORFLASH_CFG_H__ 17 18 #ifdef __cplusplus 19 extern "C" { 20 #endif 21 22 #include "stdint.h" 23 24 //------------------ 25 // Used in ROM efuse 26 //------------------ 27 enum SEC_REG_BASE_T { 28 SEC_REG_BASE_0X1000, 29 SEC_REG_BASE_0X0000, 30 SEC_REG_BASE_0X2000, 31 }; 32 33 //------------------ 34 // Used in ROM efuse 35 //------------------ 36 enum SEC_REG_SIZE_T { 37 SEC_REG_SIZE_1024, 38 SEC_REG_SIZE_512, 39 SEC_REG_SIZE_256, 40 SEC_REG_SIZE_4096, 41 }; 42 43 //------------------ 44 // Used in ROM efuse 45 //------------------ 46 enum SEC_REG_OFFSET_T { 47 SEC_REG_OFFSET_0X1000, 48 SEC_REG_OFFSET_0X0100, 49 }; 50 51 enum SEC_REG_CNT_T { 52 SEC_REG_CNT_3, 53 SEC_REG_CNT_4, 54 SEC_REG_CNT_2, 55 SEC_REG_CNT_1, 56 }; 57 58 enum SEC_REG_PP_T { 59 SEC_REG_PP_256, 60 SEC_REG_PP_1024, 61 }; 62 63 enum SEC_REG_LB_T { 64 SEC_REG_LB_S11_S13, 65 SEC_REG_LB_S10, 66 SEC_REG_LB_S10_S13, 67 SEC_REG_LB_S12_S13, 68 }; 69 70 enum NORFLASH_CFG_MOD_CLK_T { 71 NORFLASH_CFG_MOD_CLK_32K, 72 NORFLASH_CFG_MOD_CLK_26M, 73 NORFLASH_CFG_MOD_CLK_52M, 74 NORFLASH_CFG_MOD_CLK_78M, 75 NORFLASH_CFG_MOD_CLK_104M, 76 NORFLASH_CFG_MOD_CLK_208M, 77 78 NORFLASH_CFG_MOD_CLK_QTY 79 }; 80 81 struct norflash_cfg_struct_t { 82 uint8_t neg_phase:1; 83 uint8_t pos_neg:1; 84 uint8_t reserved_2:1; 85 uint8_t samdly:3; 86 87 uint8_t div; /* least 2 */ 88 89 uint8_t dualmode:1; 90 uint8_t holdpin:1; 91 uint8_t wprpin:1; 92 uint8_t quadmode:1; 93 uint8_t mod_clk:4; 94 95 uint8_t spiruen:3; 96 uint8_t spirden:3; 97 98 uint8_t dualiocmd; 99 uint8_t rdcmd; 100 uint8_t frdcmd; 101 uint8_t qrdcmd; /* quad io cmd */ 102 }; 103 104 #ifdef __cplusplus 105 } 106 #endif 107 108 #endif 109 110