Searched refs:ICS_ARCIN_V6_INTROFFSET_2 (Results 1 – 4 of 4) sorted by relevance
39 #define ICS_ARCIN_V6_INTROFFSET_2 0x3200 macro125 readb(base + ICS_ARCIN_V6_INTROFFSET_2); in icside_irqenable_arcin_v6()128 writeb(0, base + ICS_ARCIN_V6_INTROFFSET_2); in icside_irqenable_arcin_v6()144 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2); in icside_irqdisable_arcin_v6()183 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2); in icside_maskproc()186 writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_2); in icside_maskproc()191 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2); in icside_maskproc()
38 #define ICS_ARCIN_V6_INTROFFSET_2 0x3200 macro124 readb(base + ICS_ARCIN_V6_INTROFFSET_2); in icside_irqenable_arcin_v6()127 writeb(0, base + ICS_ARCIN_V6_INTROFFSET_2); in icside_irqenable_arcin_v6()143 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2); in icside_irqdisable_arcin_v6()182 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2); in icside_maskproc()185 writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_2); in icside_maskproc()190 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2); in icside_maskproc()
23 #define ICS_ARCIN_V6_INTROFFSET_2 0x3200 macro121 writeb(0, base + ICS_ARCIN_V6_INTROFFSET_2); in pata_icside_irqenable_arcin_v6()132 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2); in pata_icside_irqdisable_arcin_v6()319 (ap->port_no ? ICS_ARCIN_V6_INTROFFSET_2 : ICS_ARCIN_V6_INTROFFSET_1); in pata_icside_postreset()
22 #define ICS_ARCIN_V6_INTROFFSET_2 0x3200 macro120 writeb(0, base + ICS_ARCIN_V6_INTROFFSET_2); in pata_icside_irqenable_arcin_v6()131 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2); in pata_icside_irqdisable_arcin_v6()318 (ap->port_no ? ICS_ARCIN_V6_INTROFFSET_2 : ICS_ARCIN_V6_INTROFFSET_1); in pata_icside_postreset()