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/kernel/linux/linux-5.10/drivers/gpio/
Dgpio-omap.c77 void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable);
83 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage) argument
108 static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio, in omap_set_gpio_direction() argument
111 bank->context.oe = omap_gpio_rmw(bank->base + bank->regs->direction, in omap_set_gpio_direction()
117 static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset, in omap_set_gpio_dataout_reg() argument
120 void __iomem *reg = bank->base; in omap_set_gpio_dataout_reg()
124 reg += bank->regs->set_dataout; in omap_set_gpio_dataout_reg()
125 bank->context.dataout |= l; in omap_set_gpio_dataout_reg()
127 reg += bank->regs->clr_dataout; in omap_set_gpio_dataout_reg()
128 bank->context.dataout &= ~l; in omap_set_gpio_dataout_reg()
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Dgpio-brcmstb.c36 #define GIO_BANK_OFF(bank, off) (((bank) * GIO_BANK_SIZE) + (off * sizeof(u32))) argument
37 #define GIO_ODEN(bank) GIO_BANK_OFF(bank, GIO_REG_ODEN) argument
38 #define GIO_DATA(bank) GIO_BANK_OFF(bank, GIO_REG_DATA) argument
39 #define GIO_IODIR(bank) GIO_BANK_OFF(bank, GIO_REG_IODIR) argument
40 #define GIO_EC(bank) GIO_BANK_OFF(bank, GIO_REG_EC) argument
41 #define GIO_EI(bank) GIO_BANK_OFF(bank, GIO_REG_EI) argument
42 #define GIO_MASK(bank) GIO_BANK_OFF(bank, GIO_REG_MASK) argument
43 #define GIO_LEVEL(bank) GIO_BANK_OFF(bank, GIO_REG_LEVEL) argument
44 #define GIO_STAT(bank) GIO_BANK_OFF(bank, GIO_REG_STAT) argument
76 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); in brcmstb_gpio_gc_to_priv() local
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/kernel/linux/linux-4.19/drivers/gpio/
Dgpio-omap.c79 void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable);
80 void (*set_dataout_multiple)(struct gpio_bank *bank,
89 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage) argument
100 static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio, in omap_set_gpio_direction() argument
103 void __iomem *reg = bank->base; in omap_set_gpio_direction()
106 reg += bank->regs->direction; in omap_set_gpio_direction()
113 bank->context.oe = l; in omap_set_gpio_direction()
118 static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset, in omap_set_gpio_dataout_reg() argument
121 void __iomem *reg = bank->base; in omap_set_gpio_dataout_reg()
125 reg += bank->regs->set_dataout; in omap_set_gpio_dataout_reg()
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Dgpio-brcmstb.c36 #define GIO_BANK_OFF(bank, off) (((bank) * GIO_BANK_SIZE) + (off * sizeof(u32))) argument
37 #define GIO_ODEN(bank) GIO_BANK_OFF(bank, GIO_REG_ODEN) argument
38 #define GIO_DATA(bank) GIO_BANK_OFF(bank, GIO_REG_DATA) argument
39 #define GIO_IODIR(bank) GIO_BANK_OFF(bank, GIO_REG_IODIR) argument
40 #define GIO_EC(bank) GIO_BANK_OFF(bank, GIO_REG_EC) argument
41 #define GIO_EI(bank) GIO_BANK_OFF(bank, GIO_REG_EI) argument
42 #define GIO_MASK(bank) GIO_BANK_OFF(bank, GIO_REG_MASK) argument
43 #define GIO_LEVEL(bank) GIO_BANK_OFF(bank, GIO_REG_LEVEL) argument
44 #define GIO_STAT(bank) GIO_BANK_OFF(bank, GIO_REG_STAT) argument
76 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); in brcmstb_gpio_gc_to_priv() local
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/kernel/linux/linux-4.19/drivers/pinctrl/sh-pfc/
Dsh_pfc.h387 #define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) \ argument
388 fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
389 #define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0) argument
391 #define PORT_GP_CFG_4(bank, fn, sfx, cfg) \ argument
392 PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), \
393 PORT_GP_CFG_1(bank, 1, fn, sfx, cfg), \
394 PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), \
395 PORT_GP_CFG_1(bank, 3, fn, sfx, cfg)
396 #define PORT_GP_4(bank, fn, sfx) PORT_GP_CFG_4(bank, fn, sfx, 0) argument
398 #define PORT_GP_CFG_6(bank, fn, sfx, cfg) \ argument
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/kernel/linux/linux-5.10/drivers/pinctrl/renesas/
Dsh_pfc.h448 #define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) \ argument
449 fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
450 #define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0) argument
452 #define PORT_GP_CFG_4(bank, fn, sfx, cfg) \ argument
453 PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), \
454 PORT_GP_CFG_1(bank, 1, fn, sfx, cfg), \
455 PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), \
456 PORT_GP_CFG_1(bank, 3, fn, sfx, cfg)
457 #define PORT_GP_4(bank, fn, sfx) PORT_GP_CFG_4(bank, fn, sfx, 0) argument
459 #define PORT_GP_CFG_6(bank, fn, sfx, cfg) \ argument
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/kernel/linux/linux-5.10/drivers/pinctrl/samsung/
Dpinctrl-exynos.c56 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_irq_mask() local
57 unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset; in exynos_irq_mask()
61 spin_lock_irqsave(&bank->slock, flags); in exynos_irq_mask()
63 mask = readl(bank->eint_base + reg_mask); in exynos_irq_mask()
65 writel(mask, bank->eint_base + reg_mask); in exynos_irq_mask()
67 spin_unlock_irqrestore(&bank->slock, flags); in exynos_irq_mask()
74 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_irq_ack() local
75 unsigned long reg_pend = our_chip->eint_pend + bank->eint_offset; in exynos_irq_ack()
77 writel(1 << irqd->hwirq, bank->eint_base + reg_pend); in exynos_irq_ack()
84 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_irq_unmask() local
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/kernel/linux/linux-4.19/drivers/pinctrl/samsung/
Dpinctrl-exynos.c56 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_irq_mask() local
57 unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset; in exynos_irq_mask()
61 spin_lock_irqsave(&bank->slock, flags); in exynos_irq_mask()
63 mask = readl(bank->eint_base + reg_mask); in exynos_irq_mask()
65 writel(mask, bank->eint_base + reg_mask); in exynos_irq_mask()
67 spin_unlock_irqrestore(&bank->slock, flags); in exynos_irq_mask()
74 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_irq_ack() local
75 unsigned long reg_pend = our_chip->eint_pend + bank->eint_offset; in exynos_irq_ack()
77 writel(1 << irqd->hwirq, bank->eint_base + reg_pend); in exynos_irq_ack()
84 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_irq_unmask() local
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/kernel/linux/linux-5.10/drivers/crypto/qat/qat_common/
Dadf_transport.c36 static int adf_reserve_ring(struct adf_etr_bank_data *bank, u32 ring) in adf_reserve_ring() argument
38 spin_lock(&bank->lock); in adf_reserve_ring()
39 if (bank->ring_mask & (1 << ring)) { in adf_reserve_ring()
40 spin_unlock(&bank->lock); in adf_reserve_ring()
43 bank->ring_mask |= (1 << ring); in adf_reserve_ring()
44 spin_unlock(&bank->lock); in adf_reserve_ring()
48 static void adf_unreserve_ring(struct adf_etr_bank_data *bank, u32 ring) in adf_unreserve_ring() argument
50 spin_lock(&bank->lock); in adf_unreserve_ring()
51 bank->ring_mask &= ~(1 << ring); in adf_unreserve_ring()
52 spin_unlock(&bank->lock); in adf_unreserve_ring()
[all …]
Dadf_transport_access_macros.h77 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \ argument
78 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
80 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \ argument
81 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
83 #define READ_CSR_E_STAT(csr_base_addr, bank) \ argument
84 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
86 #define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \ argument
87 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
89 #define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \ argument
94 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
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/kernel/linux/linux-4.19/drivers/crypto/qat/qat_common/
Dadf_transport.c80 static int adf_reserve_ring(struct adf_etr_bank_data *bank, uint32_t ring) in adf_reserve_ring() argument
82 spin_lock(&bank->lock); in adf_reserve_ring()
83 if (bank->ring_mask & (1 << ring)) { in adf_reserve_ring()
84 spin_unlock(&bank->lock); in adf_reserve_ring()
87 bank->ring_mask |= (1 << ring); in adf_reserve_ring()
88 spin_unlock(&bank->lock); in adf_reserve_ring()
92 static void adf_unreserve_ring(struct adf_etr_bank_data *bank, uint32_t ring) in adf_unreserve_ring() argument
94 spin_lock(&bank->lock); in adf_unreserve_ring()
95 bank->ring_mask &= ~(1 << ring); in adf_unreserve_ring()
96 spin_unlock(&bank->lock); in adf_unreserve_ring()
[all …]
Dadf_transport_access_macros.h121 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \ argument
122 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
124 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \ argument
125 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
127 #define READ_CSR_E_STAT(csr_base_addr, bank) \ argument
128 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
130 #define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \ argument
131 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
133 #define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \ argument
138 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
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/kernel/linux/linux-5.10/drivers/pinctrl/stm32/
Dpinctrl-stm32.c153 static void stm32_gpio_backup_value(struct stm32_gpio_bank *bank, in stm32_gpio_backup_value() argument
156 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL); in stm32_gpio_backup_value()
157 bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL; in stm32_gpio_backup_value()
160 static void stm32_gpio_backup_mode(struct stm32_gpio_bank *bank, u32 offset, in stm32_gpio_backup_mode() argument
163 bank->pin_backup[offset] &= ~(STM32_GPIO_BKP_MODE_MASK | in stm32_gpio_backup_mode()
165 bank->pin_backup[offset] |= mode << STM32_GPIO_BKP_MODE_SHIFT; in stm32_gpio_backup_mode()
166 bank->pin_backup[offset] |= alt << STM32_GPIO_BKP_ALT_SHIFT; in stm32_gpio_backup_mode()
169 static void stm32_gpio_backup_driving(struct stm32_gpio_bank *bank, u32 offset, in stm32_gpio_backup_driving() argument
172 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_TYPE); in stm32_gpio_backup_driving()
173 bank->pin_backup[offset] |= drive << STM32_GPIO_BKP_TYPE; in stm32_gpio_backup_driving()
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/kernel/linux/linux-4.19/drivers/pinctrl/stm32/
Dpinctrl-stm32.c131 static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank, in __stm32_gpio_set() argument
137 clk_enable(bank->clk); in __stm32_gpio_set()
139 writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR); in __stm32_gpio_set()
141 clk_disable(bank->clk); in __stm32_gpio_set()
146 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); in stm32_gpio_request() local
147 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_gpio_request()
149 int pin = offset + (bank->bank_nr * STM32_GPIO_PINS_PER_BANK); in stm32_gpio_request()
167 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); in stm32_gpio_get() local
170 clk_enable(bank->clk); in stm32_gpio_get()
172 ret = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset)); in stm32_gpio_get()
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/kernel/linux/linux-4.19/drivers/pinctrl/
Dpinctrl-rockchip.c343 void (*pull_calc_reg)(struct rockchip_pin_bank *bank,
346 void (*drv_calc_reg)(struct rockchip_pin_bank *bank,
349 int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank,
683 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, in rockchip_get_recalced_mux() argument
686 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_recalced_mux()
693 if (data->num == bank->bank_num && in rockchip_get_recalced_mux()
1094 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, in rockchip_get_mux_route() argument
1097 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_mux_route()
1104 if ((data->bank_num == bank->bank_num) && in rockchip_get_mux_route()
1118 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) in rockchip_get_mux() argument
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/kernel/linux/linux-5.10/arch/arm/mach-s3c/
Diotiming-s3c2412.c41 unsigned int bank; in s3c2412_print_timing() local
43 for (bank = 0; bank < MAX_BANKS; bank++) { in s3c2412_print_timing()
44 bt = iot->bank[bank].io_2412; in s3c2412_print_timing()
49 "wstoen=%d.%d wstwen=%d.%d wstbrd=%d.%d\n", pfx, bank, in s3c2412_print_timing()
142 int bank; in s3c2412_iotiming_calc() local
145 for (bank = 0; bank < MAX_BANKS; bank++) { in s3c2412_iotiming_calc()
146 bt = iot->bank[bank].io_2412; in s3c2412_iotiming_calc()
153 __func__, bank); in s3c2412_iotiming_calc()
176 int bank; in s3c2412_iotiming_set() local
180 for (bank = 0; bank < MAX_BANKS; bank++) { in s3c2412_iotiming_set()
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Diotiming-s3c2410.c35 int bank; in s3c2410_print_timing() local
37 for (bank = 0; bank < MAX_BANKS; bank++) { in s3c2410_print_timing()
38 bt = timings->bank[bank].io_2410; in s3c2410_print_timing()
43 "Tcoh=%d.%d, Tcah=%d.%d\n", pfx, bank, in s3c2410_print_timing()
56 static inline void __iomem *bank_reg(unsigned int bank) in bank_reg() argument
58 return S3C2410_BANKCON0 + (bank << 2); in bank_reg()
362 int bank; in s3c2410_iotiming_calc() local
365 for (bank = 0; bank < MAX_BANKS; bank++) { in s3c2410_iotiming_calc()
366 bankcon = __raw_readl(bank_reg(bank)); in s3c2410_iotiming_calc()
367 bt = iot->bank[bank].io_2410; in s3c2410_iotiming_calc()
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/kernel/linux/linux-4.19/arch/arm/mach-s3c24xx/
Diotiming-s3c2412.c41 unsigned int bank; in s3c2412_print_timing() local
43 for (bank = 0; bank < MAX_BANKS; bank++) { in s3c2412_print_timing()
44 bt = iot->bank[bank].io_2412; in s3c2412_print_timing()
49 "wstoen=%d.%d wstwen=%d.%d wstbrd=%d.%d\n", pfx, bank, in s3c2412_print_timing()
142 int bank; in s3c2412_iotiming_calc() local
145 for (bank = 0; bank < MAX_BANKS; bank++) { in s3c2412_iotiming_calc()
146 bt = iot->bank[bank].io_2412; in s3c2412_iotiming_calc()
153 __func__, bank); in s3c2412_iotiming_calc()
176 int bank; in s3c2412_iotiming_set() local
180 for (bank = 0; bank < MAX_BANKS; bank++) { in s3c2412_iotiming_set()
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Diotiming-s3c2410.c35 int bank; in s3c2410_print_timing() local
37 for (bank = 0; bank < MAX_BANKS; bank++) { in s3c2410_print_timing()
38 bt = timings->bank[bank].io_2410; in s3c2410_print_timing()
43 "Tcoh=%d.%d, Tcah=%d.%d\n", pfx, bank, in s3c2410_print_timing()
56 static inline void __iomem *bank_reg(unsigned int bank) in bank_reg() argument
58 return S3C2410_BANKCON0 + (bank << 2); in bank_reg()
362 int bank; in s3c2410_iotiming_calc() local
365 for (bank = 0; bank < MAX_BANKS; bank++) { in s3c2410_iotiming_calc()
366 bankcon = __raw_readl(bank_reg(bank)); in s3c2410_iotiming_calc()
367 bt = iot->bank[bank].io_2410; in s3c2410_iotiming_calc()
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/kernel/linux/linux-5.10/arch/x86/kernel/cpu/mce/
Damd.c120 static enum smca_bank_types smca_get_bank_type(unsigned int bank) in smca_get_bank_type() argument
124 if (bank >= MAX_NR_BANKS) in smca_get_bank_type()
127 b = &smca_banks[bank]; in smca_get_bank_type()
214 static void smca_set_misc_banks_map(unsigned int bank, unsigned int cpu) in smca_set_misc_banks_map() argument
222 if (rdmsr_safe(MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high)) in smca_set_misc_banks_map()
228 if (rdmsr_safe(MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high)) in smca_set_misc_banks_map()
232 per_cpu(smca_misc_banks_map, cpu) |= BIT(bank); in smca_set_misc_banks_map()
236 static void smca_configure(unsigned int bank, unsigned int cpu) in smca_configure() argument
241 u32 smca_config = MSR_AMD64_SMCA_MCx_CONFIG(bank); in smca_configure()
273 smca_set_misc_banks_map(bank, cpu); in smca_configure()
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/kernel/linux/linux-5.10/drivers/pinctrl/
Dpinctrl-rockchip.c348 void (*pull_calc_reg)(struct rockchip_pin_bank *bank,
351 void (*drv_calc_reg)(struct rockchip_pin_bank *bank,
354 int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank,
780 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, in rockchip_get_recalced_mux() argument
783 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_recalced_mux()
790 if (data->num == bank->bank_num && in rockchip_get_recalced_mux()
1397 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, in rockchip_get_mux_route() argument
1400 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_mux_route()
1407 if ((data->bank_num == bank->bank_num) && in rockchip_get_mux_route()
1422 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) in rockchip_get_mux() argument
[all …]
/kernel/linux/linux-4.19/arch/x86/kernel/cpu/mcheck/
Dmce_amd.c120 static enum smca_bank_types smca_get_bank_type(unsigned int bank) in smca_get_bank_type() argument
124 if (bank >= MAX_NR_BANKS) in smca_get_bank_type()
127 b = &smca_banks[bank]; in smca_get_bank_type()
193 static void smca_configure(unsigned int bank, unsigned int cpu) in smca_configure() argument
198 u32 smca_config = MSR_AMD64_SMCA_MCx_CONFIG(bank); in smca_configure()
231 if (smca_banks[bank].hwid && smca_banks[bank].hwid->hwid_mcatype != 0) in smca_configure()
234 if (rdmsr_safe(MSR_AMD64_SMCA_MCx_IPID(bank), &low, &high)) { in smca_configure()
235 pr_warn("Failed to read MCA_IPID for bank %d\n", bank); in smca_configure()
245 smca_banks[bank].hwid = s_hwid; in smca_configure()
246 smca_banks[bank].id = low; in smca_configure()
[all …]
/kernel/linux/linux-5.10/drivers/net/phy/mscc/
Dmscc_macsec.c23 enum macsec_bank bank, u32 reg) in vsc8584_macsec_phy_read() argument
34 MSCC_PHY_MACSEC_20_TARGET(bank >> 2)); in vsc8584_macsec_phy_read()
36 if (bank >> 2 == 0x1) in vsc8584_macsec_phy_read()
38 bank &= 0x3; in vsc8584_macsec_phy_read()
40 bank = 0; in vsc8584_macsec_phy_read()
45 MSCC_PHY_MACSEC_19_TARGET(bank)); in vsc8584_macsec_phy_read()
62 enum macsec_bank bank, u32 reg, u32 val) in vsc8584_macsec_phy_write() argument
72 MSCC_PHY_MACSEC_20_TARGET(bank >> 2)); in vsc8584_macsec_phy_write()
74 if ((bank >> 2 == 0x1) || (bank >> 2 == 0x3)) in vsc8584_macsec_phy_write()
75 bank &= 0x3; in vsc8584_macsec_phy_write()
[all …]
/kernel/linux/linux-4.19/arch/unicore32/include/asm/
Dmemblock.h29 struct membank bank[NR_BANKS]; member
37 #define bank_pfn_start(bank) __phys_to_pfn((bank)->start) argument
38 #define bank_pfn_end(bank) __phys_to_pfn((bank)->start + (bank)->size) argument
39 #define bank_pfn_size(bank) ((bank)->size >> PAGE_SHIFT) argument
40 #define bank_phys_start(bank) ((bank)->start) argument
41 #define bank_phys_end(bank) ((bank)->start + (bank)->size) argument
42 #define bank_phys_size(bank) ((bank)->size) argument
/kernel/linux/linux-4.19/drivers/bus/
Duniphier-system-bus.c44 struct uniphier_system_bus_bank bank[UNIPHIER_SBC_NR_BANKS]; member
48 int bank, u32 addr, u64 paddr, u32 size) in uniphier_system_bus_add_bank() argument
54 bank, addr, paddr, size); in uniphier_system_bus_add_bank()
56 if (bank >= ARRAY_SIZE(priv->bank)) { in uniphier_system_bus_add_bank()
57 dev_err(priv->dev, "unsupported bank number %d\n", bank); in uniphier_system_bus_add_bank()
61 if (priv->bank[bank].base || priv->bank[bank].end) { in uniphier_system_bus_add_bank()
63 "range for bank %d has already been specified\n", bank); in uniphier_system_bus_add_bank()
95 priv->bank[bank].base = paddr; in uniphier_system_bus_add_bank()
96 priv->bank[bank].end = end; in uniphier_system_bus_add_bank()
99 bank, priv->bank[bank].base, priv->bank[bank].end); in uniphier_system_bus_add_bank()
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