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Searched refs:c8 (Results 1 – 25 of 123) sorted by relevance

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/kernel/linux/linux-5.10/fs/cifs/
Dsmbencrypt.c93 E_P24(unsigned char *p21, const unsigned char *c8, unsigned char *p24) in E_P24() argument
97 rc = smbhash(p24, c8, p21); in E_P24()
100 rc = smbhash(p24 + 8, c8, p21 + 7); in E_P24()
103 rc = smbhash(p24 + 16, c8, p21 + 14); in E_P24()
144 SMBencrypt(unsigned char *passwd, const unsigned char *c8, unsigned char *p24) in SMBencrypt() argument
159 rc = E_P24(p21, c8, p24); in SMBencrypt()
192 SMBNTencrypt(unsigned char *passwd, unsigned char *c8, unsigned char *p24, in SMBNTencrypt() argument
208 rc = E_P24(p21, c8, p24); in SMBNTencrypt()
/kernel/linux/linux-4.19/fs/cifs/
Dsmbencrypt.c105 E_P24(unsigned char *p21, const unsigned char *c8, unsigned char *p24) in E_P24() argument
109 rc = smbhash(p24, c8, p21); in E_P24()
112 rc = smbhash(p24 + 8, c8, p21 + 7); in E_P24()
115 rc = smbhash(p24 + 16, c8, p21 + 14); in E_P24()
156 SMBencrypt(unsigned char *passwd, const unsigned char *c8, unsigned char *p24) in SMBencrypt() argument
171 rc = E_P24(p21, c8, p24); in SMBencrypt()
204 SMBNTencrypt(unsigned char *passwd, unsigned char *c8, unsigned char *p24, in SMBNTencrypt() argument
220 rc = E_P24(p21, c8, p24); in SMBNTencrypt()
/kernel/linux/linux-5.10/arch/arm/mm/
Dtlb-v7.S47 ALT_SMP(mcr p15, 0, r0, c8, c3, 3) @ TLB invalidate U MVA all ASID (shareable)
49 ALT_SMP(mcr p15, 0, r0, c8, c3, 1) @ TLB invalidate U MVA (shareable)
51 ALT_UP(mcr p15, 0, r0, c8, c7, 1) @ TLB invalidate U MVA
76 ALT_SMP(mcr p15, 0, r0, c8, c3, 3) @ TLB invalidate U MVA all ASID (shareable)
78 ALT_SMP(mcr p15, 0, r0, c8, c3, 1) @ TLB invalidate U MVA (shareable)
80 ALT_UP(mcr p15, 0, r0, c8, c7, 1) @ TLB invalidate U MVA
Dtlb-v6.S46 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA (was 1)
48 mcrne p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA (was 1)
50 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA (was 1)
75 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA
76 mcr p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA
78 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA
Dtlb-v4wb.S38 mcrne p15, 0, r3, c8, c5, 0 @ invalidate I TLB
41 1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
61 mcr p15, 0, r3, c8, c5, 0 @ invalidate I TLB
62 1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
Dtlb-v4wbi.S40 mcrne p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry
41 mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
52 1: mcr p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry
53 mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
Dproc-arm720.S68 mcr p15, 0, r1, c8, c7, 0 @ flush TLB (v4)
95 mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
110 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
138 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
Dproc-sa110.S68 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
98 mcr p15, 0, r0, c15, c8, 2 @ Wait for interrupt, cache aligned
138 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
165 mcr p15, 0, r10, c8, c7 @ invalidate I,D TLBs on v4
Dproc-sa1100.S76 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
110 mcr p15, 0, r0, c15, c8, 2 @ wait for interrupt
149 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
185 mcr p15, 0, ip, c8, c7, 0 @ flush I+D TLBs
204 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
Dtlb-fa.S43 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry
56 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry
Dproc-fa526.S61 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
113 mcr p15, 0, ip, c8, c7, 0 @ invalidate UTLB
140 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
/kernel/linux/linux-4.19/arch/arm/mm/
Dtlb-v7.S50 ALT_SMP(mcr p15, 0, r0, c8, c3, 3) @ TLB invalidate U MVA all ASID (shareable)
52 ALT_SMP(mcr p15, 0, r0, c8, c3, 1) @ TLB invalidate U MVA (shareable)
54 ALT_UP(mcr p15, 0, r0, c8, c7, 1) @ TLB invalidate U MVA
79 ALT_SMP(mcr p15, 0, r0, c8, c3, 3) @ TLB invalidate U MVA all ASID (shareable)
81 ALT_SMP(mcr p15, 0, r0, c8, c3, 1) @ TLB invalidate U MVA (shareable)
83 ALT_UP(mcr p15, 0, r0, c8, c7, 1) @ TLB invalidate U MVA
Dtlb-v6.S49 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA (was 1)
51 mcrne p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA (was 1)
53 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA (was 1)
78 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA
79 mcr p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA
81 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA
Dtlb-v4wb.S41 mcrne p15, 0, r3, c8, c5, 0 @ invalidate I TLB
44 1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
64 mcr p15, 0, r3, c8, c5, 0 @ invalidate I TLB
65 1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
Dtlb-v4wbi.S43 mcrne p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry
44 mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
55 1: mcr p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry
56 mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
Dproc-arm720.S82 mcr p15, 0, r1, c8, c7, 0 @ flush TLB (v4)
109 mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
124 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
152 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
Dproc-sa110.S71 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
101 mcr p15, 0, r0, c15, c8, 2 @ Wait for interrupt, cache aligned
141 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
168 mcr p15, 0, r10, c8, c7 @ invalidate I,D TLBs on v4
Dproc-sa1100.S79 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
113 mcr p15, 0, r0, c15, c8, 2 @ wait for interrupt
152 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
188 mcr p15, 0, ip, c8, c7, 0 @ flush I+D TLBs
207 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
Dtlb-fa.S46 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry
59 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry
Dproc-fa526.S66 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
118 mcr p15, 0, ip, c8, c7, 0 @ invalidate UTLB
145 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
/kernel/linux/linux-4.19/arch/arm/include/asm/hardware/
Dcp14.h73 #define RCP14_DBGBVR8() MRC14(0, c0, c8, 4)
89 #define RCP14_DBGBCR8() MRC14(0, c0, c8, 5)
105 #define RCP14_DBGWVR8() MRC14(0, c0, c8, 6)
121 #define RCP14_DBGWCR8() MRC14(0, c0, c8, 7)
138 #define RCP14_DBGBXVR8() MRC14(0, c1, c8, 1)
153 #define RCP14_DBGCLAIMSET() MRC14(0, c7, c8, 6)
178 #define WCP14_DBGBVR8(val) MCR14(val, 0, c0, c8, 4)
194 #define WCP14_DBGBCR8(val) MCR14(val, 0, c0, c8, 5)
210 #define WCP14_DBGWVR8(val) MCR14(val, 0, c0, c8, 6)
226 #define WCP14_DBGWCR8(val) MCR14(val, 0, c0, c8, 7)
[all …]
/kernel/linux/linux-5.10/arch/arm/include/asm/hardware/
Dcp14.h65 #define RCP14_DBGBVR8() MRC14(0, c0, c8, 4)
81 #define RCP14_DBGBCR8() MRC14(0, c0, c8, 5)
97 #define RCP14_DBGWVR8() MRC14(0, c0, c8, 6)
113 #define RCP14_DBGWCR8() MRC14(0, c0, c8, 7)
130 #define RCP14_DBGBXVR8() MRC14(0, c1, c8, 1)
145 #define RCP14_DBGCLAIMSET() MRC14(0, c7, c8, 6)
170 #define WCP14_DBGBVR8(val) MCR14(val, 0, c0, c8, 4)
186 #define WCP14_DBGBCR8(val) MCR14(val, 0, c0, c8, 5)
202 #define WCP14_DBGWVR8(val) MCR14(val, 0, c0, c8, 6)
218 #define WCP14_DBGWCR8(val) MCR14(val, 0, c0, c8, 7)
[all …]
/kernel/linux/linux-4.19/arch/arm/include/asm/
Dkvm_hyp.h73 #define ATS1CPR __ACCESS_CP15(c7, 0, c8, 0)
74 #define TLBIALLIS __ACCESS_CP15(c8, 0, c3, 0)
75 #define TLBIALL __ACCESS_CP15(c8, 0, c7, 0)
76 #define TLBIALLNSNHIS __ACCESS_CP15(c8, 4, c3, 4)
/kernel/linux/linux-4.19/arch/alpha/include/asm/
Dstring.h39 unsigned long c8 = (c & 0xff) * 0x0101010101010101UL; in __memset() local
40 return __constant_c_memset(s, c8, n); in __memset()
/kernel/linux/linux-5.10/arch/alpha/include/asm/
Dstring.h39 unsigned long c8 = (c & 0xff) * 0x0101010101010101UL; in __memset() local
40 return __constant_c_memset(s, c8, n); in __memset()

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