| /kernel/linux/linux-4.19/drivers/gpu/drm/amd/amdgpu/ |
| D | gfxhub_v1_0.c | 105 uint32_t tmp; in gfxhub_v1_0_init_tlb_regs() local
108 tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL); in gfxhub_v1_0_init_tlb_regs()
110 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v1_0_init_tlb_regs()
111 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in gfxhub_v1_0_init_tlb_regs()
112 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in gfxhub_v1_0_init_tlb_regs()
114 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in gfxhub_v1_0_init_tlb_regs()
116 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); in gfxhub_v1_0_init_tlb_regs()
117 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in gfxhub_v1_0_init_tlb_regs()
119 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1); in gfxhub_v1_0_init_tlb_regs()
121 WREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp); in gfxhub_v1_0_init_tlb_regs()
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| D | mmhub_v1_0.c | 83 uint32_t tmp; in mmhub_v1_0_init_system_aperture_regs() local
110 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2); in mmhub_v1_0_init_system_aperture_regs()
111 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2, in mmhub_v1_0_init_system_aperture_regs()
113 WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2, tmp); in mmhub_v1_0_init_system_aperture_regs()
118 uint32_t tmp; in mmhub_v1_0_init_tlb_regs() local
121 tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL); in mmhub_v1_0_init_tlb_regs()
123 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v1_0_init_tlb_regs()
124 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in mmhub_v1_0_init_tlb_regs()
125 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in mmhub_v1_0_init_tlb_regs()
127 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in mmhub_v1_0_init_tlb_regs()
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/ |
| D | gfxhub_v1_0.c | 121 uint32_t tmp; in gfxhub_v1_0_init_tlb_regs() local
124 tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL); in gfxhub_v1_0_init_tlb_regs()
126 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v1_0_init_tlb_regs()
127 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in gfxhub_v1_0_init_tlb_regs()
128 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in gfxhub_v1_0_init_tlb_regs()
130 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in gfxhub_v1_0_init_tlb_regs()
132 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); in gfxhub_v1_0_init_tlb_regs()
133 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in gfxhub_v1_0_init_tlb_regs()
135 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1); in gfxhub_v1_0_init_tlb_regs()
137 WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp); in gfxhub_v1_0_init_tlb_regs()
[all …]
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| D | gfxhub_v2_0.c | 189 uint32_t tmp; in gfxhub_v2_0_init_tlb_regs() local
192 tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); in gfxhub_v2_0_init_tlb_regs()
194 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v2_0_init_tlb_regs()
195 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in gfxhub_v2_0_init_tlb_regs()
196 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v2_0_init_tlb_regs()
198 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v2_0_init_tlb_regs()
200 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); in gfxhub_v2_0_init_tlb_regs()
201 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v2_0_init_tlb_regs()
204 WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp); in gfxhub_v2_0_init_tlb_regs()
209 uint32_t tmp; in gfxhub_v2_0_init_cache_regs() local
[all …]
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| D | gfxhub_v2_1.c | 187 uint32_t tmp; in gfxhub_v2_1_init_tlb_regs() local
190 tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); in gfxhub_v2_1_init_tlb_regs()
192 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v2_1_init_tlb_regs()
193 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in gfxhub_v2_1_init_tlb_regs()
194 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v2_1_init_tlb_regs()
196 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v2_1_init_tlb_regs()
198 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); in gfxhub_v2_1_init_tlb_regs()
199 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, in gfxhub_v2_1_init_tlb_regs()
202 WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp); in gfxhub_v2_1_init_tlb_regs()
207 uint32_t tmp; in gfxhub_v2_1_init_cache_regs() local
[all …]
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| D | mmhub_v2_0.c | 196 uint32_t tmp; in mmhub_v2_0_init_system_aperture_regs() local
225 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2); in mmhub_v2_0_init_system_aperture_regs()
226 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2, in mmhub_v2_0_init_system_aperture_regs()
228 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2, tmp); in mmhub_v2_0_init_system_aperture_regs()
233 uint32_t tmp; in mmhub_v2_0_init_tlb_regs() local
236 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v2_0_init_tlb_regs()
238 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v2_0_init_tlb_regs()
239 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in mmhub_v2_0_init_tlb_regs()
240 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, in mmhub_v2_0_init_tlb_regs()
242 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, in mmhub_v2_0_init_tlb_regs()
[all …]
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| D | mmhub_v1_0.c | 88 uint32_t tmp; in mmhub_v1_0_init_system_aperture_regs() local
130 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2); in mmhub_v1_0_init_system_aperture_regs()
131 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2, in mmhub_v1_0_init_system_aperture_regs()
133 WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2, tmp); in mmhub_v1_0_init_system_aperture_regs()
138 uint32_t tmp; in mmhub_v1_0_init_tlb_regs() local
141 tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL); in mmhub_v1_0_init_tlb_regs()
143 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v1_0_init_tlb_regs()
144 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in mmhub_v1_0_init_tlb_regs()
145 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in mmhub_v1_0_init_tlb_regs()
147 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in mmhub_v1_0_init_tlb_regs()
[all …]
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| /kernel/linux/linux-5.10/drivers/staging/fbtft/ |
| D | fb_ssd1331.c | 133 unsigned long tmp[GAMMA_NUM * GAMMA_LEN]; in set_gamma() local
144 tmp[i] = acc; in set_gamma()
154 tmp[0], tmp[1], tmp[2], tmp[3], tmp[4], tmp[5], tmp[6], in set_gamma()
155 tmp[7], tmp[8], tmp[9], tmp[10], tmp[11], tmp[12], tmp[13], in set_gamma()
156 tmp[14], tmp[15], tmp[16], tmp[17], tmp[18], tmp[19], tmp[20], in set_gamma()
157 tmp[21], tmp[22], tmp[23], tmp[24], tmp[25], tmp[26], tmp[27], in set_gamma()
158 tmp[28], tmp[29], tmp[30], tmp[31], tmp[32], tmp[33], tmp[34], in set_gamma()
159 tmp[35], tmp[36], tmp[37], tmp[38], tmp[39], tmp[40], tmp[41], in set_gamma()
160 tmp[42], tmp[43], tmp[44], tmp[45], tmp[46], tmp[47], tmp[48], in set_gamma()
161 tmp[49], tmp[50], tmp[51], tmp[52], tmp[53], tmp[54], tmp[55], in set_gamma()
[all …]
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| D | fb_ssd1351.c | 122 unsigned long tmp[GAMMA_NUM * GAMMA_LEN]; in set_gamma() local
133 tmp[i] = acc; in set_gamma()
143 tmp[0], tmp[1], tmp[2], tmp[3], in set_gamma()
144 tmp[4], tmp[5], tmp[6], tmp[7], in set_gamma()
145 tmp[8], tmp[9], tmp[10], tmp[11], in set_gamma()
146 tmp[12], tmp[13], tmp[14], tmp[15], in set_gamma()
147 tmp[16], tmp[17], tmp[18], tmp[19], in set_gamma()
148 tmp[20], tmp[21], tmp[22], tmp[23], in set_gamma()
149 tmp[24], tmp[25], tmp[26], tmp[27], in set_gamma()
150 tmp[28], tmp[29], tmp[30], tmp[31], in set_gamma()
[all …]
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| /kernel/linux/linux-4.19/drivers/staging/fbtft/ |
| D | fb_ssd1331.c | 134 unsigned long tmp[GAMMA_NUM * GAMMA_LEN]; in set_gamma() local
145 tmp[i] = acc; in set_gamma()
155 tmp[0], tmp[1], tmp[2], tmp[3], tmp[4], tmp[5], tmp[6], in set_gamma()
156 tmp[7], tmp[8], tmp[9], tmp[10], tmp[11], tmp[12], tmp[13], in set_gamma()
157 tmp[14], tmp[15], tmp[16], tmp[17], tmp[18], tmp[19], tmp[20], in set_gamma()
158 tmp[21], tmp[22], tmp[23], tmp[24], tmp[25], tmp[26], tmp[27], in set_gamma()
159 tmp[28], tmp[29], tmp[30], tmp[31], tmp[32], tmp[33], tmp[34], in set_gamma()
160 tmp[35], tmp[36], tmp[37], tmp[38], tmp[39], tmp[40], tmp[41], in set_gamma()
161 tmp[42], tmp[43], tmp[44], tmp[45], tmp[46], tmp[47], tmp[48], in set_gamma()
162 tmp[49], tmp[50], tmp[51], tmp[52], tmp[53], tmp[54], tmp[55], in set_gamma()
[all …]
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| D | fb_ssd1351.c | 123 unsigned long tmp[GAMMA_NUM * GAMMA_LEN]; in set_gamma() local
134 tmp[i] = acc; in set_gamma()
144 tmp[0], tmp[1], tmp[2], tmp[3], in set_gamma()
145 tmp[4], tmp[5], tmp[6], tmp[7], in set_gamma()
146 tmp[8], tmp[9], tmp[10], tmp[11], in set_gamma()
147 tmp[12], tmp[13], tmp[14], tmp[15], in set_gamma()
148 tmp[16], tmp[17], tmp[18], tmp[19], in set_gamma()
149 tmp[20], tmp[21], tmp[22], tmp[23], in set_gamma()
150 tmp[24], tmp[25], tmp[26], tmp[27], in set_gamma()
151 tmp[28], tmp[29], tmp[30], tmp[31], in set_gamma()
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/radeon/ |
| D | radeon_clocks.c | 200 u32 tmp = RREG32_PLL(RADEON_PPLL_REF_DIV); in radeon_get_clock_info() local
203 (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> R300_PPLL_REF_DIV_ACC_SHIFT; in radeon_get_clock_info()
205 p1pll->reference_div = tmp & RADEON_PPLL_REF_DIV_MASK; in radeon_get_clock_info()
393 uint32_t tmp; in radeon_legacy_set_engine_clock() local
400 tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL); in radeon_legacy_set_engine_clock()
401 tmp &= ~RADEON_DONT_USE_XTALIN; in radeon_legacy_set_engine_clock()
402 WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp); in radeon_legacy_set_engine_clock()
404 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_engine_clock()
405 tmp &= ~RADEON_SCLK_SRC_SEL_MASK; in radeon_legacy_set_engine_clock()
406 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_engine_clock()
[all …]
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| D | vce_v2_0.c | 40 u32 tmp; in vce_v2_0_set_sw_cg() local
43 tmp = RREG32(VCE_CLOCK_GATING_B); in vce_v2_0_set_sw_cg()
44 tmp |= 0xe70000; in vce_v2_0_set_sw_cg()
45 WREG32(VCE_CLOCK_GATING_B, tmp); in vce_v2_0_set_sw_cg()
47 tmp = RREG32(VCE_UENC_CLOCK_GATING); in vce_v2_0_set_sw_cg()
48 tmp |= 0xff000000; in vce_v2_0_set_sw_cg()
49 WREG32(VCE_UENC_CLOCK_GATING, tmp); in vce_v2_0_set_sw_cg()
51 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); in vce_v2_0_set_sw_cg()
52 tmp &= ~0x3fc; in vce_v2_0_set_sw_cg()
53 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); in vce_v2_0_set_sw_cg()
[all …]
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| D | rs400.c | 67 uint32_t tmp; in rs400_gart_tlb_flush() local
72 tmp = RREG32_MC(RS480_GART_CACHE_CNTRL); in rs400_gart_tlb_flush()
73 if ((tmp & RS480_GART_CACHE_INVALIDATE) == 0) in rs400_gart_tlb_flush()
115 uint32_t tmp; in rs400_gart_enable() local
117 tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); in rs400_gart_enable()
118 tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS; in rs400_gart_enable()
119 WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp); in rs400_gart_enable()
154 tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16); in rs400_gart_enable()
155 tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16); in rs400_gart_enable()
157 WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp); in rs400_gart_enable()
[all …]
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| /kernel/linux/linux-4.19/drivers/gpu/drm/radeon/ |
| D | radeon_clocks.c | 196 u32 tmp = RREG32_PLL(RADEON_PPLL_REF_DIV); in radeon_get_clock_info() local
199 (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> R300_PPLL_REF_DIV_ACC_SHIFT; in radeon_get_clock_info()
201 p1pll->reference_div = tmp & RADEON_PPLL_REF_DIV_MASK; in radeon_get_clock_info()
389 uint32_t tmp; in radeon_legacy_set_engine_clock() local
396 tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL); in radeon_legacy_set_engine_clock()
397 tmp &= ~RADEON_DONT_USE_XTALIN; in radeon_legacy_set_engine_clock()
398 WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp); in radeon_legacy_set_engine_clock()
400 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_engine_clock()
401 tmp &= ~RADEON_SCLK_SRC_SEL_MASK; in radeon_legacy_set_engine_clock()
402 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_engine_clock()
[all …]
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| D | vce_v2_0.c | 40 u32 tmp; in vce_v2_0_set_sw_cg() local
43 tmp = RREG32(VCE_CLOCK_GATING_B); in vce_v2_0_set_sw_cg()
44 tmp |= 0xe70000; in vce_v2_0_set_sw_cg()
45 WREG32(VCE_CLOCK_GATING_B, tmp); in vce_v2_0_set_sw_cg()
47 tmp = RREG32(VCE_UENC_CLOCK_GATING); in vce_v2_0_set_sw_cg()
48 tmp |= 0xff000000; in vce_v2_0_set_sw_cg()
49 WREG32(VCE_UENC_CLOCK_GATING, tmp); in vce_v2_0_set_sw_cg()
51 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); in vce_v2_0_set_sw_cg()
52 tmp &= ~0x3fc; in vce_v2_0_set_sw_cg()
53 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); in vce_v2_0_set_sw_cg()
[all …]
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| D | rs400.c | 62 uint32_t tmp; in rs400_gart_tlb_flush() local
67 tmp = RREG32_MC(RS480_GART_CACHE_CNTRL); in rs400_gart_tlb_flush()
68 if ((tmp & RS480_GART_CACHE_INVALIDATE) == 0) in rs400_gart_tlb_flush()
110 uint32_t tmp; in rs400_gart_enable() local
112 tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); in rs400_gart_enable()
113 tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS; in rs400_gart_enable()
114 WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp); in rs400_gart_enable()
149 tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16); in rs400_gart_enable()
150 tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16); in rs400_gart_enable()
152 WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp); in rs400_gart_enable()
[all …]
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| /kernel/linux/linux-5.10/drivers/phy/mediatek/ |
| D | phy-mtk-tphy.c | 331 u32 tmp; in hs_slew_rate_calibrate() local
338 tmp = readl(com + U3P_USBPHYACR5); in hs_slew_rate_calibrate()
339 tmp |= PA5_RG_U2_HSTX_SRCAL_EN; in hs_slew_rate_calibrate()
340 writel(tmp, com + U3P_USBPHYACR5); in hs_slew_rate_calibrate()
344 tmp = readl(fmreg + U3P_U2FREQ_FMMONR1); in hs_slew_rate_calibrate()
345 tmp |= P2F_RG_FRCK_EN; in hs_slew_rate_calibrate()
346 writel(tmp, fmreg + U3P_U2FREQ_FMMONR1); in hs_slew_rate_calibrate()
349 tmp = readl(fmreg + U3P_U2FREQ_FMCR0); in hs_slew_rate_calibrate()
350 tmp &= ~(P2F_RG_CYCLECNT | P2F_RG_MONCLK_SEL); in hs_slew_rate_calibrate()
351 tmp |= P2F_RG_CYCLECNT_VAL(U3P_FM_DET_CYCLE_CNT); in hs_slew_rate_calibrate()
[all …]
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| /kernel/linux/linux-4.19/drivers/phy/mediatek/ |
| D | phy-mtk-tphy.c | 326 u32 tmp; in hs_slew_rate_calibrate() local
333 tmp = readl(com + U3P_USBPHYACR5); in hs_slew_rate_calibrate()
334 tmp |= PA5_RG_U2_HSTX_SRCAL_EN; in hs_slew_rate_calibrate()
335 writel(tmp, com + U3P_USBPHYACR5); in hs_slew_rate_calibrate()
339 tmp = readl(fmreg + U3P_U2FREQ_FMMONR1); in hs_slew_rate_calibrate()
340 tmp |= P2F_RG_FRCK_EN; in hs_slew_rate_calibrate()
341 writel(tmp, fmreg + U3P_U2FREQ_FMMONR1); in hs_slew_rate_calibrate()
344 tmp = readl(fmreg + U3P_U2FREQ_FMCR0); in hs_slew_rate_calibrate()
345 tmp &= ~(P2F_RG_CYCLECNT | P2F_RG_MONCLK_SEL); in hs_slew_rate_calibrate()
346 tmp |= P2F_RG_CYCLECNT_VAL(U3P_FM_DET_CYCLE_CNT); in hs_slew_rate_calibrate()
[all …]
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| /kernel/linux/linux-5.10/drivers/scsi/mvsas/ |
| D | mv_64xx.c | 31 u32 tmp; in mvs_64xx_enable_xmt() local
33 tmp = mr32(MVS_PCS); in mvs_64xx_enable_xmt()
35 tmp |= 1 << (phy_id + PCS_EN_PORT_XMT_SHIFT); in mvs_64xx_enable_xmt()
37 tmp |= 1 << (phy_id + PCS_EN_PORT_XMT_SHIFT2); in mvs_64xx_enable_xmt()
38 mw32(MVS_PCS, tmp); in mvs_64xx_enable_xmt()
70 u32 reg, tmp; in mvs_64xx_stp_reset() local
81 tmp = reg; in mvs_64xx_stp_reset()
83 tmp |= (1U << phy_id) << PCTL_LINK_OFFS; in mvs_64xx_stp_reset()
85 tmp |= (1U << (phy_id - MVS_SOC_PORTS)) << PCTL_LINK_OFFS; in mvs_64xx_stp_reset()
89 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, tmp); in mvs_64xx_stp_reset()
[all …]
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| /kernel/linux/linux-4.19/drivers/scsi/mvsas/ |
| D | mv_64xx.c | 47 u32 tmp; in mvs_64xx_enable_xmt() local
49 tmp = mr32(MVS_PCS); in mvs_64xx_enable_xmt()
51 tmp |= 1 << (phy_id + PCS_EN_PORT_XMT_SHIFT); in mvs_64xx_enable_xmt()
53 tmp |= 1 << (phy_id + PCS_EN_PORT_XMT_SHIFT2); in mvs_64xx_enable_xmt()
54 mw32(MVS_PCS, tmp); in mvs_64xx_enable_xmt()
86 u32 reg, tmp; in mvs_64xx_stp_reset() local
97 tmp = reg; in mvs_64xx_stp_reset()
99 tmp |= (1U << phy_id) << PCTL_LINK_OFFS; in mvs_64xx_stp_reset()
101 tmp |= (1U << (phy_id - MVS_SOC_PORTS)) << PCTL_LINK_OFFS; in mvs_64xx_stp_reset()
105 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, tmp); in mvs_64xx_stp_reset()
[all …]
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| /kernel/linux/linux-5.10/drivers/video/fbdev/kyro/ |
| D | STG4000Ramdac.c | 29 u32 tmp = 0; in InitialiseRamdac() local
35 tmp = STG_READ_REG(SoftwareReset); in InitialiseRamdac()
37 if (tmp & 0x1) { in InitialiseRamdac()
39 STG_WRITE_REG(SoftwareReset, tmp); in InitialiseRamdac()
43 tmp = STG_READ_REG(DACPixelFormat); in InitialiseRamdac()
53 tmp |= _16BPP; in InitialiseRamdac()
60 tmp |= _32BPP; in InitialiseRamdac()
67 STG_WRITE_REG(DACPixelFormat, tmp); in InitialiseRamdac()
76 tmp = STG_READ_REG(DACPrimSize); in InitialiseRamdac()
79 tmp |= in InitialiseRamdac()
[all …]
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| D | STG4000OverlayDevice.c | 81 u32 tmp; in ResetOverlayRegisters() local
84 tmp = STG_READ_REG(DACOverlayAddr); in ResetOverlayRegisters()
87 STG_WRITE_REG(DACOverlayAddr, tmp); in ResetOverlayRegisters()
90 tmp = STG_READ_REG(DACOverlayUAddr); in ResetOverlayRegisters()
92 STG_WRITE_REG(DACOverlayUAddr, tmp); in ResetOverlayRegisters()
95 tmp = STG_READ_REG(DACOverlayVAddr); in ResetOverlayRegisters()
97 STG_WRITE_REG(DACOverlayVAddr, tmp); in ResetOverlayRegisters()
100 tmp = STG_READ_REG(DACOverlaySize); in ResetOverlayRegisters()
103 STG_WRITE_REG(DACOverlaySize, tmp); in ResetOverlayRegisters()
106 tmp = STG4000_NO_DECIMATION; in ResetOverlayRegisters()
[all …]
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| /kernel/linux/linux-4.19/drivers/video/fbdev/kyro/ |
| D | STG4000Ramdac.c | 29 u32 tmp = 0; in InitialiseRamdac() local
35 tmp = STG_READ_REG(SoftwareReset); in InitialiseRamdac()
37 if (tmp & 0x1) { in InitialiseRamdac()
39 STG_WRITE_REG(SoftwareReset, tmp); in InitialiseRamdac()
43 tmp = STG_READ_REG(DACPixelFormat); in InitialiseRamdac()
53 tmp |= _16BPP; in InitialiseRamdac()
60 tmp |= _32BPP; in InitialiseRamdac()
67 STG_WRITE_REG(DACPixelFormat, tmp); in InitialiseRamdac()
76 tmp = STG_READ_REG(DACPrimSize); in InitialiseRamdac()
79 tmp |= in InitialiseRamdac()
[all …]
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| /kernel/linux/linux-5.10/arch/csky/kernel/probes/ |
| D | simulate-insn.c | 125 unsigned long tmp = (opcode >> 2) & 0xf; in simulate_jmp16() local
127 csky_insn_reg_get_val(regs, tmp, &tmp); in simulate_jmp16()
129 instruction_pointer_set(regs, tmp & 0xfffffffe); in simulate_jmp16()
135 unsigned long tmp = opcode & 0x1f; in simulate_jmp32() local
137 csky_insn_reg_get_val(regs, tmp, &tmp); in simulate_jmp32()
139 instruction_pointer_set(regs, tmp & 0xfffffffe); in simulate_jmp32()
145 unsigned long tmp = (opcode >> 2) & 0xf; in simulate_jsr16() local
147 csky_insn_reg_get_val(regs, tmp, &tmp); in simulate_jsr16()
151 instruction_pointer_set(regs, tmp & 0xfffffffe); in simulate_jsr16()
157 unsigned long tmp = opcode & 0x1f; in simulate_jsr32() local
[all …]
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