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Searched refs:CLK_TOP_AUD_INTBUS_SEL (Results 1 – 4 of 4) sorted by relevance

/third_party/uboot/u-boot-2020.01/include/dt-bindings/clock/
Dmt7629-clk.h104 #define CLK_TOP_AUD_INTBUS_SEL 90 macro
Dmt8516-clk.h82 #define CLK_TOP_AUD_INTBUS_SEL 58 macro
/third_party/uboot/u-boot-2020.01/drivers/clk/mediatek/
Dclk-mt7629.c135 FACTOR1(CLK_TOP_F_FAUD_INTBUS, CLK_TOP_AUD_INTBUS_SEL, 1, 1),
389 MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x80, 8, 2, 15),
Dclk-mt8516.c504 MUX(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x000, 27, 3),