Searched refs:CLK_TOP_PCIE0_MCU_SEL (Results 1 – 2 of 2) sorted by relevance
116 #define CLK_TOP_PCIE0_MCU_SEL 102 macro
408 MUX_GATE(CLK_TOP_PCIE0_MCU_SEL, scp_parents, 0xB0, 8, 2, 15),