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Searched refs:CLK_TOP_UART_SEL (Results 1 – 6 of 6) sorted by relevance

/third_party/uboot/u-boot-2020.01/arch/arm/dts/
Dmt7623.dtsi192 clocks = <&topckgen CLK_TOP_UART_SEL>,
203 clocks = <&topckgen CLK_TOP_UART_SEL>,
214 clocks = <&topckgen CLK_TOP_UART_SEL>,
226 clocks = <&topckgen CLK_TOP_UART_SEL>,
Dmt7629.dtsi183 clocks = <&topckgen CLK_TOP_UART_SEL>,
197 clocks = <&topckgen CLK_TOP_UART_SEL>,
210 clocks = <&topckgen CLK_TOP_UART_SEL>,
/third_party/uboot/u-boot-2020.01/include/dt-bindings/clock/
Dmt7629-clk.h95 #define CLK_TOP_UART_SEL 81 macro
Dmt7623-clk.h109 #define CLK_TOP_UART_SEL 95 macro
/third_party/uboot/u-boot-2020.01/drivers/clk/mediatek/
Dclk-mt7629.c376 MUX_GATE(CLK_TOP_UART_SEL, uart_parents, 0x60, 0, 1, 7),
Dclk-mt7623.c520 MUX_GATE(CLK_TOP_UART_SEL, uart_parents, 0x60, 0, 1, 7),