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Searched refs:CONFIG_SYS_SDRAM_BASE (Results 1 – 25 of 634) sorted by relevance

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/third_party/uboot/u-boot-2020.01/include/configs/
Dexynos5-common.h52 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
53 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000)
54 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
58 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
60 #define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
62 #define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
64 #define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
66 #define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
68 #define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
70 #define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
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Dexynos7420-common.h45 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
47 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
49 #define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
51 #define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
53 #define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
55 #define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
57 #define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
59 #define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
61 #define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
Dsmdkv310.h23 #define CONFIG_SYS_SDRAM_BASE 0x40000000 macro
45 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
46 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x6000000)
47 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
51 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
53 #define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
55 #define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
57 #define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
Dsmdkc100.h28 #define CONFIG_SYS_SDRAM_BASE 0x30000000 macro
113 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
114 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5e00000)
115 #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
118 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* SDRAM Bank #1 */
136 #define CONFIG_SYS_MAPPED_RAM_BASE CONFIG_SYS_SDRAM_BASE
Dboston.h27 # define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000 macro
29 # define CONFIG_SYS_SDRAM_BASE 0x80000000 macro
36 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x08000000)
38 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0)
39 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x10000000)
Dorigen.h18 #define CONFIG_SYS_SDRAM_BASE 0x40000000 macro
19 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
23 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
24 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x6000000)
25 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
Dat91rm9200ek.h57 #define CONFIG_SYS_SDRAM_BASE 0x20000000 macro
60 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
85 #define CONFIG_SYS_SDRAM CONFIG_SYS_SDRAM_BASE /* address of the SDRAM */
86 #define CONFIG_SYS_SDRAM1 (CONFIG_SYS_SDRAM_BASE+0x80)
156 #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_16M
169 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K \
Dtrats.h25 #define CONFIG_SYS_SDRAM_BASE 0x40000000 macro
26 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
30 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
31 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000)
32 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000)
157 #define CONFIG_SYS_SPL_ARGS_ADDR CONFIG_SYS_SDRAM_BASE + 0x100
Dmalta.h36 # define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000 macro
38 # define CONFIG_SYS_SDRAM_BASE 0x80000000 macro
44 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x01000000)
45 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x00100000)
46 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x00800000)
Dodroid.h24 #define CONFIG_SYS_SDRAM_BASE 0x40000000 macro
26 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
32 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
33 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000)
34 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
Ds5pc210_universal.h20 #define CONFIG_SYS_SDRAM_BASE 0x40000000 macro
21 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
40 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
41 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000)
42 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000)
Dtrats2.h24 #define CONFIG_SYS_SDRAM_BASE 0x40000000 macro
25 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
28 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
29 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000)
30 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
Dr7780mp.h23 #define CONFIG_SYS_SDRAM_BASE (0x08000000) macro
28 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
49 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
88 #define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE
89 #define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE
Ds5p_goni.h25 #define CONFIG_SYS_SDRAM_BASE 0x30000000 macro
150 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
151 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000)
152 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4000000)
155 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* OneDRAM Bank #0 */
Dstmark2.h84 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
104 #define CONFIG_SYS_SDRAM_BASE 0x40000000 macro
107 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x400)
133 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \
154 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
Dmeesc.h58 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM macro
61 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x00100000)
62 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01E00000)
63 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x00100000)
DM5235EVB.h92 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE+0x20000)
118 #define CONFIG_SYS_SDRAM_BASE 0x00000000 macro
121 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
136 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
173 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
Dwork_92105.h30 #define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE macro
32 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + SZ_32K)
35 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K)
37 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_512K \
DM54451EVB.h128 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
153 #define CONFIG_SYS_SDRAM_BASE 0x40000000 macro
162 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
182 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
223 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
/third_party/uboot/u-boot-2020.01/board/freescale/m5275evb/
Dm5275evb.c36 out_be32(&sdp->sdbar0, CONFIG_SYS_SDRAM_BASE); in dram_init()
50 *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; in dram_init()
56 *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; in dram_init()
60 *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; in dram_init()
67 *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; in dram_init()
72 *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; in dram_init()
73 *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; in dram_init()
77 *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; in dram_init()
/third_party/uboot/u-boot-2020.01/arch/arm/mach-at91/arm926ejs/
Dlowlevel_init.S204 .word CONFIG_SYS_SDRAM_BASE
208 .word CONFIG_SYS_SDRAM_BASE
210 .word CONFIG_SYS_SDRAM_BASE
212 .word CONFIG_SYS_SDRAM_BASE
214 .word CONFIG_SYS_SDRAM_BASE
216 .word CONFIG_SYS_SDRAM_BASE
218 .word CONFIG_SYS_SDRAM_BASE
220 .word CONFIG_SYS_SDRAM_BASE
222 .word CONFIG_SYS_SDRAM_BASE
226 .word CONFIG_SYS_SDRAM_BASE
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/third_party/uboot/u-boot-2020.01/drivers/ram/rockchip/
Dsdram_common.c210 writel(0, CONFIG_SYS_SDRAM_BASE); in sdram_detect_col()
211 test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE + in sdram_detect_col()
215 (readl(CONFIG_SYS_SDRAM_BASE) == 0)) in sdram_detect_col()
235 test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE + in sdram_detect_bank()
237 writel(0, CONFIG_SYS_SDRAM_BASE); in sdram_detect_bank()
240 (readl(CONFIG_SYS_SDRAM_BASE) == 0)) in sdram_detect_bank()
258 test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE + in sdram_detect_bg()
260 writel(0, CONFIG_SYS_SDRAM_BASE); in sdram_detect_bg()
263 (readl(CONFIG_SYS_SDRAM_BASE) == 0)) in sdram_detect_bg()
327 writel(0, CONFIG_SYS_SDRAM_BASE); in sdram_detect_row()
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/third_party/uboot/u-boot-2020.01/arch/arm/mach-sunxi/
Ddram_helpers.c33 writel(0, CONFIG_SYS_SDRAM_BASE); in mctl_mem_matches()
34 writel(0xaa55aa55, (ulong)CONFIG_SYS_SDRAM_BASE + offset); in mctl_mem_matches()
37 return readl(CONFIG_SYS_SDRAM_BASE) == in mctl_mem_matches()
38 readl((ulong)CONFIG_SYS_SDRAM_BASE + offset); in mctl_mem_matches()
/third_party/uboot/u-boot-2020.01/arch/arm/mach-rockchip/
Dsdram.c38 size_t top = min((unsigned long)(gd->ram_size + CONFIG_SYS_SDRAM_BASE), in dram_init_banksize()
49 tos_parameter = (struct tos_parameter_t *)(CONFIG_SYS_SDRAM_BASE + in dram_init_banksize()
53 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; in dram_init_banksize()
55 - CONFIG_SYS_SDRAM_BASE; in dram_init_banksize()
61 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; in dram_init_banksize()
64 gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE in dram_init_banksize()
70 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; in dram_init_banksize()
210 unsigned long top = CONFIG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE; in board_get_usable_ram_top()
/third_party/uboot/u-boot-2020.01/cmd/ti/
Dddr3.c19 #define DDR_MIN_ADDR CONFIG_SYS_SDRAM_BASE
246 + CONFIG_SYS_SDRAM_BASE; in is_addr_valid()
248 CONFIG_SYS_SDRAM_BASE; in is_addr_valid()
258 + CONFIG_SYS_SDRAM_BASE; in is_addr_valid()
260 CONFIG_SYS_SDRAM_BASE; in is_addr_valid()
308 if ((start_addr < CONFIG_SYS_SDRAM_BASE) || in do_ddr_test()
309 (start_addr > (CONFIG_SYS_SDRAM_BASE + in do_ddr_test()
311 (end_addr < CONFIG_SYS_SDRAM_BASE) || in do_ddr_test()
312 (end_addr > (CONFIG_SYS_SDRAM_BASE + in do_ddr_test()

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