1 /*
2 * rtl8139.c : U-Boot driver for the RealTek RTL8139
3 *
4 * Masami Komiya (mkomiya@sonare.it)
5 *
6 * Most part is taken from rtl8139.c of etherboot
7 *
8 */
9
10 /* rtl8139.c - etherboot driver for the Realtek 8139 chipset
11
12 ported from the linux driver written by Donald Becker
13 by Rainer Bawidamann (Rainer.Bawidamann@informatik.uni-ulm.de) 1999
14
15 This software may be used and distributed according to the terms
16 of the GNU Public License, incorporated herein by reference.
17
18 changes to the original driver:
19 - removed support for interrupts, switching to polling mode (yuck!)
20 - removed support for the 8129 chip (external MII)
21
22 */
23
24 /*********************************************************************/
25 /* Revision History */
26 /*********************************************************************/
27
28 /*
29 28 Dec 2002 ken_yap@users.sourceforge.net (Ken Yap)
30 Put in virt_to_bus calls to allow Etherboot relocation.
31
32 06 Apr 2001 ken_yap@users.sourceforge.net (Ken Yap)
33 Following email from Hyun-Joon Cha, added a disable routine, otherwise
34 NIC remains live and can crash the kernel later.
35
36 4 Feb 2000 espenlaub@informatik.uni-ulm.de (Klaus Espenlaub)
37 Shuffled things around, removed the leftovers from the 8129 support
38 that was in the Linux driver and added a bit more 8139 definitions.
39 Moved the 8K receive buffer to a fixed, available address outside the
40 0x98000-0x9ffff range. This is a bit of a hack, but currently the only
41 way to make room for the Etherboot features that need substantial amounts
42 of code like the ANSI console support. Currently the buffer is just below
43 0x10000, so this even conforms to the tagged boot image specification,
44 which reserves the ranges 0x00000-0x10000 and 0x98000-0xA0000. My
45 interpretation of this "reserved" is that Etherboot may do whatever it
46 likes, as long as its environment is kept intact (like the BIOS
47 variables). Hopefully fixed rtl_poll() once and for all. The symptoms
48 were that if Etherboot was left at the boot menu for several minutes, the
49 first eth_poll failed. Seems like I am the only person who does this.
50 First of all I fixed the debugging code and then set out for a long bug
51 hunting session. It took me about a week full time work - poking around
52 various places in the driver, reading Don Becker's and Jeff Garzik's Linux
53 driver and even the FreeBSD driver (what a piece of crap!) - and
54 eventually spotted the nasty thing: the transmit routine was acknowledging
55 each and every interrupt pending, including the RxOverrun and RxFIFIOver
56 interrupts. This confused the RTL8139 thoroughly. It destroyed the
57 Rx ring contents by dumping the 2K FIFO contents right where we wanted to
58 get the next packet. Oh well, what fun.
59
60 18 Jan 2000 mdc@thinguin.org (Marty Connor)
61 Drastically simplified error handling. Basically, if any error
62 in transmission or reception occurs, the card is reset.
63 Also, pointed all transmit descriptors to the same buffer to
64 save buffer space. This should decrease driver size and avoid
65 corruption because of exceeding 32K during runtime.
66
67 28 Jul 1999 (Matthias Meixner - meixner@rbg.informatik.tu-darmstadt.de)
68 rtl_poll was quite broken: it used the RxOK interrupt flag instead
69 of the RxBufferEmpty flag which often resulted in very bad
70 transmission performace - below 1kBytes/s.
71
72 */
73
74 #include <common.h>
75 #include <cpu_func.h>
76 #include <malloc.h>
77 #include <net.h>
78 #include <netdev.h>
79 #include <asm/io.h>
80 #include <pci.h>
81
82 #define RTL_TIMEOUT 100000
83
84 /* PCI Tuning Parameters
85 Threshold is bytes transferred to chip before transmission starts. */
86 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
87 #define RX_FIFO_THRESH 4 /* Rx buffer level before first PCI xfer. */
88 #define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 bytes */
89 #define TX_DMA_BURST 4 /* Calculate as 16<<val. */
90 #define NUM_TX_DESC 4 /* Number of Tx descriptor registers. */
91 #define TX_BUF_SIZE ETH_FRAME_LEN /* FCS is added by the chip */
92 #define RX_BUF_LEN_IDX 0 /* 0, 1, 2 is allowed - 8,16,32K rx buffer */
93 #define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX)
94
95 #define DEBUG_TX 0 /* set to 1 to enable debug code */
96 #define DEBUG_RX 0 /* set to 1 to enable debug code */
97
98 #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a)
99 #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
100
101 /* Symbolic offsets to registers. */
102 enum RTL8139_registers {
103 MAC0=0, /* Ethernet hardware address. */
104 MAR0=8, /* Multicast filter. */
105 TxStatus0=0x10, /* Transmit status (four 32bit registers). */
106 TxAddr0=0x20, /* Tx descriptors (also four 32bit). */
107 RxBuf=0x30, RxEarlyCnt=0x34, RxEarlyStatus=0x36,
108 ChipCmd=0x37, RxBufPtr=0x38, RxBufAddr=0x3A,
109 IntrMask=0x3C, IntrStatus=0x3E,
110 TxConfig=0x40, RxConfig=0x44,
111 Timer=0x48, /* general-purpose counter. */
112 RxMissed=0x4C, /* 24 bits valid, write clears. */
113 Cfg9346=0x50, Config0=0x51, Config1=0x52,
114 TimerIntrReg=0x54, /* intr if gp counter reaches this value */
115 MediaStatus=0x58,
116 Config3=0x59,
117 MultiIntr=0x5C,
118 RevisionID=0x5E, /* revision of the RTL8139 chip */
119 TxSummary=0x60,
120 MII_BMCR=0x62, MII_BMSR=0x64, NWayAdvert=0x66, NWayLPAR=0x68,
121 NWayExpansion=0x6A,
122 DisconnectCnt=0x6C, FalseCarrierCnt=0x6E,
123 NWayTestReg=0x70,
124 RxCnt=0x72, /* packet received counter */
125 CSCR=0x74, /* chip status and configuration register */
126 PhyParm1=0x78,TwisterParm=0x7c,PhyParm2=0x80, /* undocumented */
127 /* from 0x84 onwards are a number of power management/wakeup frame
128 * definitions we will probably never need to know about. */
129 };
130
131 enum ChipCmdBits {
132 CmdReset=0x10, CmdRxEnb=0x08, CmdTxEnb=0x04, RxBufEmpty=0x01, };
133
134 /* Interrupt register bits, using my own meaningful names. */
135 enum IntrStatusBits {
136 PCIErr=0x8000, PCSTimeout=0x4000, CableLenChange= 0x2000,
137 RxFIFOOver=0x40, RxUnderrun=0x20, RxOverflow=0x10,
138 TxErr=0x08, TxOK=0x04, RxErr=0x02, RxOK=0x01,
139 };
140 enum TxStatusBits {
141 TxHostOwns=0x2000, TxUnderrun=0x4000, TxStatOK=0x8000,
142 TxOutOfWindow=0x20000000, TxAborted=0x40000000,
143 TxCarrierLost=0x80000000,
144 };
145 enum RxStatusBits {
146 RxMulticast=0x8000, RxPhysical=0x4000, RxBroadcast=0x2000,
147 RxBadSymbol=0x0020, RxRunt=0x0010, RxTooLong=0x0008, RxCRCErr=0x0004,
148 RxBadAlign=0x0002, RxStatusOK=0x0001,
149 };
150
151 enum MediaStatusBits {
152 MSRTxFlowEnable=0x80, MSRRxFlowEnable=0x40, MSRSpeed10=0x08,
153 MSRLinkFail=0x04, MSRRxPauseFlag=0x02, MSRTxPauseFlag=0x01,
154 };
155
156 enum MIIBMCRBits {
157 BMCRReset=0x8000, BMCRSpeed100=0x2000, BMCRNWayEnable=0x1000,
158 BMCRRestartNWay=0x0200, BMCRDuplex=0x0100,
159 };
160
161 enum CSCRBits {
162 CSCR_LinkOKBit=0x0400, CSCR_LinkChangeBit=0x0800,
163 CSCR_LinkStatusBits=0x0f000, CSCR_LinkDownOffCmd=0x003c0,
164 CSCR_LinkDownCmd=0x0f3c0,
165 };
166
167 /* Bits in RxConfig. */
168 enum rx_mode_bits {
169 RxCfgWrap=0x80,
170 AcceptErr=0x20, AcceptRunt=0x10, AcceptBroadcast=0x08,
171 AcceptMulticast=0x04, AcceptMyPhys=0x02, AcceptAllPhys=0x01,
172 };
173
174 static int ioaddr;
175 static unsigned int cur_rx,cur_tx;
176
177 /* The RTL8139 can only transmit from a contiguous, aligned memory block. */
178 static unsigned char tx_buffer[TX_BUF_SIZE] __attribute__((aligned(4)));
179 static unsigned char rx_ring[RX_BUF_LEN+16] __attribute__((aligned(4)));
180
181 static int rtl8139_probe(struct eth_device *dev, bd_t *bis);
182 static int read_eeprom(int location, int addr_len);
183 static void rtl_reset(struct eth_device *dev);
184 static int rtl_transmit(struct eth_device *dev, void *packet, int length);
185 static int rtl_poll(struct eth_device *dev);
186 static void rtl_disable(struct eth_device *dev);
rtl_bcast_addr(struct eth_device * dev,const u8 * bcast_mac,int join)187 static int rtl_bcast_addr(struct eth_device *dev, const u8 *bcast_mac, int join)
188 {
189 return (0);
190 }
191
192 static struct pci_device_id supported[] = {
193 {PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139},
194 {PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_8139},
195 {}
196 };
197
rtl8139_initialize(bd_t * bis)198 int rtl8139_initialize(bd_t *bis)
199 {
200 pci_dev_t devno;
201 int card_number = 0;
202 struct eth_device *dev;
203 u32 iobase;
204 int idx=0;
205
206 while(1){
207 /* Find RTL8139 */
208 if ((devno = pci_find_devices(supported, idx++)) < 0)
209 break;
210
211 pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
212 iobase &= ~0xf;
213
214 debug ("rtl8139: REALTEK RTL8139 @0x%x\n", iobase);
215
216 dev = (struct eth_device *)malloc(sizeof *dev);
217 if (!dev) {
218 printf("Can not allocate memory of rtl8139\n");
219 break;
220 }
221 memset(dev, 0, sizeof(*dev));
222
223 sprintf (dev->name, "RTL8139#%d", card_number);
224
225 dev->priv = (void *) devno;
226 dev->iobase = (int)bus_to_phys(iobase);
227 dev->init = rtl8139_probe;
228 dev->halt = rtl_disable;
229 dev->send = rtl_transmit;
230 dev->recv = rtl_poll;
231 dev->mcast = rtl_bcast_addr;
232
233 eth_register (dev);
234
235 card_number++;
236
237 pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x20);
238
239 udelay (10 * 1000);
240 }
241
242 return card_number;
243 }
244
rtl8139_probe(struct eth_device * dev,bd_t * bis)245 static int rtl8139_probe(struct eth_device *dev, bd_t *bis)
246 {
247 int i;
248 int addr_len;
249 unsigned short *ap = (unsigned short *)dev->enetaddr;
250
251 ioaddr = dev->iobase;
252
253 /* Bring the chip out of low-power mode. */
254 outb(0x00, ioaddr + Config1);
255
256 addr_len = read_eeprom(0,8) == 0x8129 ? 8 : 6;
257 for (i = 0; i < 3; i++)
258 *ap++ = le16_to_cpu (read_eeprom(i + 7, addr_len));
259
260 rtl_reset(dev);
261
262 if (inb(ioaddr + MediaStatus) & MSRLinkFail) {
263 printf("Cable not connected or other link failure\n");
264 return -1 ;
265 }
266
267 return 0;
268 }
269
270 /* Serial EEPROM section. */
271
272 /* EEPROM_Ctrl bits. */
273 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
274 #define EE_CS 0x08 /* EEPROM chip select. */
275 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
276 #define EE_WRITE_0 0x00
277 #define EE_WRITE_1 0x02
278 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
279 #define EE_ENB (0x80 | EE_CS)
280
281 /*
282 Delay between EEPROM clock transitions.
283 No extra delay is needed with 33MHz PCI, but 66MHz may change this.
284 */
285
286 #define eeprom_delay() inl(ee_addr)
287
288 /* The EEPROM commands include the alway-set leading bit. */
289 #define EE_WRITE_CMD (5)
290 #define EE_READ_CMD (6)
291 #define EE_ERASE_CMD (7)
292
read_eeprom(int location,int addr_len)293 static int read_eeprom(int location, int addr_len)
294 {
295 int i;
296 unsigned int retval = 0;
297 long ee_addr = ioaddr + Cfg9346;
298 int read_cmd = location | (EE_READ_CMD << addr_len);
299
300 outb(EE_ENB & ~EE_CS, ee_addr);
301 outb(EE_ENB, ee_addr);
302 eeprom_delay();
303
304 /* Shift the read command bits out. */
305 for (i = 4 + addr_len; i >= 0; i--) {
306 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
307 outb(EE_ENB | dataval, ee_addr);
308 eeprom_delay();
309 outb(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
310 eeprom_delay();
311 }
312 outb(EE_ENB, ee_addr);
313 eeprom_delay();
314
315 for (i = 16; i > 0; i--) {
316 outb(EE_ENB | EE_SHIFT_CLK, ee_addr);
317 eeprom_delay();
318 retval = (retval << 1) | ((inb(ee_addr) & EE_DATA_READ) ? 1 : 0);
319 outb(EE_ENB, ee_addr);
320 eeprom_delay();
321 }
322
323 /* Terminate the EEPROM access. */
324 outb(~EE_CS, ee_addr);
325 eeprom_delay();
326 return retval;
327 }
328
329 static const unsigned int rtl8139_rx_config =
330 (RX_BUF_LEN_IDX << 11) |
331 (RX_FIFO_THRESH << 13) |
332 (RX_DMA_BURST << 8);
333
set_rx_mode(struct eth_device * dev)334 static void set_rx_mode(struct eth_device *dev) {
335 unsigned int mc_filter[2];
336 int rx_mode;
337 /* !IFF_PROMISC */
338 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
339 mc_filter[1] = mc_filter[0] = 0xffffffff;
340
341 outl(rtl8139_rx_config | rx_mode, ioaddr + RxConfig);
342
343 outl(mc_filter[0], ioaddr + MAR0 + 0);
344 outl(mc_filter[1], ioaddr + MAR0 + 4);
345 }
346
rtl_reset(struct eth_device * dev)347 static void rtl_reset(struct eth_device *dev)
348 {
349 int i;
350
351 outb(CmdReset, ioaddr + ChipCmd);
352
353 cur_rx = 0;
354 cur_tx = 0;
355
356 /* Give the chip 10ms to finish the reset. */
357 for (i=0; i<100; ++i){
358 if ((inb(ioaddr + ChipCmd) & CmdReset) == 0) break;
359 udelay (100); /* wait 100us */
360 }
361
362
363 for (i = 0; i < ETH_ALEN; i++)
364 outb(dev->enetaddr[i], ioaddr + MAC0 + i);
365
366 /* Must enable Tx/Rx before setting transfer thresholds! */
367 outb(CmdRxEnb | CmdTxEnb, ioaddr + ChipCmd);
368 outl((RX_FIFO_THRESH<<13) | (RX_BUF_LEN_IDX<<11) | (RX_DMA_BURST<<8),
369 ioaddr + RxConfig); /* accept no frames yet! */
370 outl((TX_DMA_BURST<<8)|0x03000000, ioaddr + TxConfig);
371
372 /* The Linux driver changes Config1 here to use a different LED pattern
373 * for half duplex or full/autodetect duplex (for full/autodetect, the
374 * outputs are TX/RX, Link10/100, FULL, while for half duplex it uses
375 * TX/RX, Link100, Link10). This is messy, because it doesn't match
376 * the inscription on the mounting bracket. It should not be changed
377 * from the configuration EEPROM default, because the card manufacturer
378 * should have set that to match the card. */
379
380 debug_cond(DEBUG_RX,
381 "rx ring address is %lX\n",(unsigned long)rx_ring);
382 flush_cache((unsigned long)rx_ring, RX_BUF_LEN);
383 outl(phys_to_bus((int)rx_ring), ioaddr + RxBuf);
384
385 /* If we add multicast support, the MAR0 register would have to be
386 * initialized to 0xffffffffffffffff (two 32 bit accesses). Etherboot
387 * only needs broadcast (for ARP/RARP/BOOTP/DHCP) and unicast. */
388
389 outb(CmdRxEnb | CmdTxEnb, ioaddr + ChipCmd);
390
391 outl(rtl8139_rx_config, ioaddr + RxConfig);
392
393 /* Start the chip's Tx and Rx process. */
394 outl(0, ioaddr + RxMissed);
395
396 /* set_rx_mode */
397 set_rx_mode(dev);
398
399 /* Disable all known interrupts by setting the interrupt mask. */
400 outw(0, ioaddr + IntrMask);
401 }
402
rtl_transmit(struct eth_device * dev,void * packet,int length)403 static int rtl_transmit(struct eth_device *dev, void *packet, int length)
404 {
405 unsigned int status;
406 unsigned long txstatus;
407 unsigned int len = length;
408 int i = 0;
409
410 ioaddr = dev->iobase;
411
412 memcpy((char *)tx_buffer, (char *)packet, (int)length);
413
414 debug_cond(DEBUG_TX, "sending %d bytes\n", len);
415
416 /* Note: RTL8139 doesn't auto-pad, send minimum payload (another 4
417 * bytes are sent automatically for the FCS, totalling to 64 bytes). */
418 while (len < ETH_ZLEN) {
419 tx_buffer[len++] = '\0';
420 }
421
422 flush_cache((unsigned long)tx_buffer, length);
423 outl(phys_to_bus((int)tx_buffer), ioaddr + TxAddr0 + cur_tx*4);
424 outl(((TX_FIFO_THRESH<<11) & 0x003f0000) | len,
425 ioaddr + TxStatus0 + cur_tx*4);
426
427 do {
428 status = inw(ioaddr + IntrStatus);
429 /* Only acknlowledge interrupt sources we can properly handle
430 * here - the RxOverflow/RxFIFOOver MUST be handled in the
431 * rtl_poll() function. */
432 outw(status & (TxOK | TxErr | PCIErr), ioaddr + IntrStatus);
433 if ((status & (TxOK | TxErr | PCIErr)) != 0) break;
434 udelay(10);
435 } while (i++ < RTL_TIMEOUT);
436
437 txstatus = inl(ioaddr + TxStatus0 + cur_tx*4);
438
439 if (status & TxOK) {
440 cur_tx = (cur_tx + 1) % NUM_TX_DESC;
441
442 debug_cond(DEBUG_TX,
443 "tx done, status %hX txstatus %lX\n",
444 status, txstatus);
445
446 return length;
447 } else {
448
449 debug_cond(DEBUG_TX,
450 "tx timeout/error (%d usecs), status %hX txstatus %lX\n",
451 10*i, status, txstatus);
452
453 rtl_reset(dev);
454
455 return 0;
456 }
457 }
458
rtl_poll(struct eth_device * dev)459 static int rtl_poll(struct eth_device *dev)
460 {
461 unsigned int status;
462 unsigned int ring_offs;
463 unsigned int rx_size, rx_status;
464 int length=0;
465
466 ioaddr = dev->iobase;
467
468 if (inb(ioaddr + ChipCmd) & RxBufEmpty) {
469 return 0;
470 }
471
472 status = inw(ioaddr + IntrStatus);
473 /* See below for the rest of the interrupt acknowledges. */
474 outw(status & ~(RxFIFOOver | RxOverflow | RxOK), ioaddr + IntrStatus);
475
476 debug_cond(DEBUG_RX, "rtl_poll: int %hX ", status);
477
478 ring_offs = cur_rx % RX_BUF_LEN;
479 /* ring_offs is guaranteed being 4-byte aligned */
480 rx_status = le32_to_cpu(*(unsigned int *)(rx_ring + ring_offs));
481 rx_size = rx_status >> 16;
482 rx_status &= 0xffff;
483
484 if ((rx_status & (RxBadSymbol|RxRunt|RxTooLong|RxCRCErr|RxBadAlign)) ||
485 (rx_size < ETH_ZLEN) || (rx_size > ETH_FRAME_LEN + 4)) {
486 printf("rx error %hX\n", rx_status);
487 rtl_reset(dev); /* this clears all interrupts still pending */
488 return 0;
489 }
490
491 /* Received a good packet */
492 length = rx_size - 4; /* no one cares about the FCS */
493 if (ring_offs+4+rx_size-4 > RX_BUF_LEN) {
494 int semi_count = RX_BUF_LEN - ring_offs - 4;
495 unsigned char rxdata[RX_BUF_LEN];
496
497 memcpy(rxdata, rx_ring + ring_offs + 4, semi_count);
498 memcpy(&(rxdata[semi_count]), rx_ring, rx_size-4-semi_count);
499
500 net_process_received_packet(rxdata, length);
501 debug_cond(DEBUG_RX, "rx packet %d+%d bytes",
502 semi_count, rx_size-4-semi_count);
503 } else {
504 net_process_received_packet(rx_ring + ring_offs + 4, length);
505 debug_cond(DEBUG_RX, "rx packet %d bytes", rx_size-4);
506 }
507 flush_cache((unsigned long)rx_ring, RX_BUF_LEN);
508
509 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
510 outw(cur_rx - 16, ioaddr + RxBufPtr);
511 /* See RTL8139 Programming Guide V0.1 for the official handling of
512 * Rx overflow situations. The document itself contains basically no
513 * usable information, except for a few exception handling rules. */
514 outw(status & (RxFIFOOver | RxOverflow | RxOK), ioaddr + IntrStatus);
515 return length;
516 }
517
rtl_disable(struct eth_device * dev)518 static void rtl_disable(struct eth_device *dev)
519 {
520 int i;
521
522 ioaddr = dev->iobase;
523
524 /* reset the chip */
525 outb(CmdReset, ioaddr + ChipCmd);
526
527 /* Give the chip 10ms to finish the reset. */
528 for (i=0; i<100; ++i){
529 if ((inb(ioaddr + ChipCmd) & CmdReset) == 0) break;
530 udelay (100); /* wait 100us */
531 }
532 }
533