Searched refs:DDR_CLK_MHZ (Results 1 – 2 of 2) sorted by relevance
| /third_party/uboot/u-boot-2020.01/board/phytec/phycore_am335x_r2/ |
| D | board.c | 32 #define DDR_CLK_MHZ 400 /* DDR_DPLL_MULT value */ macro
36 DDR_CLK_MHZ, OSC - 1, 1, -1, -1, -1, -1};
135 config_ddr(DDR_CLK_MHZ, &ioregs, in sdram_init()
158 config_ddr(DDR_CLK_MHZ, &ioregs, in sdram_init()
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| /third_party/uboot/u-boot-2020.01/board/phytec/pcm051/ |
| D | board.c | 41 #define DDR_CLK_MHZ 303 /* DDR_DPLL_MULT value */ macro
45 DDR_CLK_MHZ, OSC-1, 1, -1, -1, -1, -1};
92 config_ddr(DDR_CLK_MHZ, &ioregs, &ddr3_data, in sdram_init()
135 config_ddr(DDR_CLK_MHZ, &ioregs, &ddr3_data, in sdram_init()
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