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Searched refs:DIV_ROUND_UP (Results 1 – 25 of 125) sorted by relevance

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/third_party/uboot/u-boot-2020.01/drivers/ddr/microchip/
Dddr2.c105 hc_delay = max_t(u32, DIV_ROUND_UP(delay, T_CK), 2) - 2; in host_load_cmd()
138 writel(REFCNT_CLK(DIV_ROUND_UP(T_RFI, T_CK_CTRL) - 2) | in ddr2_ctrl_init()
139 REFDLY_CLK(DIV_ROUND_UP(T_RFC_MIN, T_CK_CTRL) - 2) | in ddr2_ctrl_init()
150 wr2rd = max_t(u32, DIV_ROUND_UP(T_WTR, T_CK_CTRL), in ddr2_ctrl_init()
151 DIV_ROUND_UP(T_WTR_TCK, 2)) + WL + BL; in ddr2_ctrl_init()
153 wr2prech = DIV_ROUND_UP(T_WR, T_CK_CTRL) + WL + BL; in ddr2_ctrl_init()
154 rd2prech = max_t(u32, DIV_ROUND_UP(T_RTP, T_CK_CTRL), in ddr2_ctrl_init()
155 DIV_ROUND_UP(T_RTP_TCK, 2)) + BL - 2; in ddr2_ctrl_init()
156 ras2ras = max_t(u32, DIV_ROUND_UP(T_RRD, T_CK_CTRL), in ddr2_ctrl_init()
157 DIV_ROUND_UP(T_RRD_TCK, 2)) - 1; in ddr2_ctrl_init()
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/third_party/uboot/u-boot-2020.01/arch/arm/mach-imx/mx6/
Dddr.c1024 trfc = DIV_ROUND_UP(130000, clkper) - 1; in mx6_lpddr2_cfg()
1025 txsr = DIV_ROUND_UP(140000, clkper) - 1; in mx6_lpddr2_cfg()
1028 trfc = DIV_ROUND_UP(210000, clkper) - 1; in mx6_lpddr2_cfg()
1029 txsr = DIV_ROUND_UP(220000, clkper) - 1; in mx6_lpddr2_cfg()
1041 txp = DIV_ROUND_UP(7500, clkper) - 1; in mx6_lpddr2_cfg()
1044 tfaw = DIV_ROUND_UP(60000, clkper) - 1; in mx6_lpddr2_cfg()
1046 tfaw = DIV_ROUND_UP(50000, clkper) - 1; in mx6_lpddr2_cfg()
1047 trrd = DIV_ROUND_UP(10000, clkper) - 1; in mx6_lpddr2_cfg()
1050 tcksre = DIV_ROUND_UP(15000, clkper); in mx6_lpddr2_cfg()
1052 twr = DIV_ROUND_UP(15000, clkper) - 1; in mx6_lpddr2_cfg()
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/third_party/uboot/u-boot-2020.01/drivers/clk/rockchip/
Dclk_rv1108.c158 div = DIV_ROUND_UP(pll_rate, rate) - 1; in rv1108_mac_set_clk()
179 div = DIV_ROUND_UP(pll_rate, rate) - 1; in rv1108_sfc_set_clk()
204 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; in rv1108_saradc_set_clk()
229 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1; in rv1108_aclk_vio1_set_clk()
255 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1; in rv1108_aclk_vio0_set_clk()
290 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1; in rv1108_dclk_vop_set_clk()
320 src_clk_div = DIV_ROUND_UP(parent_rate, hz) - 1; in rv1108_aclk_bus_set_clk()
372 src_clk_div = DIV_ROUND_UP(parent_rate, hz) - 1; in rv1108_aclk_peri_set_clk()
388 src_clk_div = DIV_ROUND_UP(parent_rate, hz) - 1; in rv1108_hclk_peri_set_clk()
403 src_clk_div = DIV_ROUND_UP(parent_rate, hz) - 1; in rv1108_pclk_peri_set_clk()
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Dclk_px30.c109 postdiv1 = DIV_ROUND_UP(VCO_MIN_HZ / 1000, rate_khz); in pll_clk_set_by_auto()
111 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1); in pll_clk_set_by_auto()
112 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2); in pll_clk_set_by_auto()
318 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in px30_i2c_set_clk()
493 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, set_rate); in px30_nandc_set_clk()
557 src_clk_div = DIV_ROUND_UP(priv->gpll_hz / 2, set_rate); in px30_mmc_set_clk()
561 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate); in px30_mmc_set_clk()
605 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in px30_pwm_set_clk()
647 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz); in px30_saradc_set_clk()
673 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz); in px30_tsadc_set_clk()
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Dclk_rk3308.c159 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_i2c_set_clk()
209 div = DIV_ROUND_UP(pll_rate, hz) - 1; in rk3308_mac_set_clk()
284 src_clk_div = DIV_ROUND_UP(priv->vpll0_hz / 2, set_rate); in rk3308_mmc_set_clk()
288 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate); in rk3308_mmc_set_clk()
323 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz); in rk3308_saradc_set_clk()
351 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz); in rk3308_tsadc_set_clk()
394 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_spi_set_clk()
438 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_pwm_set_clk()
508 div = DIV_ROUND_UP(pll_rate, hz); in rk3308_vop_set_clk()
572 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_bus_set_clk()
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Dclk_rk3288.c242 no = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz); in pll_para_config()
244 *ext_div = DIV_ROUND_UP(no, max_no); in pll_para_config()
245 no = DIV_ROUND_UP(no, *ext_div); in pll_para_config()
250 no = DIV_ROUND_UP(no, 2) * 2; in pll_para_config()
323 div = DIV_ROUND_UP(pll_rate, freq) - 1; in rockchip_mac_set_clk()
612 src_clk_div = DIV_ROUND_UP(gclk_rate / 2, freq); in rockchip_mmc_set_clk()
615 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq); in rockchip_mmc_set_clk()
690 src_clk_div = DIV_ROUND_UP(gclk_rate, freq) - 1; in rockchip_spi_set_clk()
733 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; in rockchip_saradc_set_clk()
Dclk_rk3128.c92 postdiv1 = DIV_ROUND_UP(VCO_MIN_HZ / 1000, freq_khz); in pll_para_config()
94 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1); in pll_para_config()
95 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2); in pll_para_config()
316 src_clk_div = DIV_ROUND_UP(clk_general_rate / 2, freq); in rockchip_mmc_set_clk()
319 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq); in rockchip_mmc_set_clk()
406 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; in rk3128_saradc_set_clk()
Dclk_rk3399.c373 postdiv1 = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz); in pll_para_config()
375 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1); in pll_para_config()
376 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2); in pll_para_config()
649 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1; in rk3399_spi_set_clk()
753 src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate); in rk3399_mmc_set_clk()
757 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate); in rk3399_mmc_set_clk()
772 src_clk_div = DIV_ROUND_UP(GPLL_HZ, aclk_emmc); in rk3399_mmc_set_clk()
781 src_clk_div = DIV_ROUND_UP(GPLL_HZ, set_rate); in rk3399_mmc_set_clk()
881 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; in rk3399_saradc_set_clk()
/third_party/uboot/u-boot-2020.01/drivers/fastboot/
Dfb_mmc.c153 hdr_sectors = DIV_ROUND_UP(sizeof(struct andr_img_hdr), sector_size); in fb_mmc_get_boot_header()
239 ramdisk_sector_start += DIV_ROUND_UP(hdr->kernel_size, hdr->page_size) * in fb_mmc_update_zimage()
241 ramdisk_sectors = DIV_ROUND_UP(hdr->ramdisk_size, hdr->page_size) * in fb_mmc_update_zimage()
266 kernel_sectors = DIV_ROUND_UP(hdr->kernel_size, hdr->page_size) * in fb_mmc_update_zimage()
278 ramdisk_sector_start += DIV_ROUND_UP(hdr->kernel_size, hdr->page_size) * in fb_mmc_update_zimage()
/third_party/uboot/u-boot-2020.01/board/freescale/common/
Dvid.c192 voltage_read = DIV_ROUND_UP(voltage_read, 128); in read_voltage_from_IR()
246 vcode = DIV_ROUND_UP(vcode * 1000, 4096); in read_voltage_from_LTC()
339 vid = DIV_ROUND_UP(vdd - 265, 5); in set_voltage_to_IR()
341 vid = DIV_ROUND_UP(vdd - 245, 5); in set_voltage_to_IR()
634 vdd_target = DIV_ROUND_UP(vdd_target, 10); in adjust_vdd()
844 vdd_target = DIV_ROUND_UP(vdd_target, 10); in adjust_vdd()
/third_party/uboot/u-boot-2020.01/drivers/spi/
Dcadence_qspi_apb.c270 div = DIV_ROUND_UP(ref_clk_hz, sclk_hz * 2) - 1; in cadence_qspi_apb_config_baudrate_div()
350 ref_clk_ns = DIV_ROUND_UP(1000000000, ref_clk); in cadence_qspi_apb_delay()
353 sclk_ns = DIV_ROUND_UP(1000000000, sclk_hz); in cadence_qspi_apb_delay()
360 tshsl = DIV_ROUND_UP(tshsl_ns, ref_clk_ns); in cadence_qspi_apb_delay()
361 tchsh = DIV_ROUND_UP(tchsh_ns, ref_clk_ns); in cadence_qspi_apb_delay()
362 tslch = DIV_ROUND_UP(tslch_ns, ref_clk_ns); in cadence_qspi_apb_delay()
363 tsd2d = DIV_ROUND_UP(tsd2d_ns, ref_clk_ns); in cadence_qspi_apb_delay()
Dfsl_espi.c109 fsl->tx_timeout = DIV_ROUND_UP((US_PER_SECOND * ESPI_FIFO_WIDTH_BIT in spi_setup_slave()
216 rx_times = DIV_ROUND_UP(bytes, 4); in fsl_espi_rx()
298 num_chunks = DIV_ROUND_UP(data_len, max_tran_len); in spi_xfer()
304 num_blks = DIV_ROUND_UP(tran_len + cmd_len, 4); in spi_xfer()
Dmxc_spi.c122 div = DIV_ROUND_UP(clk_src, max_hz); in spi_cfg_mxc()
241 int nbytes = DIV_ROUND_UP(bitlen, 8); in spi_xchg_single()
320 nbytes = DIV_ROUND_UP(bitlen, 8); in spi_xchg_single()
357 int n_bytes = DIV_ROUND_UP(bitlen, 8); in mxc_spi_xfer_internal()
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv8/fsl-layerscape/
Dppa.c99 cnt = DIV_ROUND_UP(fdt_header_len, 512); in ppa_init()
125 cnt = DIV_ROUND_UP(CONFIG_LS_PPA_ESBC_HDR_SIZE, 512); in ppa_init()
149 cnt = DIV_ROUND_UP(fw_length, 512); in ppa_init()
/third_party/uboot/u-boot-2020.01/drivers/mtd/onenand/
Donenand_spl.c184 to_page = page + DIV_ROUND_UP(size, 2048); in onenand_spl_load_image()
187 to_page = page + DIV_ROUND_UP(size, 4096); in onenand_spl_load_image()
/third_party/uboot/u-boot-2020.01/tools/
Domapimage.c22 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) macro
155 DIV_ROUND_UP(sbuf->st_size, sizeof(uint32_t)); in omapimage_set_header()
Dsunxi-spl-image-builder.c19 #define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d)) macro
118 int eccbytes = DIV_ROUND_UP(info->ecc_strength * 14, 8); in write_page()
381 eccbytes = DIV_ROUND_UP(info->ecc_strength * 14, 8); in check_image_info()
/third_party/uboot/u-boot-2020.01/include/linux/
Ddelay.h18 udelay(DIV_ROUND_UP(nsec, 1000)); in ndelay()
/third_party/uboot/u-boot-2020.01/drivers/mtd/nand/raw/
Ddenali.c976 acc_clks = DIV_ROUND_UP(timings->tREA_max, t_x); in denali_setup_data_interface()
985 re_2_we = DIV_ROUND_UP(timings->tRHW_min, t_x); in denali_setup_data_interface()
994 re_2_re = DIV_ROUND_UP(timings->tRHZ_max, t_x); in denali_setup_data_interface()
1008 we_2_re = DIV_ROUND_UP(max(timings->tCCS_min, timings->tWHR_min), t_x); in denali_setup_data_interface()
1023 addr_2_data = DIV_ROUND_UP(timings->tADL_min, t_x); in denali_setup_data_interface()
1032 rdwr_en_hi = DIV_ROUND_UP(max(timings->tREH_min, timings->tWH_min), in denali_setup_data_interface()
1042 rdwr_en_lo = DIV_ROUND_UP(max(timings->tRP_min, timings->tWP_min), t_x); in denali_setup_data_interface()
1043 rdwr_en_lo_hi = DIV_ROUND_UP(max(timings->tRC_min, timings->tWC_min), in denali_setup_data_interface()
1055 cs_setup = max3((int)DIV_ROUND_UP(timings->tCS_min, t_x) - rdwr_en_lo, in denali_setup_data_interface()
1056 (int)DIV_ROUND_UP(timings->tCEA_max, t_x) - acc_clks, in denali_setup_data_interface()
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Dpxa3xx_nand.c452 u32 tCH_min = DIV_ROUND_UP(t->tCH_min, 1000); in pxa3xx_nand_set_sdr_timing()
453 u32 tCS_min = DIV_ROUND_UP(t->tCS_min, 1000); in pxa3xx_nand_set_sdr_timing()
454 u32 tWH_min = DIV_ROUND_UP(t->tWH_min, 1000); in pxa3xx_nand_set_sdr_timing()
455 u32 tWP_min = DIV_ROUND_UP(t->tWC_min - t->tWH_min, 1000); in pxa3xx_nand_set_sdr_timing()
456 u32 tREH_min = DIV_ROUND_UP(t->tREH_min, 1000); in pxa3xx_nand_set_sdr_timing()
457 u32 tRP_min = DIV_ROUND_UP(t->tRC_min - t->tREH_min, 1000); in pxa3xx_nand_set_sdr_timing()
459 u32 tWHR_min = DIV_ROUND_UP(t->tWHR_min, 1000); in pxa3xx_nand_set_sdr_timing()
460 u32 tAR_min = DIV_ROUND_UP(t->tAR_min, 1000); in pxa3xx_nand_set_sdr_timing()
631 DIV_ROUND_UP(data_len, 4)); in handle_data_pio()
636 DIV_ROUND_UP(info->step_spare_size, 4)); in handle_data_pio()
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/third_party/uboot/u-boot-2020.01/drivers/i2c/
Drk_i2c.c52 *divh = DIV_ROUND_UP(div, 2); in rk_i2c_get_div()
68 div = DIV_ROUND_UP(i2c_rate, scl_rate * 8) - 2; in rk_i2c_set_clk()
207 words_xferred = DIV_ROUND_UP(bytes_xferred, 4); in rk_i2c_read()
285 words_xferred = DIV_ROUND_UP(bytes_xferred, 4); in rk_i2c_write()
/third_party/uboot/u-boot-2020.01/drivers/fpga/
Dsocfpga.c52 uint32_t loops4 = DIV_ROUND_UP(rbf_size % 32, 4); in fpgamgr_program_write()
/third_party/uboot/u-boot-2020.01/lib/aes/
Daes-decrypt.c34 aes_blocks = DIV_ROUND_UP(cipher_len, AES_BLOCK_LENGTH); in image_aes_decrypt()
/third_party/uboot/u-boot-2020.01/arch/arm/mach-sunxi/
Dclock_sun4i.c134 axi = DIV_ROUND_UP(hz, 432000000); /* Max 450MHz */ in clock_set_pll1()
135 ahb = DIV_ROUND_UP(hz/axi, 204000000); /* Max 250MHz */ in clock_set_pll1()
/third_party/uboot/u-boot-2020.01/drivers/misc/
Dmxc_ocotp.c256 fsource = DIV_ROUND_UP((ipg_clk / 1000) * BV_TIMING_FSOURCE_NS, in set_timing()
280 relax = DIV_ROUND_UP(ipg_clk * BV_TIMING_RELAX_NS, 1000000000) - 1; in set_timing()
281 strobe_read = DIV_ROUND_UP(ipg_clk * BV_TIMING_STROBE_READ_NS, in set_timing()

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