1 /* 2 * hifmc_common.h 3 * 4 * The Flash Memory Controller v100 Device Driver for hisilicon 5 * 6 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program. If not, see <http://www.gnu.org/licenses/>. 20 * 21 */ 22 23 #ifndef __HIFMC_COMMON_H__ 24 #define __HIFMC_COMMON_H__ 25 26 /*****************************************************************************/ 27 #define _32B 32 28 #define _64B 64 29 #define _128B 128 30 #define _218B 218 31 #define _224B 224 32 #define _232B 232 33 #define _256B 256 34 #define _448B 448 35 #define _512B 512 36 #define _640B 640 37 #define _744B 744 38 #define _1K 1024 39 #define _1280B 1280 40 #define _2K 2048 41 #define _4K 4096 42 #define _8K 8192 43 #define _16K 16384 44 #define _32K 32768 45 #define _64K 0x10000UL 46 #define _128K 0x20000UL 47 #define _256K 0x40000UL 48 #define _512K 0x80000UL 49 #define _1M 0x100000UL 50 #define _2M 0x200000UL 51 #define _4M 0x400000UL 52 #define _8M 0x800000UL 53 #define _16M 0x1000000UL 54 #define _32M 0x2000000UL 55 #define _64M 0x4000000UL 56 #define _128M 0x8000000UL 57 #define _256M 0x10000000UL 58 #define _512M 0x20000000UL 59 #define _1G 0x40000000ULL 60 #define _2G 0x80000000ULL 61 #define _4G 0x100000000ULL 62 #define _8G 0x200000000ULL 63 #define _16G 0x400000000ULL 64 #define _64G 0x1000000000ULL 65 66 #define ECC_TYPE_0BIT 0x0 67 #define ECC_TYPE_8BIT 0x1 68 #define ECC_TYPE_16BIT 0x2 69 #define ECC_TYPE_24BIT 0x3 70 #define ECC_TYPE_28BIT 0x4 71 #define ECC_TYPE_40BIT 0x5 72 #define ECC_TYPE_64BIT 0x6 73 74 #define PAGE_SIZE_2KB 0x0 75 #define PAGE_SIZE_4KB 0x1 76 #define PAGE_SIZE_8KB 0x2 77 #define PAGE_SIZE_16KB 0x3 78 79 /* id len */ 80 #define _2B 2 81 #define _3B 3 82 #define _4B 4 83 #define _5B 5 84 #define _6B 6 85 #define _7B 7 86 #define _8B 8 87 #define _9B 9 88 #define _10B 10 89 #define _11B 11 90 #define _12B 12 91 92 #ifdef CONFIG_HIFMC 93 /*****************************************************************************/ 94 /* HIFMC REG */ 95 /*****************************************************************************/ 96 #define FMC_CFG 0x00 97 #define fmc_cfg_spi_nand_sel(_type) (((_size) & 0x3) << 11) 98 #define fmc_cfg_spi_nor_addr_mode(_mode) ((_mode) << 10) 99 #define fmc_cfg_block_size(_size) (((_size) & 0x3) << 8) 100 #define fmc_cfg_ecc_type(_type) (((_type) & 0x7) << 5) 101 #define fmc_cfg_page_size(_size) (((_size) & 0x3) << 3) 102 #define fmc_cfg_flash_sel(_type) (((_type) & 0x3) << 1) 103 #define fmc_cfg_op_mode(_mode) ((_mode) & 0x1) 104 105 #define SPI_NAND_MFR_OTHER 0x0 106 #define SPI_NAND_MFR_WINBOND 0x1 107 #define SPI_NAND_MFR_ESMT 0x2 108 #define SPI_NAND_MFR_MICRON 0x3 109 110 #define SPI_NAND_SEL_SHIFT 11 111 #define SPI_NAND_SEL_MASK (0x3 << SPI_NAND_SEL_SHIFT) 112 113 #define SPI_NOR_ADDR_MODE_3_BYTES 0x0 114 #define SPI_NOR_ADDR_MODE_4_BYTES 0x1 115 116 #define SPI_NOR_ADDR_MODE_SHIFT 10 117 #define SPI_NOR_ADDR_MODE_MASK (0x1 << SPI_NOR_ADDR_MODE_SHIFT) 118 119 #define BLOCK_SIZE_64_PAGE 0x0 120 #define BLOCK_SIZE_128_PAGE 0x1 121 #define BLOCK_SIZE_256_PAGE 0x2 122 #define BLOCK_SIZE_512_PAGE 0x3 123 124 #define _64_PAGES 64 125 #define _128_PAGES 128 126 #define _256_PAGES 256 127 #define _512_PAGES 512 128 129 #define EB_NORMAL 28 130 #define EB_2K_16_BIT 4 131 #define EB_4K_16_BIT 12 132 133 #define BLOCK_SIZE_MASK (0x3 << 8) 134 135 #define ECC_TYPE_SHIFT 5 136 #define ECC_TYPE_MASK (0x7 << ECC_TYPE_SHIFT) 137 138 #define PAGE_SIZE_SHIFT 3 139 #define PAGE_SIZE_MASK (0x3 << PAGE_SIZE_SHIFT) 140 141 #define FLASH_TYPE_SPI_NOR 0x0 142 #define FLASH_TYPE_SPI_NAND 0x1 143 #define FLASH_TYPE_NAND 0x2 144 #define FLASH_TYPE_DEFAULT 0x3 145 146 #define FLASH_SEL_SHIFT 1 147 #define FLASH_SEL_MASK (0x3 << FLASH_SEL_SHIFT) 148 149 #define OP_MODE_BOOT 0x0 150 #define OP_MODE_NORMAL 0x1 151 152 #define OP_MODE_MASK 0x1 153 154 /*****************************************************************************/ 155 #define FMC_GLOBAL_CFG 0x04 156 #define FMC_GLOBAL_CFG_WP_ENABLE (1 << 6) 157 #define FMC_GLOBAL_CFG_RANDOMIZER_EN (1 << 2) 158 159 /*****************************************************************************/ 160 #define FMC_SPI_TIMING_CFG 0x08 161 #define timing_cfg_tcsh(_n) (((_n) & 0xf) << 8) 162 #define timing_cfg_tcss(_n) (((_n) & 0xf) << 4) 163 #define timing_cfg_tshsl(_n) ((_n) & 0xf) 164 165 #define CS_HOLD_TIME 0x6 166 #define CS_SETUP_TIME 0x6 167 #define CS_DESELECT_TIME 0xf 168 169 /*****************************************************************************/ 170 #define FMC_PND_PWIDTH_CFG 0x0c 171 #define pwidth_cfg_rw_hcnt(_n) (((_n) & 0xf) << 8) 172 #define pwidth_cfg_r_lcnt(_n) (((_n) & 0xf) << 4) 173 #define pwidth_cfg_w_lcnt(_n) ((_n) & 0xf) 174 175 #ifdef CONFIG_NAND_EDO_MODE 176 #define RW_H_WIDTH 0x3 177 #define R_L_WIDTH 0x2 178 #define W_L_WIDTH 0x2 179 #define NAND_EDO_MODE_SHIFT 9 180 #define NAND_EDO_MODE_MASK (1<<NAND_EDO_MODE_SHIFT) 181 #define set_nand_edo_mode_en(reg) ((reg) | NAND_EDO_MODE_MASK) 182 #else 183 #define RW_H_WIDTH 0xa 184 #define R_L_WIDTH 0xa 185 #define W_L_WIDTH 0xa 186 #endif 187 /*****************************************************************************/ 188 #define FMC_INT 0x18 189 #define FMC_INT_AHB_OP (1 << 7) 190 #define FMC_INT_WR_LOCK (1 << 6) 191 #define FMC_INT_DMA_ERR (1 << 5) 192 #define FMC_INT_ERR_ALARM (1 << 4) 193 #define FMC_INT_ERR_INVALID (1 << 3) 194 #define FMC_INT_ERR_VALID (1 << 2) 195 #define FMC_INT_OP_FAIL (1 << 1) 196 #define FMC_INT_OP_DONE (1 << 0) 197 198 /*****************************************************************************/ 199 #define FMC_INT_EN 0x1c 200 #define FMC_INT_EN_AHB_OP (1 << 7) 201 #define FMC_INT_EN_WR_LOCK (1 << 6) 202 #define FMC_INT_EN_DMA_ERR (1 << 5) 203 #define FMC_INT_EN_ERR_ALARM (1 << 4) 204 #define FMC_INT_EN_ERR_INVALID (1 << 3) 205 #define FMC_INT_EN_ERR_VALID (1 << 2) 206 #define FMC_INT_EN_OP_FAIL (1 << 1) 207 #define FMC_INT_EN_OP_DONE (1 << 0) 208 209 /*****************************************************************************/ 210 #define FMC_INT_CLR 0x20 211 #define FMC_INT_CLR_AHB_OP (1 << 7) 212 #define FMC_INT_CLR_WR_LOCK (1 << 6) 213 #define FMC_INT_CLR_DMA_ERR (1 << 5) 214 #define FMC_INT_CLR_ERR_ALARM (1 << 4) 215 #define FMC_INT_CLR_ERR_INVALID (1 << 3) 216 #define FMC_INT_CLR_ERR_VALID (1 << 2) 217 #define FMC_INT_CLR_OP_FAIL (1 << 1) 218 #define FMC_INT_CLR_OP_DONE (1 << 0) 219 220 #define FMC_INT_CLR_ALL 0xff 221 222 /*****************************************************************************/ 223 #define FMC_CMD 0x24 224 #define fmc_cmd_cmd2(_cmd) (((_cmd) & 0xff) << 8) 225 #define fmc_cmd_cmd1(_cmd) ((_cmd) & 0xff) 226 227 /*****************************************************************************/ 228 #define FMC_ADDRH 0x28 229 #define fmc_addrh_set(_addr) ((_addr) & 0xff) 230 231 /*****************************************************************************/ 232 #define FMC_ADDRL 0x2c 233 #define fmc_addrl_block_h_mask(_page) (((_page) & 0xffff) << 16) 234 #define fmc_addrl_block_l_mask(_page) ((_page) & 0xffc0) 235 236 #define READ_ID_ADDR 0x00 237 #define PROTECT_ADDR 0xa0 238 #define FEATURE_ADDR 0xb0 239 #define STATUS_ADDR 0xc0 240 241 /*****************************************************************************/ 242 #define FMC_OP_CFG 0x30 243 #define op_cfg_fm_cs(_cs) ((_cs) << 11) 244 #define op_cfg_force_cs_en(_en) ((_en) << 10) 245 #define op_cfg_mem_if_type(_type) (((_type) & 0x7) << 7) 246 #define op_cfg_addr_num(_addr) (((_addr) & 0x7) << 4) 247 #define op_cfg_dummy_num(_dummy) ((_dummy) & 0xf) 248 #define OP_CFG_OEN_EN (0x1 << 13) 249 250 #define IF_TYPE_STD 0x0 251 #define IF_TYPE_DUAL 0x1 252 #define IF_TYPE_DIO 0x2 253 #define IF_TYPE_QUAD 0x3 254 #define IF_TYPE_QIO 0x4 255 #define IF_TYPE_DTR 0x4 256 257 #define IF_TYPE_SHIFT 7 258 #define IF_TYPE_MASK (0x7 << IF_TYPE_SHIFT) 259 260 #define READ_ID_ADDR_NUM 1 261 #define FEATURES_OP_ADDR_NUM 1 262 #define STD_OP_ADDR_NUM 3 263 264 /*****************************************************************************/ 265 #define FMC_SPI_OP_ADDR 0x34 266 267 /*****************************************************************************/ 268 #define FMC_DATA_NUM 0x38 269 #define fmc_data_num_cnt(_n) ((_n) & 0x3fff) 270 271 #define SPI_NOR_SR_LEN 1 /* Status Register length */ 272 #define SPI_NOR_CR_LEN 1 /* Config Register length */ 273 #define FEATURES_DATA_LEN 1 274 #define READ_OOB_BB_LEN 1 275 #define MAX_SPI_NOR_ID_LEN 8 276 #define MAX_NAND_ID_LEN 8 277 #define MAX_SPI_NAND_ID_LEN 3 278 279 #define PROTECT_BRWD_MASK (1 << 7) 280 #define PROTECT_BP3_MASK (1 << 6) 281 #define PROTECT_BP2_MASK (1 << 5) 282 #define PROTECT_BP1_MASK (1 << 4) 283 #define PROTECT_BP0_MASK (1 << 3) 284 285 #define any_bp_enable(_val) ((PROTECT_BP3_MASK & _val) || \ 286 (PROTECT_BP2_MASK & _val) || (PROTECT_BP1_MASK & _val) || \ 287 (PROTECT_BP0_MASK & _val)) 288 289 #define ALL_BP_MASK (PROTECT_BP3_MASK \ 290 | PROTECT_BP2_MASK \ 291 | PROTECT_BP1_MASK \ 292 | PROTECT_BP0_MASK) 293 294 #define FEATURE_ECC_ENABLE (1 << 4) 295 #define FEATURE_QE_ENABLE (1 << 0) 296 297 /* read nand id or nand status, return from nand data length */ 298 #define MAX_NANDINFO_LEN 0x10 299 300 /*****************************************************************************/ 301 #define FMC_OP 0x3c 302 #define fmc_op_dummy_en(_en) ((_en) << 8) 303 #define fmc_op_cmd1_en(_en) ((_en) << 7) 304 #define fmc_op_addr_en(_en) ((_en) << 6) 305 #define fmc_op_write_data_en(_en) ((_en) << 5) 306 #define fmc_op_cmd2_en(_en) ((_en) << 4) 307 #define fmc_op_wait_ready_en(_en) ((_en) << 3) 308 #define fmc_op_read_data_en(_en) ((_en) << 2) 309 #define fmc_op_read_status_en(_en) ((_en) << 1) 310 #define FMC_OP_REG_OP_START 1 311 312 /*****************************************************************************/ 313 #define FMC_DMA_LEN 0x40 314 #define fmc_dma_len_set(_len) ((_len) & 0x0fffffff) 315 #define byte_to_mb(_x) ((_x) >> 20) 316 /*****************************************************************************/ 317 #define FMC_DMA_AHB_CTRL 0x48 318 #define FMC_DMA_AHB_CTRL_DMA_PP_EN (1 << 3) 319 #define FMC_DMA_AHB_CTRL_BURST16_EN (1 << 2) 320 #define FMC_DMA_AHB_CTRL_BURST8_EN (1 << 1) 321 #define FMC_DMA_AHB_CTRL_BURST4_EN 1 322 323 #define ALL_BURST_ENABLE (FMC_DMA_AHB_CTRL_BURST16_EN \ 324 | FMC_DMA_AHB_CTRL_BURST8_EN \ 325 | FMC_DMA_AHB_CTRL_BURST4_EN) 326 327 #define FMC_DMA_ADDR_OFFSET 4096 328 329 /*****************************************************************************/ 330 #define FMC_DMA_SADDR_D0 0x4c 331 332 /*****************************************************************************/ 333 #define FMC_DMA_SADDR_D1 0x50 334 335 /*****************************************************************************/ 336 #define FMC_DMA_SADDR_D2 0x54 337 338 /*****************************************************************************/ 339 #define FMC_DMA_SADDR_D3 0x58 340 341 /*****************************************************************************/ 342 #define FMC_DMA_SADDR_OOB 0x5c 343 344 /*****************************************************************************/ 345 #define FMC_DMA_SADDRH_D0 0x200 346 #define FMC_DMA_SADDRH_SHIFT 0x3LL 347 #define FMC_DMA_SADDRH_MASK (FMC_DMA_SADDRH_SHIFT << 32) 348 349 /*****************************************************************************/ 350 #define FMC_DMA_SADDRH_OOB 0x210 351 352 /*****************************************************************************/ 353 #define FMC_DMA_BLK_SADDR 0x60 354 #define fmc_dma_blk_saddr_set(_addr) ((_addr) & 0xffffff) 355 356 /*****************************************************************************/ 357 #define FMC_DMA_BLK_LEN 0x64 358 #define fmc_dma_blk_len_set(_len) ((_len) & 0xffff) 359 360 /*****************************************************************************/ 361 #define FMC_OP_CTRL 0x68 362 #define op_ctrl_rd_opcode(_code) (((_code) & 0xff) << 16) 363 #define op_ctrl_wr_opcode(_code) (((_code) & 0xff) << 8) 364 #define op_ctrl_rd_op_sel(_op) (((_op) & 0x3) << 4) 365 #define op_ctrl_dma_op(_type) ((_type) << 2) 366 #define op_ctrl_rw_op(_op) ((_op) << 1) 367 #define OP_CTRL_DMA_OP_READY 1 368 369 #define RD_OP_READ_ALL_PAGE 0x0 370 #define RD_OP_READ_OOB 0x1 371 #define RD_OP_BLOCK_READ 0x2 372 373 #define RD_OP_SHIFT 4 374 #define RD_OP_MASK (0x3 << RD_OP_SHIFT) 375 376 #define OP_TYPE_DMA 0x0 377 #define OP_TYPE_REG 0x1 378 379 #define RW_OP_READ 0x0 380 #define RW_OP_WRITE 0x1 381 382 /*****************************************************************************/ 383 #define FMC_OP_PARA 0x70 384 #define FMC_OP_PARA_RD_OOB_ONLY (1 << 1) 385 386 /*****************************************************************************/ 387 #define FMC_BOOT_SET 0x74 388 #define FMC_BOOT_SET_DEVICE_ECC_EN (1 << 3) 389 #define FMC_BOOT_SET_BOOT_QUAD_EN (1 << 1) 390 391 /*****************************************************************************/ 392 #define FMC_STATUS 0xac 393 394 #define GET_OP 0 395 #define SET_OP 1 396 397 #define STATUS_ECC_MASK (0x3 << 4) 398 #define STATUS_P_FAIL_MASK (1 << 3) 399 #define STATUS_E_FAIL_MASK (1 << 2) 400 #define STATUS_WEL_MASK (1 << 1) 401 #define STATUS_OIP_MASK (1 << 0) 402 403 /*****************************************************************************/ 404 #define FMC_VERSION 0xbc 405 406 /* Hifmc IP version */ 407 #define HIFMC_VER_100 0x100 408 409 #endif /* End of CONFIG_HIFMC */ 410 411 /*****************************************************************************/ 412 #define DISABLE 0 413 #define ENABLE 1 414 415 /*****************************************************************************/ 416 /* DMA address align with 32 bytes. */ 417 #define FMC_DMA_ALIGN 32 418 419 #define FMC_CHIP_DELAY 25 420 421 #define TMP_BUF_LEN 128 422 /*****************************************************************************/ 423 #define hifmc_read(_host, _reg) \ 424 readl((uintptr_t)((char *)_host->regbase + (_reg))) 425 426 #define hifmc_write(_host, _reg, _value) \ 427 writel((u_int)(_value), (uintptr_t)((char *)_host->regbase + (_reg))) 428 429 #define get_page_index(host) \ 430 ((host->addr_value[0] >> 16) | (host->addr_value[1] << 16)) 431 432 /*****************************************************************************/ 433 #define db_msg(_fmt, arg...) \ 434 printf("%s(%d): " _fmt, __func__, __LINE__, ##arg); 435 436 #define db_bug(fmt, args...) \ 437 do { \ 438 printf("%s(%d): BUG: " fmt, __FILE__, __LINE__, ##args); \ 439 while (1) ; \ 440 } while (0) 441 442 /*****************************************************************************/ 443 444 #ifdef CONFIG_MINI_BOOT 445 #define FMC_INFO 0 446 #else 447 #define FMC_INFO 1 448 #endif 449 450 #define BT_DBG 0 /* Boot init debug print */ 451 #define ER_DBG 0 /* Erase debug print */ 452 #define WR_DBG 0 /* Write debug print */ 453 #define RD_DBG 0 /* Read debug print */ 454 #define QE_DBG 0 /* Quad Enable debug print */ 455 #define OP_DBG 0 /* OP command debug print */ 456 #define DMA_DB 0 /* DMA read or write debug print */ 457 #define AC_DBG 0 /* 3-4byte Address Cycle */ 458 #define SR_DBG 0 /* Status Register debug print */ 459 #define CR_DBG 0 /* Config Register debug print */ 460 #define FT_DBG 0 /* Features debug print */ 461 #define WE_DBG 0 /* Write Enable debug print */ 462 #define BP_DBG 0 /* Block Protection debug print */ 463 #define EC_DBG 0 /* enable/disable ecc0 and randomizer */ 464 #define DTR_DB 0 /* 4DTR debug print */ 465 #define RST_DB 0 /* enable/disable reset pin */ 466 #define REG_DB 0 /* operation debug print */ 467 468 #define fmc_pr(_type, _fmt, arg...) \ 469 do { \ 470 if (_type) \ 471 db_msg(_fmt, ##arg) \ 472 } while (0) 473 474 /*****************************************************************************/ 475 #define FMC_WAIT_TIMEOUT 400000 /* 4s equals 400000*10us */ 476 477 #define fmc_cmd_wait_cpu_finish(_host) \ 478 do { \ 479 unsigned regval, timeout = FMC_WAIT_TIMEOUT; \ 480 do { \ 481 udelay(10);\ 482 regval = hifmc_read((_host), FMC_OP); \ 483 --timeout; \ 484 } while ((regval & FMC_OP_REG_OP_START) && timeout); \ 485 if (!timeout) \ 486 db_msg("Error: Wait cmd cpu finish timeout!\n"); \ 487 } while (0) 488 489 /*****************************************************************************/ 490 #define fmc_dma_wait_int_finish(_host) \ 491 do { \ 492 unsigned regval, timeout = FMC_WAIT_TIMEOUT; \ 493 do { \ 494 udelay(10);\ 495 regval = hifmc_read((_host), FMC_INT); \ 496 --timeout; \ 497 } while ((!(regval & FMC_INT_OP_DONE) && timeout)); \ 498 if (!timeout) { \ 499 debug_register_dump(); \ 500 db_msg("Error: Wait dma int finish timeout!\n"); \ 501 } \ 502 } while (0) 503 504 /*****************************************************************************/ 505 #define fmc_dma_wait_cpu_finish(_host) \ 506 do { \ 507 unsigned regval, timeout = FMC_WAIT_TIMEOUT; \ 508 do { \ 509 udelay(10);\ 510 regval = hifmc_read((_host), FMC_OP_CTRL); \ 511 --timeout; \ 512 } while ((regval & OP_CTRL_DMA_OP_READY) && timeout); \ 513 if (!timeout) { \ 514 debug_register_dump(); \ 515 db_msg("Error: Wait dma cpu finish timeout!\n"); \ 516 } \ 517 } while (0) 518 519 /*****************************************************************************/ 520 #define clk_2x(_clk) (((_clk) + 1) >> 1) 521 #define clk_4x(_clk) (((_clk) + 1) >> 2) 522 523 enum OP { 524 READ = 1, 525 WRITE, 526 ERASE, 527 }; 528 529 /*****************************************************************************/ 530 struct hifmc_cmd_op { 531 unsigned char cs; 532 unsigned char cmd; 533 unsigned char l_cmd; 534 unsigned char addr_h; 535 unsigned int addr_l; 536 unsigned int data_no; 537 unsigned short option; 538 unsigned short op_cfg; 539 }; 540 /*****************************************************************************/ 541 char *ulltostr(unsigned long long size); 542 543 void debug_register_dump(void); 544 545 int hifmc_ip_ver_check(void); 546 547 void hifmc_dev_type_switch(unsigned char type); 548 549 void *get_hifmc_ip(void); 550 551 unsigned char *get_cs_number(unsigned char cs); 552 553 unsigned int get_fmc_boot_mode (void); 554 555 #endif /* End of __HIFMC_COMMON_H__ */ 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