Searched refs:KHz (Results 1 – 25 of 38) sorted by relevance
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70 #define KHz 1000 macro88 #define PERIHP_ACLK_HZ (148500*KHz)89 #define PERIHP_HCLK_HZ (148500*KHz)90 #define PERIHP_PCLK_HZ (37125*KHz)92 #define PERILP0_ACLK_HZ (99000*KHz)93 #define PERILP0_HCLK_HZ (99000*KHz)94 #define PERILP0_PCLK_HZ (49500*KHz)96 #define PERILP1_HCLK_HZ (99000*KHz)97 #define PERILP1_PCLK_HZ (49500*KHz)
48 #define KHz 1000 macro58 #define PERIHP_ACLK_HZ (144000 * KHz)59 #define PERIHP_HCLK_HZ (72000 * KHz)60 #define PERIHP_PCLK_HZ (72000 * KHz)
11 #define KHz 1000 macro
89 * The gsl1680 is rated at 400KHz and it will not work reliable at90 * 100KHz, this has been confirmed on multiple different q8 tablets.91 * All other devices on this bus are also rated for 400KHz.
213 regulator-name = "32KHz AP";218 regulator-name = "32KHz CP";
24 /* KHz uV */
66 * The gsl1680 is rated at 400KHz and it will not work reliable at67 * 100KHz, this has been confirmed on multiple different q8 tablets.
80 pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
86 pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
50 /* KHz uV */
186 pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
170 pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
197 pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
81 pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
49 /* KHz uV */
160 pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
341 pwms = <&pwm_ab 0 30518 0>; /* PWM_A at 32.768KHz */
133 /* KHz uV */
287 #define VCO_MAX_KHZ (3200 * (MHz / KHz))288 #define VCO_MIN_KHZ (800 * (MHz / KHz))289 #define OUTPUT_MAX_KHZ (3200 * (MHz / KHz))290 #define OUTPUT_MIN_KHZ (16 * (MHz / KHz))359 u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0; in pll_para_config()366 u32 freq_khz = freq_hz / KHz; in pll_para_config()412 if (best_diff_khz > 4 * (MHz / KHz)) { in pll_para_config()415 best_diff_khz * KHz); in pll_para_config()
179 #define VCO_MAX_KHZ (3200 * (MHz / KHz))180 #define VCO_MIN_KHZ (800 * (MHz / KHz))181 #define OUTPUT_MAX_KHZ (3200 * (MHz / KHz))182 #define OUTPUT_MIN_KHZ (16 * (MHz / KHz))
95 u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0; in pll_clk_set_by_auto()102 u32 rate_khz = drate / KHz; in pll_clk_set_by_auto()117 if (vco_khz < (VCO_MIN_HZ / KHz) || vco_khz > (VCO_MAX_HZ / KHz) || in pll_clk_set_by_auto()149 if (best_diff_khz > 4 * (MHz / KHz)) { in pll_clk_set_by_auto()152 best_diff_khz * KHz); in pll_clk_set_by_auto()
18 It not defined, then default is 5us (~50KHz).
49 32KHz clock is supported by the driver but the duty cycle is
13 the 32 KHz "32k_in", and the board-specific oscillator "osc".
192 as a SoC power controller. It also provides 32KHz clock outputs. This