1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Amlogic Meson Video Processing Unit driver
4 *
5 * Copyright (c) 2018 BayLibre, SAS.
6 * Author: Neil Armstrong <narmstrong@baylibre.com>
7 */
8
9 #ifndef __MESON_VPU_H__
10 #define __MESON_VPU_H__
11
12 #include <common.h>
13 #include <dm.h>
14 #include <video.h>
15 #include <display.h>
16 #include <linux/io.h>
17 #include <linux/bitfield.h>
18 #include "meson_registers.h"
19
20 enum {
21 /* Maximum size we support */
22 VPU_MAX_WIDTH = 3840,
23 VPU_MAX_HEIGHT = 2160,
24 VPU_MAX_LOG2_BPP = VIDEO_BPP32,
25 };
26
27 enum vpu_compatible {
28 VPU_COMPATIBLE_GXBB = 0,
29 VPU_COMPATIBLE_GXL = 1,
30 VPU_COMPATIBLE_GXM = 2,
31 VPU_COMPATIBLE_G12A = 3,
32 };
33
34 struct meson_vpu_priv {
35 struct udevice *dev;
36 void __iomem *io_base;
37 void __iomem *hhi_base;
38 void __iomem *dmc_base;
39 };
40
meson_vpu_is_compatible(struct meson_vpu_priv * priv,enum vpu_compatible family)41 static inline bool meson_vpu_is_compatible(struct meson_vpu_priv *priv,
42 enum vpu_compatible family)
43 {
44 enum vpu_compatible compat = dev_get_driver_data(priv->dev);
45
46 return compat == family;
47 }
48
49 #define hhi_update_bits(offset, mask, value) \
50 writel_bits(mask, value, priv->hhi_base + offset)
51
52 #define hhi_write(offset, value) \
53 writel(value, priv->hhi_base + offset)
54
55 #define hhi_read(offset) \
56 readl(priv->hhi_base + offset)
57
58 #define dmc_update_bits(offset, mask, value) \
59 writel_bits(mask, value, priv->dmc_base + offset)
60
61 #define dmc_write(offset, value) \
62 writel(value, priv->dmc_base + offset)
63
64 #define dmc_read(offset) \
65 readl(priv->dmc_base + offset)
66
67 #define MESON_CANVAS_ID_OSD1 0x4e
68
69 /* Canvas configuration. */
70 #define MESON_CANVAS_WRAP_NONE 0x00
71 #define MESON_CANVAS_WRAP_X 0x01
72 #define MESON_CANVAS_WRAP_Y 0x02
73
74 #define MESON_CANVAS_BLKMODE_LINEAR 0x00
75 #define MESON_CANVAS_BLKMODE_32x32 0x01
76 #define MESON_CANVAS_BLKMODE_64x64 0x02
77
78 void meson_canvas_setup(struct meson_vpu_priv *priv,
79 u32 canvas_index, u32 addr,
80 u32 stride, u32 height,
81 unsigned int wrap,
82 unsigned int blkmode);
83
84 /* Mux VIU/VPP to ENCI */
85 #define MESON_VIU_VPP_MUX_ENCI 0x5
86 /* Mux VIU/VPP to ENCP */
87 #define MESON_VIU_VPP_MUX_ENCP 0xA
88
89 void meson_vpp_setup_mux(struct meson_vpu_priv *priv, unsigned int mux);
90 void meson_vpu_init(struct udevice *dev);
91 void meson_vpu_setup_plane(struct udevice *dev, bool is_interlaced);
92 bool meson_venc_hdmi_supported_mode(const struct display_timing *mode);
93 void meson_vpu_setup_venc(struct udevice *dev,
94 const struct display_timing *mode, bool is_cvbs);
95 bool meson_vclk_dmt_supported_freq(struct meson_vpu_priv *priv,
96 unsigned int freq);
97 void meson_vpu_setup_vclk(struct udevice *dev,
98 const struct display_timing *mode, bool is_cvbs);
99 #endif
100