1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * TI PHY drivers
4 *
5 */
6 #include <common.h>
7 #include <phy.h>
8 #include <linux/compat.h>
9 #include <malloc.h>
10
11 #include <dm.h>
12 #include <dt-bindings/net/ti-dp83867.h>
13
14
15 /* TI DP83867 */
16 #define DP83867_DEVADDR 0x1f
17
18 #define MII_DP83867_PHYCTRL 0x10
19 #define MII_DP83867_MICR 0x12
20 #define MII_DP83867_CFG2 0x14
21 #define MII_DP83867_BISCR 0x16
22 #define DP83867_CTRL 0x1f
23
24 /* Extended Registers */
25 #define DP83867_CFG4 0x0031
26 #define DP83867_RGMIICTL 0x0032
27 #define DP83867_STRAP_STS1 0x006E
28 #define DP83867_STRAP_STS2 0x006f
29 #define DP83867_RGMIIDCTL 0x0086
30 #define DP83867_IO_MUX_CFG 0x0170
31
32 #define DP83867_SW_RESET BIT(15)
33 #define DP83867_SW_RESTART BIT(14)
34
35 /* MICR Interrupt bits */
36 #define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15)
37 #define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14)
38 #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13)
39 #define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12)
40 #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11)
41 #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10)
42 #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8)
43 #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
44 #define MII_DP83867_MICR_WOL_INT_EN BIT(3)
45 #define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2)
46 #define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1)
47 #define MII_DP83867_MICR_JABBER_INT_EN BIT(0)
48
49 /* RGMIICTL bits */
50 #define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1)
51 #define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0)
52
53 /* STRAP_STS1 bits */
54 #define DP83867_STRAP_STS1_RESERVED BIT(11)
55
56 /* STRAP_STS2 bits */
57 #define DP83867_STRAP_STS2_CLK_SKEW_TX_MASK GENMASK(6, 4)
58 #define DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT 4
59 #define DP83867_STRAP_STS2_CLK_SKEW_RX_MASK GENMASK(2, 0)
60 #define DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT 0
61 #define DP83867_STRAP_STS2_CLK_SKEW_NONE BIT(2)
62
63 /* PHY CTRL bits */
64 #define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14
65 #define DP83867_PHYCR_FIFO_DEPTH_MASK GENMASK(15, 14)
66 #define DP83867_PHYCR_RESERVED_MASK BIT(11)
67 #define DP83867_MDI_CROSSOVER 5
68 #define DP83867_MDI_CROSSOVER_MDIX 2
69 #define DP83867_PHYCTRL_SGMIIEN 0x0800
70 #define DP83867_PHYCTRL_RXFIFO_SHIFT 12
71 #define DP83867_PHYCTRL_TXFIFO_SHIFT 14
72
73 /* RGMIIDCTL bits */
74 #define DP83867_RGMII_TX_CLK_DELAY_MAX 0xf
75 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4
76 #define DP83867_RGMII_RX_CLK_DELAY_MAX 0xf
77
78 /* CFG2 bits */
79 #define MII_DP83867_CFG2_SPEEDOPT_10EN 0x0040
80 #define MII_DP83867_CFG2_SGMII_AUTONEGEN 0x0080
81 #define MII_DP83867_CFG2_SPEEDOPT_ENH 0x0100
82 #define MII_DP83867_CFG2_SPEEDOPT_CNT 0x0800
83 #define MII_DP83867_CFG2_SPEEDOPT_INTLOW 0x2000
84 #define MII_DP83867_CFG2_MASK 0x003F
85
86 /* User setting - can be taken from DTS */
87 #define DEFAULT_FIFO_DEPTH DP83867_PHYCR_FIFO_DEPTH_4_B_NIB
88
89 /* IO_MUX_CFG bits */
90 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL 0x1f
91
92 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0
93 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f
94 #define DP83867_IO_MUX_CFG_CLK_O_DISABLE BIT(6)
95 #define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT 8
96 #define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK \
97 GENMASK(0x1f, DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT)
98
99 /* CFG4 bits */
100 #define DP83867_CFG4_PORT_MIRROR_EN BIT(0)
101
102 enum {
103 DP83867_PORT_MIRRORING_KEEP,
104 DP83867_PORT_MIRRORING_EN,
105 DP83867_PORT_MIRRORING_DIS,
106 };
107
108 struct dp83867_private {
109 u32 rx_id_delay;
110 u32 tx_id_delay;
111 int fifo_depth;
112 int io_impedance;
113 bool rxctrl_strap_quirk;
114 int port_mirroring;
115 bool set_clk_output;
116 unsigned int clk_output_sel;
117 };
118
dp83867_config_port_mirroring(struct phy_device * phydev)119 static int dp83867_config_port_mirroring(struct phy_device *phydev)
120 {
121 struct dp83867_private *dp83867 =
122 (struct dp83867_private *)phydev->priv;
123 u16 val;
124
125 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4);
126
127 if (dp83867->port_mirroring == DP83867_PORT_MIRRORING_EN)
128 val |= DP83867_CFG4_PORT_MIRROR_EN;
129 else
130 val &= ~DP83867_CFG4_PORT_MIRROR_EN;
131
132 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, val);
133
134 return 0;
135 }
136
137 #if defined(CONFIG_DM_ETH)
138 /**
139 * dp83867_data_init - Convenience function for setting PHY specific data
140 *
141 * @phydev: the phy_device struct
142 */
dp83867_of_init(struct phy_device * phydev)143 static int dp83867_of_init(struct phy_device *phydev)
144 {
145 struct dp83867_private *dp83867 = phydev->priv;
146 ofnode node;
147 int ret;
148
149 node = phy_get_ofnode(phydev);
150 if (!ofnode_valid(node))
151 return -EINVAL;
152
153 /* Optional configuration */
154 ret = ofnode_read_u32(node, "ti,clk-output-sel",
155 &dp83867->clk_output_sel);
156 /* If not set, keep default */
157 if (!ret) {
158 dp83867->set_clk_output = true;
159 /* Valid values are 0 to DP83867_CLK_O_SEL_REF_CLK or
160 * DP83867_CLK_O_SEL_OFF.
161 */
162 if (dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK &&
163 dp83867->clk_output_sel != DP83867_CLK_O_SEL_OFF) {
164 pr_debug("ti,clk-output-sel value %u out of range\n",
165 dp83867->clk_output_sel);
166 return -EINVAL;
167 }
168 }
169
170 if (ofnode_read_bool(node, "ti,max-output-impedance"))
171 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
172 else if (ofnode_read_bool(node, "ti,min-output-impedance"))
173 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
174 else
175 dp83867->io_impedance = -EINVAL;
176
177 if (ofnode_read_bool(node, "ti,dp83867-rxctrl-strap-quirk"))
178 dp83867->rxctrl_strap_quirk = true;
179
180 /* Existing behavior was to use default pin strapping delay in rgmii
181 * mode, but rgmii should have meant no delay. Warn existing users.
182 */
183 if (phydev->interface == PHY_INTERFACE_MODE_RGMII) {
184 u16 val = phy_read_mmd(phydev, DP83867_DEVADDR,
185 DP83867_STRAP_STS2);
186 u16 txskew = (val & DP83867_STRAP_STS2_CLK_SKEW_TX_MASK) >>
187 DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT;
188 u16 rxskew = (val & DP83867_STRAP_STS2_CLK_SKEW_RX_MASK) >>
189 DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT;
190
191 if (txskew != DP83867_STRAP_STS2_CLK_SKEW_NONE ||
192 rxskew != DP83867_STRAP_STS2_CLK_SKEW_NONE)
193 pr_warn("PHY has delays via pin strapping, but phy-mode = 'rgmii'\n"
194 "Should be 'rgmii-id' to use internal delays\n");
195 }
196
197 /* RX delay *must* be specified if internal delay of RX is used. */
198 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
199 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
200 ret = ofnode_read_u32(node, "ti,rx-internal-delay",
201 &dp83867->rx_id_delay);
202 if (ret) {
203 pr_debug("ti,rx-internal-delay must be specified\n");
204 return ret;
205 }
206 if (dp83867->rx_id_delay > DP83867_RGMII_RX_CLK_DELAY_MAX) {
207 pr_debug("ti,rx-internal-delay value of %u out of range\n",
208 dp83867->rx_id_delay);
209 return -EINVAL;
210 }
211 }
212
213 /* TX delay *must* be specified if internal delay of RX is used. */
214 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
215 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
216 ret = ofnode_read_u32(node, "ti,tx-internal-delay",
217 &dp83867->tx_id_delay);
218 if (ret) {
219 debug("ti,tx-internal-delay must be specified\n");
220 return ret;
221 }
222 if (dp83867->tx_id_delay > DP83867_RGMII_TX_CLK_DELAY_MAX) {
223 pr_debug("ti,tx-internal-delay value of %u out of range\n",
224 dp83867->tx_id_delay);
225 return -EINVAL;
226 }
227 }
228
229 dp83867->fifo_depth = ofnode_read_u32_default(node, "ti,fifo-depth",
230 DEFAULT_FIFO_DEPTH);
231 if (ofnode_read_bool(node, "enet-phy-lane-swap"))
232 dp83867->port_mirroring = DP83867_PORT_MIRRORING_EN;
233
234 if (ofnode_read_bool(node, "enet-phy-lane-no-swap"))
235 dp83867->port_mirroring = DP83867_PORT_MIRRORING_DIS;
236
237 return 0;
238 }
239 #else
dp83867_of_init(struct phy_device * phydev)240 static int dp83867_of_init(struct phy_device *phydev)
241 {
242 struct dp83867_private *dp83867 = phydev->priv;
243
244 dp83867->rx_id_delay = DP83867_RGMIIDCTL_2_25_NS;
245 dp83867->tx_id_delay = DP83867_RGMIIDCTL_2_75_NS;
246 dp83867->fifo_depth = DEFAULT_FIFO_DEPTH;
247 dp83867->io_impedance = -EINVAL;
248
249 return 0;
250 }
251 #endif
252
dp83867_config(struct phy_device * phydev)253 static int dp83867_config(struct phy_device *phydev)
254 {
255 struct dp83867_private *dp83867;
256 unsigned int val, delay, cfg2;
257 int ret, bs;
258
259 dp83867 = (struct dp83867_private *)phydev->priv;
260
261 ret = dp83867_of_init(phydev);
262 if (ret)
263 return ret;
264
265 /* Restart the PHY. */
266 val = phy_read(phydev, MDIO_DEVAD_NONE, DP83867_CTRL);
267 phy_write(phydev, MDIO_DEVAD_NONE, DP83867_CTRL,
268 val | DP83867_SW_RESTART);
269
270 /* Mode 1 or 2 workaround */
271 if (dp83867->rxctrl_strap_quirk) {
272 val = phy_read_mmd(phydev, DP83867_DEVADDR,
273 DP83867_CFG4);
274 val &= ~BIT(7);
275 phy_write_mmd(phydev, DP83867_DEVADDR,
276 DP83867_CFG4, val);
277 }
278
279 if (phy_interface_is_rgmii(phydev)) {
280 val = phy_read(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL);
281 if (val < 0)
282 goto err_out;
283 val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK;
284 val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT);
285
286 /* The code below checks if "port mirroring" N/A MODE4 has been
287 * enabled during power on bootstrap.
288 *
289 * Such N/A mode enabled by mistake can put PHY IC in some
290 * internal testing mode and disable RGMII transmission.
291 *
292 * In this particular case one needs to check STRAP_STS1
293 * register's bit 11 (marked as RESERVED).
294 */
295
296 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1);
297 if (bs & DP83867_STRAP_STS1_RESERVED)
298 val &= ~DP83867_PHYCR_RESERVED_MASK;
299
300 ret = phy_write(phydev, MDIO_DEVAD_NONE,
301 MII_DP83867_PHYCTRL, val);
302
303 val = phy_read_mmd(phydev, DP83867_DEVADDR,
304 DP83867_RGMIICTL);
305
306 val &= ~(DP83867_RGMII_TX_CLK_DELAY_EN |
307 DP83867_RGMII_RX_CLK_DELAY_EN);
308 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
309 val |= (DP83867_RGMII_TX_CLK_DELAY_EN |
310 DP83867_RGMII_RX_CLK_DELAY_EN);
311
312 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
313 val |= DP83867_RGMII_TX_CLK_DELAY_EN;
314
315 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
316 val |= DP83867_RGMII_RX_CLK_DELAY_EN;
317
318 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val);
319
320 delay = (dp83867->rx_id_delay |
321 (dp83867->tx_id_delay <<
322 DP83867_RGMII_TX_CLK_DELAY_SHIFT));
323
324 phy_write_mmd(phydev, DP83867_DEVADDR,
325 DP83867_RGMIIDCTL, delay);
326 }
327
328 if (phy_interface_is_sgmii(phydev)) {
329 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR,
330 (BMCR_ANENABLE | BMCR_FULLDPLX | BMCR_SPEED1000));
331
332 cfg2 = phy_read(phydev, phydev->addr, MII_DP83867_CFG2);
333 cfg2 &= MII_DP83867_CFG2_MASK;
334 cfg2 |= (MII_DP83867_CFG2_SPEEDOPT_10EN |
335 MII_DP83867_CFG2_SGMII_AUTONEGEN |
336 MII_DP83867_CFG2_SPEEDOPT_ENH |
337 MII_DP83867_CFG2_SPEEDOPT_CNT |
338 MII_DP83867_CFG2_SPEEDOPT_INTLOW);
339 phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_CFG2, cfg2);
340
341 phy_write_mmd(phydev, DP83867_DEVADDR,
342 DP83867_RGMIICTL, 0x0);
343
344 phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL,
345 DP83867_PHYCTRL_SGMIIEN |
346 (DP83867_MDI_CROSSOVER_MDIX <<
347 DP83867_MDI_CROSSOVER) |
348 (dp83867->fifo_depth << DP83867_PHYCTRL_RXFIFO_SHIFT) |
349 (dp83867->fifo_depth << DP83867_PHYCTRL_TXFIFO_SHIFT));
350 phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_BISCR, 0x0);
351 }
352
353 if (dp83867->io_impedance >= 0) {
354 val = phy_read_mmd(phydev,
355 DP83867_DEVADDR,
356 DP83867_IO_MUX_CFG);
357 val &= ~DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
358 val |= dp83867->io_impedance &
359 DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
360 phy_write_mmd(phydev, DP83867_DEVADDR,
361 DP83867_IO_MUX_CFG, val);
362 }
363
364 if (dp83867->port_mirroring != DP83867_PORT_MIRRORING_KEEP)
365 dp83867_config_port_mirroring(phydev);
366
367 /* Clock output selection if muxing property is set */
368 if (dp83867->set_clk_output) {
369 val = phy_read_mmd(phydev, DP83867_DEVADDR,
370 DP83867_IO_MUX_CFG);
371
372 if (dp83867->clk_output_sel == DP83867_CLK_O_SEL_OFF) {
373 val |= DP83867_IO_MUX_CFG_CLK_O_DISABLE;
374 } else {
375 val &= ~(DP83867_IO_MUX_CFG_CLK_O_SEL_MASK |
376 DP83867_IO_MUX_CFG_CLK_O_DISABLE);
377 val |= dp83867->clk_output_sel <<
378 DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT;
379 }
380 phy_write_mmd(phydev, DP83867_DEVADDR,
381 DP83867_IO_MUX_CFG, val);
382 }
383
384 genphy_config_aneg(phydev);
385 return 0;
386
387 err_out:
388 return ret;
389 }
390
dp83867_probe(struct phy_device * phydev)391 static int dp83867_probe(struct phy_device *phydev)
392 {
393 struct dp83867_private *dp83867;
394
395 dp83867 = kzalloc(sizeof(*dp83867), GFP_KERNEL);
396 if (!dp83867)
397 return -ENOMEM;
398
399 phydev->priv = dp83867;
400 return 0;
401 }
402
403 static struct phy_driver DP83867_driver = {
404 .name = "TI DP83867",
405 .uid = 0x2000a231,
406 .mask = 0xfffffff0,
407 .features = PHY_GBIT_FEATURES,
408 .probe = dp83867_probe,
409 .config = &dp83867_config,
410 .startup = &genphy_startup,
411 .shutdown = &genphy_shutdown,
412 };
413
phy_ti_init(void)414 int phy_ti_init(void)
415 {
416 phy_register(&DP83867_driver);
417 return 0;
418 }
419