| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPULegalizerInfo.h | 35 bool legalizeCustom(MachineInstr &MI, MachineRegisterInfo &MRI,
40 MachineRegisterInfo &MRI,
43 bool legalizeAddrSpaceCast(MachineInstr &MI, MachineRegisterInfo &MRI,
45 bool legalizeFrint(MachineInstr &MI, MachineRegisterInfo &MRI,
47 bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI,
49 bool legalizeIntrinsicTrunc(MachineInstr &MI, MachineRegisterInfo &MRI,
51 bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI,
53 bool legalizeMinNumMaxNum(MachineInstr &MI, MachineRegisterInfo &MRI,
55 bool legalizeExtractVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
57 bool legalizeInsertVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
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| D | AMDGPURegisterBankInfo.cpp | 45 MachineRegisterInfo &MRI; member in __anon5b5de1ed0111::ApplyRegBankMapping
52 : RBI(RBI_), MRI(MRI_), NewBank(RB) {} in ApplyRegBankMapping()
69 const RegisterBank *SrcBank = RBI.getRegBank(SrcReg, MRI, *RBI.TRI); in applyBank()
72 assert(MRI.getType(SrcReg) == LLT::scalar(1)); in applyBank()
73 assert(MRI.getType(DstReg) == S32); in applyBank()
82 MRI.setRegBank(True.getReg(0), *NewBank); in applyBank()
83 MRI.setRegBank(False.getReg(0), *NewBank); in applyBank()
87 assert(!MRI.getRegClassOrRegBank(DstReg)); in applyBank()
88 MRI.setRegBank(DstReg, *NewBank); in applyBank()
95 const RegisterBank *DstBank = RBI.getRegBank(DstReg, MRI, *RBI.TRI); in applyBank()
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| D | GCNRegPressure.cpp | 38 const MachineRegisterInfo &MRI) { in printLivesAt() argument
42 for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) { in printLivesAt()
52 dbgs() << " " << printReg(Reg, MRI.getTargetRegisterInfo()) in printLivesAt()
86 const MachineRegisterInfo &MRI) { in getRegKind() argument
88 const auto RC = MRI.getRegClass(Reg); in getRegKind()
89 auto STI = static_cast<const SIRegisterInfo*>(MRI.getTargetRegisterInfo()); in getRegKind()
100 const MachineRegisterInfo &MRI) { in inc() argument
110 const auto MaxMask = MRI.getMaxLaneMaskForVReg(Reg); in inc()
112 switch (auto Kind = getRegKind(Reg, MRI)) { in inc()
131 Value[Kind] += Sign * MRI.getPressureSets(Reg).getWeight(); in inc()
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| D | AMDGPUInstructionSelector.cpp | 69 MRI = &MF.getRegInfo(); in setupMF()
74 const MachineRegisterInfo &MRI) const { in isVCC()
78 auto &RegClassOrBank = MRI.getRegClassOrRegBank(Reg); in isVCC()
82 const LLT Ty = MRI.getType(Reg); in isVCC()
101 if (isVCC(DstReg, *MRI)) { in selectCOPY()
104 = TRI.getConstrainedRegClassForOperand(Dst, *MRI); in selectCOPY()
107 return RBI.constrainGenericRegister(DstReg, *RC, *MRI); in selectCOPY()
110 if (!isVCC(SrcReg, *MRI)) { in selectCOPY()
112 if (!RBI.constrainGenericRegister(DstReg, *TRI.getBoolRC(), *MRI)) in selectCOPY()
116 = TRI.getConstrainedRegClassForOperand(Src, *MRI); in selectCOPY()
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| D | AMDGPURegisterBankInfo.h | 53 MachineRegisterInfo &MRI,
60 MachineRegisterInfo &MRI) const;
64 MachineRegisterInfo &MRI,
67 MachineRegisterInfo &MRI,
70 void constrainOpWithReadfirstlane(MachineInstr &MI, MachineRegisterInfo &MRI,
74 MachineRegisterInfo &MRI) const;
78 MachineRegisterInfo &MRI, int RSrcIdx) const;
82 Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI,
97 unsigned getRegBankID(Register Reg, const MachineRegisterInfo &MRI,
103 const MachineRegisterInfo &MRI,
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| D | SIFixSGPRCopies.cpp | 117 MachineRegisterInfo *MRI; member in __anon7045b2640111::SIFixSGPRCopies
155 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo(); in hasVectorOperands() local
161 if (TRI->hasVectorRegisters(MRI.getRegClass(MI.getOperand(i).getReg()))) in hasVectorOperands()
170 const MachineRegisterInfo &MRI) { in getCopyRegClasses() argument
175 ? MRI.getRegClass(SrcReg) in getCopyRegClasses()
182 ? MRI.getRegClass(DstReg) in getCopyRegClasses()
205 MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo(); in tryChangeVGPRtoSGPRinCopy() local
213 for (const auto &MO : MRI.reg_nodbg_operands(DstReg)) { in tryChangeVGPRtoSGPRinCopy()
223 MRI.setRegClass(DstReg, TRI->getEquivalentSGPRClass(MRI.getRegClass(DstReg))); in tryChangeVGPRtoSGPRinCopy()
243 MachineRegisterInfo &MRI) { in foldVGPRCopyIntoRegSequence() argument
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| D | SIFixupVectorISel.cpp | 88 MachineRegisterInfo &MRI, in findSRegBaseAndIndex() argument
96 MachineInstr *DefInst = MRI.getUniqueVRegDef(WOp->getReg()); in findSRegBaseAndIndex()
120 MachineInstr *MI = MRI.getUniqueVRegDef(IndexReg); in findSRegBaseAndIndex()
127 IdxRC = MRI.getRegClass(MI->getOperand(1).getReg()); in findSRegBaseAndIndex()
132 MI = MRI.getUniqueVRegDef(BaseReg); in findSRegBaseAndIndex()
137 BaseRC = MRI.getRegClass(BaseReg); in findSRegBaseAndIndex()
141 if (!TRI->isSGPRReg(MRI, BaseReg)) in findSRegBaseAndIndex()
143 if (!TRI->hasVGPRs(MRI.getRegClass(IndexReg))) in findSRegBaseAndIndex()
146 MRI.clearKillFlags(IndexReg); in findSRegBaseAndIndex()
147 MRI.clearKillFlags(BaseReg); in findSRegBaseAndIndex()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCVSXCopy.cpp | 52 MachineRegisterInfo &MRI) { in IsRegInClass()
54 return RC->hasSubClassEq(MRI.getRegClass(Reg)); in IsRegInClass()
62 bool IsVSReg(unsigned Reg, MachineRegisterInfo &MRI) { in IsVSReg()
63 return IsRegInClass(Reg, &PPC::VSRCRegClass, MRI); in IsVSReg()
66 bool IsVRReg(unsigned Reg, MachineRegisterInfo &MRI) { in IsVRReg()
67 return IsRegInClass(Reg, &PPC::VRRCRegClass, MRI); in IsVRReg()
70 bool IsF8Reg(unsigned Reg, MachineRegisterInfo &MRI) { in IsF8Reg()
71 return IsRegInClass(Reg, &PPC::F8RCRegClass, MRI); in IsF8Reg()
74 bool IsVSFReg(unsigned Reg, MachineRegisterInfo &MRI) { in IsVSFReg()
75 return IsRegInClass(Reg, &PPC::VSFRCRegClass, MRI); in IsVSFReg()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64AdvSIMDScalarPass.cpp | 66 MachineRegisterInfo *MRI; member in __anon22eb08eb0111::AArch64AdvSIMDScalar
105 const MachineRegisterInfo *MRI) { in isGPR64() argument
109 return MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::GPR64RegClass); in isGPR64()
114 const MachineRegisterInfo *MRI) { in isFPR64() argument
116 return (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR64RegClass) && in isFPR64()
118 (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR128RegClass) && in isFPR64()
128 const MachineRegisterInfo *MRI, in getSrcFromCopy() argument
145 MRI) && in getSrcFromCopy()
146 isGPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), MRI)) in getSrcFromCopy()
149 MRI) && in getSrcFromCopy()
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| D | AArch64InstructionSelector.cpp | 80 bool earlySelectSHL(MachineInstr &I, MachineRegisterInfo &MRI) const;
84 MachineRegisterInfo &MRI) const;
87 MachineRegisterInfo &MRI) const;
89 MachineRegisterInfo &MRI) const;
92 MachineRegisterInfo &MRI) const;
94 bool selectVectorASHR(MachineInstr &I, MachineRegisterInfo &MRI) const;
95 bool selectVectorSHL(MachineInstr &I, MachineRegisterInfo &MRI) const;
114 bool selectInsertElt(MachineInstr &I, MachineRegisterInfo &MRI) const;
115 bool selectBuildVector(MachineInstr &I, MachineRegisterInfo &MRI) const;
116 bool selectMergeValues(MachineInstr &I, MachineRegisterInfo &MRI) const;
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| D | AArch64RegisterBankInfo.cpp | 274 const MachineRegisterInfo &MRI = MF.getRegInfo(); in getInstrAlternativeMappings() local
280 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI); in getInstrAlternativeMappings()
301 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI); in getInstrAlternativeMappings()
337 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI); in getInstrAlternativeMappings()
423 const MachineRegisterInfo &MRI = MF.getRegInfo(); in getSameKindOfOperandsMapping() local
429 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getSameKindOfOperandsMapping()
445 LLT OpTy = MRI.getType(MI.getOperand(Idx).getReg()); in getSameKindOfOperandsMapping()
462 const MachineInstr &MI, const MachineRegisterInfo &MRI, in hasFPConstraints() argument
476 return getRegBank(MI.getOperand(0).getReg(), MRI, TRI) == in hasFPConstraints()
481 const MachineRegisterInfo &MRI, in onlyUsesFP() argument
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86InstructionSelector.cpp | 76 bool selectLoadStoreOp(MachineInstr &I, MachineRegisterInfo &MRI,
78 bool selectFrameIndexOrGep(MachineInstr &I, MachineRegisterInfo &MRI,
80 bool selectGlobalValue(MachineInstr &I, MachineRegisterInfo &MRI,
82 bool selectConstant(MachineInstr &I, MachineRegisterInfo &MRI,
84 bool selectTruncOrPtrToInt(MachineInstr &I, MachineRegisterInfo &MRI,
86 bool selectZext(MachineInstr &I, MachineRegisterInfo &MRI,
88 bool selectAnyext(MachineInstr &I, MachineRegisterInfo &MRI,
90 bool selectCmp(MachineInstr &I, MachineRegisterInfo &MRI,
92 bool selectFCmp(MachineInstr &I, MachineRegisterInfo &MRI,
94 bool selectUadde(MachineInstr &I, MachineRegisterInfo &MRI,
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| D | X86RegisterBankInfo.cpp | 112 const MachineInstr &MI, const MachineRegisterInfo &MRI, const bool isFP, in getInstrPartialMappingIdxs() argument
121 OpRegBankIdx[Idx] = getPartialMappingIdx(MRI.getType(MO.getReg()), isFP); in getInstrPartialMappingIdxs()
148 const MachineRegisterInfo &MRI = MF.getRegInfo(); in getSameOperandsMapping() local
151 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getSameOperandsMapping()
153 if (NumOperands != 3 || (Ty != MRI.getType(MI.getOperand(1).getReg())) || in getSameOperandsMapping()
154 (Ty != MRI.getType(MI.getOperand(2).getReg()))) in getSameOperandsMapping()
164 const MachineRegisterInfo &MRI = MF.getRegInfo(); in getInstrMapping() local
189 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
207 getInstrPartialMappingIdxs(MI, MRI, /* isFP */ true, OpRegBankIdx); in getInstrMapping()
215 const LLT Ty0 = MRI.getType(Op0.getReg()); in getInstrMapping()
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| D | X86CallLowering.cpp | 56 MachineRegisterInfo &MRI, in splitToValueTypes() argument
86 ArgInfo{MRI.createGenericVirtualRegister(getLLTForType(*PartTy, DL)), in splitToValueTypes()
99 OutgoingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, in OutgoingValueHandler()
101 : ValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB), in OutgoingValueHandler()
111 Register SPReg = MRI.createGenericVirtualRegister(p0); in getStackAddress()
114 Register OffsetReg = MRI.createGenericVirtualRegister(SType); in getStackAddress()
117 Register AddrReg = MRI.createGenericVirtualRegister(p0); in getStackAddress()
136 MRI.getTargetRegisterInfo()->getRegSizeInBits(PhysReg, MRI); in assignValueToReg()
197 MachineRegisterInfo &MRI = MF.getRegInfo(); in lowerReturn() local
211 if (!splitToValueTypes(CurArgInfo, SplitArgs, DL, MRI, in lowerReturn()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/ |
| D | BPFMISimplifyPatchable.cpp | 56 void processCandidate(MachineRegisterInfo *MRI, MachineBasicBlock &MBB,
59 void processDstReg(MachineRegisterInfo *MRI, Register &DstReg,
62 void processInst(MachineRegisterInfo *MRI, MachineInstr *Inst,
64 void checkADDrr(MachineRegisterInfo *MRI, MachineOperand *RelocOp,
66 void checkShift(MachineRegisterInfo *MRI, MachineBasicBlock &MBB,
88 void BPFMISimplifyPatchable::checkADDrr(MachineRegisterInfo *MRI, in checkADDrr() argument
97 auto Begin = MRI->use_begin(Op0.getReg()), End = MRI->use_end(); in checkADDrr()
102 if (!MRI->getUniqueVRegDef(I->getReg())) in checkADDrr()
131 void BPFMISimplifyPatchable::checkShift(MachineRegisterInfo *MRI, in checkShift() argument
145 void BPFMISimplifyPatchable::processCandidate(MachineRegisterInfo *MRI, in processCandidate() argument
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | Utils.cpp | 30 unsigned llvm::constrainRegToClass(MachineRegisterInfo &MRI, in constrainRegToClass() argument
34 if (!RBI.constrainGenericRegister(Reg, RegClass, MRI)) in constrainRegToClass()
35 return MRI.createVirtualRegister(&RegClass); in constrainRegToClass()
42 MachineRegisterInfo &MRI, const TargetInstrInfo &TII, in constrainOperandRegClass() argument
50 unsigned ConstrainedReg = constrainRegToClass(MRI, TII, RBI, Reg, RegClass); in constrainOperandRegClass()
72 MachineRegisterInfo &MRI, const TargetInstrInfo &TII, in constrainOperandRegClass() argument
89 RegClass = TRI.getConstrainedRegClassForOperand(RegMO, MRI); in constrainOperandRegClass()
107 return constrainOperandRegClass(MF, TRI, MRI, TII, RBI, InsertPt, *RegClass, in constrainOperandRegClass()
119 MachineRegisterInfo &MRI = MF.getRegInfo(); in constrainSelectedInstRegOperands() local
144 MO.setReg(constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, I.getDesc(), in constrainSelectedInstRegOperands()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | MIPatternMatch.h | 24 bool mi_match(Reg R, const MachineRegisterInfo &MRI, Pattern &&P) { in mi_match() argument
25 return P.match(MRI, R); in mi_match()
33 bool match(const MachineRegisterInfo &MRI, unsigned Reg) { in match()
34 return MRI.hasOneUse(Reg) && SubPat.match(MRI, Reg); in match()
46 bool match(const MachineRegisterInfo &MRI, unsigned Reg) { in match()
47 if (auto MaybeCst = getConstantVRegVal(Reg, MRI)) { in match()
63 bool match(const MachineRegisterInfo &MRI, unsigned Reg) { return true; } in match()
64 bool match(const MachineRegisterInfo &MRI, MachineOperand *MO) { in match()
74 bool match(const MachineRegisterInfo &MRI, MatchSrc &&src) { in match()
86 bool match(const MachineRegisterInfo &MRI, MatchSrc &&src) {
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| D | Utils.h | 45 unsigned constrainRegToClass(MachineRegisterInfo &MRI,
59 MachineRegisterInfo &MRI,
77 MachineRegisterInfo &MRI,
98 bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI);
114 const MachineRegisterInfo &MRI);
129 getConstantVRegValWithLookThrough(unsigned VReg, const MachineRegisterInfo &MRI,
133 const MachineRegisterInfo &MRI);
139 const MachineRegisterInfo &MRI);
145 const MachineRegisterInfo &MRI);
156 const MachineRegisterInfo &MRI);
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| D | LegalizationArtifactCombiner.h | 28 MachineRegisterInfo &MRI; variable
44 LegalizationArtifactCombiner(MachineIRBuilder &B, MachineRegisterInfo &MRI, in LegalizationArtifactCombiner() argument
46 : Builder(B), MRI(MRI), LI(LI) {} in LegalizationArtifactCombiner()
59 if (mi_match(SrcReg, MRI, m_GTrunc(m_Reg(TruncSrc)))) { in tryCombineAnyExt()
63 markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts); in tryCombineAnyExt()
70 if (mi_match(SrcReg, MRI, in tryCombineAnyExt()
82 auto *SrcMI = MRI.getVRegDef(SrcReg); in tryCombineAnyExt()
84 const LLT &DstTy = MRI.getType(DstReg); in tryCombineAnyExt()
108 if (mi_match(SrcReg, MRI, m_GTrunc(m_Reg(TruncSrc)))) { in tryCombineZExt()
109 LLT DstTy = MRI.getType(DstReg); in tryCombineZExt()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMInstructionSelector.cpp | 48 MachineRegisterInfo &MRI) const;
60 bool selectGlobal(MachineInstrBuilder &MIB, MachineRegisterInfo &MRI) const;
61 bool selectSelect(MachineInstrBuilder &MIB, MachineRegisterInfo &MRI) const;
66 bool validOpRegPair(MachineRegisterInfo &MRI, unsigned LHS, unsigned RHS,
70 bool validReg(MachineRegisterInfo &MRI, unsigned Reg, unsigned ExpectedSize,
188 MachineRegisterInfo &MRI, in guessRegClass() argument
191 const RegisterBank *RegBank = RBI.getRegBank(Reg, MRI, TRI); in guessRegClass()
194 const unsigned Size = MRI.getType(Reg).getSizeInBits(); in guessRegClass()
214 MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, in selectCopy() argument
220 const TargetRegisterClass *RC = guessRegClass(DstReg, MRI, TRI, RBI); in selectCopy()
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| D | ARMRegisterBankInfo.cpp | 226 const MachineRegisterInfo &MRI = MF.getRegInfo(); in getInstrMapping() local
235 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
270 LLT LargeTy = MRI.getType(MI.getOperand(1).getReg()); in getInstrMapping()
280 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
293 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
300 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
314 LLT ToTy = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
315 LLT FromTy = MRI.getType(MI.getOperand(1).getReg()); in getInstrMapping()
323 LLT ToTy = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
324 LLT FromTy = MRI.getType(MI.getOperand(1).getReg()); in getInstrMapping()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyRegColoring.cpp | 65 static float computeWeight(const MachineRegisterInfo *MRI, in computeWeight() argument
69 for (MachineOperand &MO : MRI->reg_nodbg_operands(VReg)) in computeWeight()
88 MachineRegisterInfo *MRI = &MF.getRegInfo(); in runOnMachineFunction() local
95 unsigned NumVRegs = MRI->getNumVirtRegs(); in runOnMachineFunction()
105 if (MRI->use_empty(VReg)) in runOnMachineFunction()
110 LI->weight = computeWeight(MRI, MBFI, VReg); in runOnMachineFunction()
120 llvm::sort(SortedIntervals, [MRI](LiveInterval *LHS, LiveInterval *RHS) { in runOnMachineFunction()
121 if (MRI->isLiveIn(LHS->reg) != MRI->isLiveIn(RHS->reg)) in runOnMachineFunction()
122 return MRI->isLiveIn(LHS->reg); in runOnMachineFunction()
140 const TargetRegisterClass *RC = MRI->getRegClass(Old); in runOnMachineFunction()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsRegisterBankInfo.cpp | 173 Register Reg, const MachineRegisterInfo &MRI) { in addDefUses() argument
174 assert(!MRI.getType(Reg).isPointer() && in addDefUses()
176 for (MachineInstr &UseMI : MRI.use_instructions(Reg)) { in addDefUses()
181 addDefUses(NonCopyInstr->getOperand(0).getReg(), MRI); in addDefUses()
188 Register Reg, const MachineRegisterInfo &MRI) { in addUseDef() argument
189 assert(!MRI.getType(Reg).isPointer() && in addUseDef()
191 MachineInstr *DefMI = MRI.getVRegDef(Reg); in addUseDef()
199 const MachineRegisterInfo &MRI = MF.getRegInfo(); in skipCopiesOutgoing() local
203 MRI.hasOneUse(Ret->getOperand(0).getReg())) { in skipCopiesOutgoing()
204 Ret = &(*MRI.use_instr_begin(Ret->getOperand(0).getReg())); in skipCopiesOutgoing()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | ModuloSchedule.cpp | 85 for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(Reg), in expand()
86 EI = MRI.use_end(); in expand()
336 MachineRegisterInfo &MRI, in replaceRegUsesAfterLoop() argument
338 for (MachineRegisterInfo::use_iterator I = MRI.use_begin(FromReg), in replaceRegUsesAfterLoop()
339 E = MRI.use_end(); in replaceRegUsesAfterLoop()
353 MachineRegisterInfo &MRI) { in hasUseAfterLoop() argument
354 for (MachineRegisterInfo::use_iterator I = MRI.use_begin(Reg), in hasUseAfterLoop()
355 E = MRI.use_end(); in hasUseAfterLoop()
400 int LoopValStage = Schedule.getStage(MRI.getVRegDef(LoopVal)); in generateExistingPhis()
451 MachineInstr *InstOp1 = MRI.getVRegDef(PhiOp1); in generateExistingPhis()
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| D | RegAllocBase.cpp | 61 MRI = &vrm.getRegInfo(); in init()
65 MRI->freezeReservedRegs(vrm.getMachineFunction()); in init()
75 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) { in seedLiveRegs()
77 if (MRI->reg_nodbg_empty(Reg)) in seedLiveRegs()
93 if (MRI->reg_nodbg_empty(VirtReg->reg)) { in allocatePhysRegs()
107 << TRI->getRegClassName(MRI->getRegClass(VirtReg->reg)) in allocatePhysRegs()
120 I = MRI->reg_instr_begin(VirtReg->reg), E = MRI->reg_instr_end(); in allocatePhysRegs()
137 RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front()); in allocatePhysRegs()
149 if (MRI->reg_nodbg_empty(SplitVirtReg->reg)) { in allocatePhysRegs()
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