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1 /*
2  * hinfc_common.h
3  *
4  * The Flash Memory Controller v100 Device Driver for hisilicon.
5  *
6  * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED.
7  *
8  * This program is free software; you can redistribute  it and/or modify it
9  * under  the terms of  the GNU General  Public License as published by the
10  * Free Software Foundation;  either version 2 of the  License, or (at your
11  * option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
20  *
21  */
22 
23 #ifndef __HINFC_COMMON_H__
24 #define __HINFC_COMMON_H__
25 
26 /*****************************************************************************/
27 #include <asm/io.h>
28 #include <common.h>
29 #include <linux/mtd/rawnand.h>
30 #include <match_table.h>
31 #include <hifmc_common.h>
32 
33 /*****************************************************************************/
34 #define _512B                               512
35 #define _2K                                 2048
36 #define _4K                                 4096
37 #define _8K                                 8192
38 #define _16K                                16384
39 
40 /*****************************************************************************/
41 #define NAND_PAGE_512B                   0
42 #define NAND_PAGE_1K                     1
43 #define NAND_PAGE_2K                     2
44 #define NAND_PAGE_4K                     3
45 #define NAND_PAGE_8K                     4
46 #define NAND_PAGE_16K                    5
47 #define NAND_PAGE_32K                    6
48 
49 /*****************************************************************************/
50 #define NAND_ECC_NONE                    0
51 #define NAND_ECC_0BIT                    0
52 #define NAND_ECC_1BIT                    1
53 #define NAND_ECC_1BIT_512                1
54 #define NAND_ECC_4BIT                    2
55 #define NAND_ECC_4BIT_512                2
56 #define NAND_ECC_4BYTE                   2
57 #define NAND_ECC_8BIT                    2
58 #define NAND_ECC_8BIT_512                3
59 #define NAND_ECC_8BYTE                   3
60 #define NAND_ECC_13BIT                   4
61 #define NAND_ECC_16BIT                   5
62 #define NAND_ECC_18BIT                   6
63 #define NAND_ECC_24BIT                   7
64 #define NAND_ECC_27BIT                   8
65 #define NAND_ECC_28BIT                   9
66 #define NAND_ECC_32BIT                   10
67 #define NAND_ECC_40BIT                   11
68 #define NAND_ECC_41BIT                   12
69 #define NAND_ECC_42BIT                   13
70 #define NAND_ECC_48BIT                   14
71 #define NAND_ECC_60BIT                   15
72 #define NAND_ECC_64BIT                   16
73 #define NAND_ECC_72BIT                   17
74 #define NAND_ECC_80BIT                   18
75 
76 #define ERSTR_HARDWARE                   "Hardware configuration error."
77 #define ERSTR_DRIVER                     "Driver does not support."
78 
79 #define DISABLE                          0
80 #define ENABLE                           1
81 
82 #define is_randomizer(_dev)        ((_dev)->flags & NAND_RANDOMIZER)
83 #define is_hw_auto(_dev)           ((_dev)->flags & NAND_HW_AUTO)
84 #define is_synchronous(_dev)       ((_dev)->flags & NAND_SYNCHRONOUS)
85 #define is_config_done(_dev)       ((_dev)->flags & NAND_CONFIG_DONE)
86 #define is_synchronous_boot(_dev)  ((_dev)->flags & NAND_SYNCHRONOUS_BOOT)
87 
88 #define NAND_PAGE_SHIFT                  9 /* 512 */
89 
90 #if defined(CONFIG_NAND_FLASH_HISNFC100) \
91 	|| defined(CONFIG_NAND_FLASH_HINFC610) \
92 	|| defined(CONFIG_HIFMC_SPI_NAND) \
93 	|| defined(CONFIG_HIFMC_NAND)
94 /*****************************************************************************/
95 enum ecc_type {
96 	ET_ECC_NONE    = 0x00,
97 	ET_ECC_1BIT    = 0x01,
98 	ET_ECC_4BIT    = 0x02,
99 	ET_ECC_8BIT    = 0x03,
100 	ET_ECC_24BIT1K = 0x04,
101 	ET_ECC_40BIT1K = 0x05,
102 	ET_ECC_64BIT1K = 0x06,
103 };
104 
105 enum page_type {
106 	PT_PAGESIZE_512   = 0x00,
107 	PT_PAGESIZE_2K    = 0x01,
108 	PT_PAGESIZE_4K    = 0x02,
109 	PT_PAGESIZE_8K    = 0x03,
110 	PT_PAGESIZE_16K   = 0x04,
111 };
112 
113 struct nand_config_info {
114 	unsigned int pagetype;
115 	unsigned int ecctype;
116 	unsigned int oobsize;
117 	struct nand_ecclayout *layout;
118 };
119 
120 struct hinfc_host;
121 
122 struct read_retry_t {
123 	int type;
124 	int count;
125 	int (*set_rr_param)(struct hinfc_host *host, int param);
126 	int (*get_rr_param)(struct hinfc_host *host);
127 	int (*reset_rr_param)(struct hinfc_host *host);
128 	int (*enable_enhanced_slc)(struct hinfc_host *host, int enable);
129 };
130 #endif
131 
132 /*****************************************************************************/
133 struct nand_flash_dev_ex {
134 	struct nand_flash_dev flash_dev;
135 
136 	char *start_type;
137 	unsigned char ids[8];  /* 8Byte  */
138 	int oobsize;
139 	int ecctype;
140 
141 #define NAND_RANDOMIZER        0x01 /* nand chip need randomizer */
142 #define NAND_HW_AUTO           0x02 /* controller support hardware auto config */
143 #define NAND_SYNCHRONOUS       0x04 /* nand chip support synchronous */
144 #define NAND_ASYNCHRONOUS      0x08 /* nand chip support asynchronous */
145 #define NAND_SYNCHRONOUS_BOOT  0x10 /* nand boot from synchronous mode */
146 #define NAND_CONFIG_DONE       0x20 /* current controller config finish */
147 	int flags;
148 	int is_randomizer;
149 #define NAND_RR_NONE                   0x00
150 #define NAND_RR_HYNIX_BG_BDIE          0x10
151 #define NAND_RR_HYNIX_BG_CDIE          0x11
152 #define NAND_RR_HYNIX_CG_ADIE          0x12
153 #define NAND_RR_MICRON                 0x20
154 #define NAND_RR_SAMSUNG                0x30
155 #define NAND_RR_TOSHIBA_24NM           0x40
156 #define NAND_RR_TOSHIBA_19NM           0x41
157 #define NAND_RR_MASK                   0xF0
158 	int read_retry_type;
159 
160 	int hostver; /* host controller version. */
161 };
162 
163 /*****************************************************************************/
164 const char *nand_ecc_name(int type);
165 
166 const char *nand_page_name(int type);
167 
168 int nandpage_size2type(int size);
169 
170 int nandpage_type2size(int size);
171 
172 /*****************************************************************************/
173 extern int nand_get_ecctype(void);
174 
175 extern struct nand_flash_dev *(*get_flash_type)(struct mtd_info *mtd,
176 		struct nand_chip *chip, unsigned char *id);
177 
178 extern int (*nand_oob_resize)(struct mtd_info *mtd);
179 
180 /*****************************************************************************/
181 extern unsigned char match_ecc_type_to_yaffs(unsigned char type);
182 
183 extern unsigned char match_page_reg_to_type(unsigned char reg);
184 
185 extern unsigned char match_page_type_to_reg(unsigned char type);
186 
187 extern const char *match_page_type_to_str(unsigned char type);
188 
189 /*****************************************************************************/
190 extern unsigned char match_ecc_reg_to_type(unsigned char reg);
191 
192 extern unsigned char match_ecc_type_to_reg(unsigned char type);
193 
194 extern const char *match_ecc_type_to_str(unsigned char type);
195 
196 /*****************************************************************************/
197 extern unsigned char match_page_size_to_type(unsigned int size);
198 
199 extern unsigned int match_page_type_to_size(unsigned char type);
200 
201 #endif /* End of __HINFC_COMMON_H__ */
202 
203