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Searched refs:NUM_TX_DESC (Results 1 – 8 of 8) sorted by relevance

/third_party/uboot/u-boot-2020.01/drivers/net/
Ddc2114x.c118 #define NUM_TX_DESC 1 /* Number of TX descriptors */ macro
120 #define NUM_TX_DESC 4 macro
136 static struct de4x5_desc tx_ring[NUM_TX_DESC] __attribute__ ((aligned(32))); /* TX descriptor ring …
344 for (i=0; i < NUM_TX_DESC; i++) { in dc21x4x_init()
350 tx_ring[i].next = cpu_to_le32(phys_to_bus((u32) &tx_ring[(i+1) % NUM_TX_DESC])); in dc21x4x_init()
357 txRingSize = NUM_TX_DESC; in dc21x4x_init()
419 tx_new = (tx_new+1) % NUM_TX_DESC; in dc21x4x_send()
517 tx_new = (tx_new+1) % NUM_TX_DESC; in send_setup_frame()
Drtl8169.c86 #define NUM_TX_DESC 1 /* Number of Tx descriptor registers */ macro
316 DEFINE_ALIGN_BUFFER(u8, txb, NUM_TX_DESC * RX_BUF_SIZE, RTL8169_ALIGN);
335 unsigned char *Tx_skbuff[NUM_TX_DESC];
612 int entry = tpc->cur_tx % NUM_TX_DESC; in rtl_send_common()
641 if (entry != (NUM_TX_DESC - 1)) { in rtl_send_common()
817 memset(tpc->TxDescArray, 0x0, NUM_TX_DESC * sizeof(struct TxDesc)); in rtl8169_init_ring()
820 for (i = 0; i < NUM_TX_DESC; i++) { in rtl8169_init_ring()
1108 tpc->TxDescArray = rtl_alloc_descs(NUM_TX_DESC); in rtl_init()
Deepro100.c192 #define NUM_TX_DESC 1 /* Number of TX descriptors */ macro
197 static struct TxFD tx_ring[NUM_TX_DESC]; /* TX descriptor ring */
519 tx_next = ((tx_next + 1) % NUM_TX_DESC); in eepro100_init()
555 tx_next = ((tx_next + 1) % NUM_TX_DESC); in eepro100_init()
606 tx_next = (tx_next + 1) % NUM_TX_DESC; in eepro100_send()
895 for (i = 0; i < NUM_TX_DESC; i++) { in purge_tx_ring()
Dmt7628-eth.c119 #define NUM_TX_DESC 4 macro
411 idx = (idx + 1) % NUM_TX_DESC; in mt7628_eth_send()
488 for (i = 0; i < NUM_TX_DESC; i++) { in mt7628_eth_start()
510 writel(NUM_TX_DESC, base + TX_MAX_CNT0); in mt7628_eth_start()
582 sizeof(*priv->tx_ring) * NUM_TX_DESC)); in mt7628_eth_probe()
Dmtk_eth.c27 #define NUM_TX_DESC 24 macro
29 #define TX_TOTAL_BUF_SIZE (NUM_TX_DESC * PKTSIZE_ALIGN)
827 memset(priv->tx_ring_noc, 0, NUM_TX_DESC * sizeof(struct pdma_txdesc)); in mtk_eth_fifo_init()
836 for (i = 0; i < NUM_TX_DESC; i++) { in mtk_eth_fifo_init()
853 mtk_pdma_write(priv, TX_MAX_CNT_REG(0), NUM_TX_DESC); in mtk_eth_fifo_init()
949 priv->tx_cpu_owner_idx0 = (priv->tx_cpu_owner_idx0 + 1) % NUM_TX_DESC; in mtk_eth_send()
1013 noncached_alloc(sizeof(struct pdma_txdesc) * NUM_TX_DESC, in mtk_eth_probe()
Drtl8139.c90 #define NUM_TX_DESC 4 /* Number of Tx descriptor registers. */ macro
440 cur_tx = (cur_tx + 1) % NUM_TX_DESC; in rtl_transmit()
Dsh_eth.c116 if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC) in sh_eth_send_common()
195 u32 alloc_desc_size = NUM_TX_DESC * sizeof(struct tx_desc_s); in sh_eth_tx_desc_init()
219 for (cur_tx_desc = port_info->tx_desc_base, i = 0; i < NUM_TX_DESC; in sh_eth_tx_desc_init()
Dsh_eth.h50 #define NUM_TX_DESC 8 macro