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Searched refs:PERI_CRG_DDRT (Results 1 – 15 of 15) sorted by relevance

/third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3516dv300/
Dddr_training_custom.c23 #define PERI_CRG_DDRT 0x198U macro
40 ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_save()
42 ddr_write(ddrt_clk_reg, CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_save()
44 ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_save()
46 ddr_write(ddrt_clk_reg, CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_save()
58 ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_restore()
60 ddr_write(ddrt_clk_reg, CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_restore()
62 ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_restore()
64 ddr_write(ddrt_clk_reg, CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_restore()
/third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3516av300/
Dddr_training_custom.c23 #define PERI_CRG_DDRT 0x198U macro
40 ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_save()
42 ddr_write(ddrt_clk_reg, CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_save()
44 ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_save()
46 ddr_write(ddrt_clk_reg, CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_save()
58 ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_restore()
60 ddr_write(ddrt_clk_reg, CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_restore()
62 ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_restore()
64 ddr_write(ddrt_clk_reg, CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_restore()
/third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3516cv500/
Dddr_training_custom.c23 #define PERI_CRG_DDRT 0x198U macro
40 ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_save()
42 ddr_write(ddrt_clk_reg, CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_save()
44 ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_save()
46 ddr_write(ddrt_clk_reg, CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_save()
58 ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_restore()
60 ddr_write(ddrt_clk_reg, CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_restore()
62 ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_restore()
64 ddr_write(ddrt_clk_reg, CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_restore()
/third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3516dv200/
Dddr_training_custom.c23 #define PERI_CRG_DDRT 0x198U macro
48 reg->custom.ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_save()
50 ddr_write(reg->custom.ddrt_clk_reg | (1U << 1), CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_save()
53 ddr_write(ddr_read(CRG_REG_BASE + PERI_CRG_DDRT) & (~(1U << 0)), CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_save()
74 ddr_write(reg->custom.ddrt_clk_reg, CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_restore()
/third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3516ev200/
Dddr_training_custom.c23 #define PERI_CRG_DDRT 0x198U macro
48 reg->custom.ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_save()
50 ddr_write(reg->custom.ddrt_clk_reg | (1U << 1), CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_save()
53 ddr_write(ddr_read(CRG_REG_BASE + PERI_CRG_DDRT) & (~(1U << 0)), CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_save()
74 ddr_write(reg->custom.ddrt_clk_reg, CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_restore()
/third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3518ev300/
Dddr_training_custom.c23 #define PERI_CRG_DDRT 0x198U macro
48 reg->custom.ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_save()
50 ddr_write(reg->custom.ddrt_clk_reg | (1U << 1), CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_save()
53 ddr_write(ddr_read(CRG_REG_BASE + PERI_CRG_DDRT) & (~(1U << 0)), CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_save()
74 ddr_write(reg->custom.ddrt_clk_reg, CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_restore()
/third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3516ev300/
Dddr_training_custom.c23 #define PERI_CRG_DDRT 0x198U macro
48 reg->custom.ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_save()
50 ddr_write(reg->custom.ddrt_clk_reg | (1U << 1), CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_save()
53 ddr_write(ddr_read(CRG_REG_BASE + PERI_CRG_DDRT) & (~(1U << 0)), CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_save()
74 ddr_write(reg->custom.ddrt_clk_reg, CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_restore()
/third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3535av100/
Dddr_training_custom.c23 #define PERI_CRG_DDRT 0x22A0U macro
85 relate_reg->custom.ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG_DDRT); in ddr_boot_cmd_save()
87 …_write(relate_reg->custom.ddrt_clk_reg | (0x1 << DDRTEST0_CKEN_BIT), CRG_REG_BASE + PERI_CRG_DDRT); in ddr_boot_cmd_save()
90 …ddr_write(ddr_read(CRG_REG_BASE + PERI_CRG_DDRT) & (~(0x1 << DDRTEST0_SRST_REQ_BIT)), CRG_REG_BASE… in ddr_boot_cmd_save()
114 ddr_write(relate_reg->custom.ddrt_clk_reg, CRG_REG_BASE + PERI_CRG_DDRT); in ddr_boot_cmd_restore()
/third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3520dv500/
Dddr_training_custom.c23 #define PERI_CRG_DDRT 0x22A0U macro
83 relate_reg->custom.ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG_DDRT); in ddr_boot_cmd_save()
85 …_write(relate_reg->custom.ddrt_clk_reg | (0x1 << DDRTEST0_CKEN_BIT), CRG_REG_BASE + PERI_CRG_DDRT); in ddr_boot_cmd_save()
88 …ddr_write(ddr_read(CRG_REG_BASE + PERI_CRG_DDRT) & (~(0x1 << DDRTEST0_SRST_REQ_BIT)), CRG_REG_BASE… in ddr_boot_cmd_save()
112 ddr_write(relate_reg->custom.ddrt_clk_reg, CRG_REG_BASE + PERI_CRG_DDRT); in ddr_boot_cmd_restore()
/third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3521dv200/
Dddr_training_custom.c23 #define PERI_CRG_DDRT 0x22A0U macro
83 relate_reg->custom.ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG_DDRT); in ddr_boot_cmd_save()
85 …_write(relate_reg->custom.ddrt_clk_reg | (0x1 << DDRTEST0_CKEN_BIT), CRG_REG_BASE + PERI_CRG_DDRT); in ddr_boot_cmd_save()
88 …ddr_write(ddr_read(CRG_REG_BASE + PERI_CRG_DDRT) & (~(0x1 << DDRTEST0_SRST_REQ_BIT)), CRG_REG_BASE… in ddr_boot_cmd_save()
112 ddr_write(relate_reg->custom.ddrt_clk_reg, CRG_REG_BASE + PERI_CRG_DDRT); in ddr_boot_cmd_restore()
/third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3531dv200/
Dddr_training_custom.c23 #define PERI_CRG_DDRT 0x22A0U macro
85 relate_reg->custom.ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG_DDRT); in ddr_boot_cmd_save()
87 …_write(relate_reg->custom.ddrt_clk_reg | (0x1 << DDRTEST0_CKEN_BIT), CRG_REG_BASE + PERI_CRG_DDRT); in ddr_boot_cmd_save()
90 …ddr_write(ddr_read(CRG_REG_BASE + PERI_CRG_DDRT) & (~(0x1 << DDRTEST0_SRST_REQ_BIT)), CRG_REG_BASE… in ddr_boot_cmd_save()
114 ddr_write(relate_reg->custom.ddrt_clk_reg, CRG_REG_BASE + PERI_CRG_DDRT); in ddr_boot_cmd_restore()
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3516ev200/
Dlowlevel_init_v300.c292 #define PERI_CRG_DDRT 0x198 macro
319 reg->custom.ddrt_clk_reg = readl(CRG_REG_BASE + PERI_CRG_DDRT); in ddr_boot_prepare()
321 writel(reg->custom.ddrt_clk_reg | (0x1 << 1), CRG_REG_BASE + PERI_CRG_DDRT); in ddr_boot_prepare()
324 writel(readl(CRG_REG_BASE + PERI_CRG_DDRT) & (~(0x1 << 0)), in ddr_boot_prepare()
325 CRG_REG_BASE + PERI_CRG_DDRT); in ddr_boot_prepare()
351 writel(reg->custom.ddrt_clk_reg, CRG_REG_BASE + PERI_CRG_DDRT); in ddr_boot_restore()
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3516ev300/
Dlowlevel_init_v300.c288 #define PERI_CRG_DDRT 0x198 macro
315 reg->custom.ddrt_clk_reg = readl(CRG_REG_BASE + PERI_CRG_DDRT); in ddr_boot_prepare()
317 writel(reg->custom.ddrt_clk_reg | (0x1 << 1), CRG_REG_BASE + PERI_CRG_DDRT); in ddr_boot_prepare()
320 writel(readl(CRG_REG_BASE + PERI_CRG_DDRT) & (~(0x1 << 0)), in ddr_boot_prepare()
321 CRG_REG_BASE + PERI_CRG_DDRT); in ddr_boot_prepare()
347 writel(reg->custom.ddrt_clk_reg, CRG_REG_BASE + PERI_CRG_DDRT); in ddr_boot_restore()
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3516dv200/
Dlowlevel_init_v300.c291 #define PERI_CRG_DDRT 0x198 macro
318 reg->custom.ddrt_clk_reg = readl(CRG_REG_BASE + PERI_CRG_DDRT); in ddr_boot_prepare()
320 writel(reg->custom.ddrt_clk_reg | (0x1 << 1), CRG_REG_BASE + PERI_CRG_DDRT); in ddr_boot_prepare()
323 writel(readl(CRG_REG_BASE + PERI_CRG_DDRT) & (~(0x1 << 0)), in ddr_boot_prepare()
324 CRG_REG_BASE + PERI_CRG_DDRT); in ddr_boot_prepare()
350 writel(reg->custom.ddrt_clk_reg, CRG_REG_BASE + PERI_CRG_DDRT); in ddr_boot_restore()
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3518ev300/
Dlowlevel_init_v300.c293 #define PERI_CRG_DDRT 0x198 macro
320 reg->custom.ddrt_clk_reg = readl(CRG_REG_BASE + PERI_CRG_DDRT); in ddr_boot_prepare()
322 writel(reg->custom.ddrt_clk_reg | (0x1 << 1), CRG_REG_BASE + PERI_CRG_DDRT); in ddr_boot_prepare()
325 writel(readl(CRG_REG_BASE + PERI_CRG_DDRT) & (~(0x1 << 0)), in ddr_boot_prepare()
326 CRG_REG_BASE + PERI_CRG_DDRT); in ddr_boot_prepare()
352 writel(reg->custom.ddrt_clk_reg, CRG_REG_BASE + PERI_CRG_DDRT); in ddr_boot_restore()