1 // SPDX-License-Identifier: GPL-2.0+
2 /**
3 * PCIe SERDES driver for AM654x SoC
4 *
5 * Copyright (C) 2018 Texas Instruments
6 * Author: Kishon Vijay Abraham I <kishon@ti.com>
7 */
8
9 #include <common.h>
10 #include <clk-uclass.h>
11 #include <dm.h>
12 #include <dm/device.h>
13 #include <dm/lists.h>
14 #include <dt-bindings/phy/phy.h>
15 #include <generic-phy.h>
16 #include <asm/io.h>
17 #include <asm/arch/sys_proto.h>
18 #include <power-domain.h>
19 #include <regmap.h>
20 #include <syscon.h>
21
22 #define CMU_R07C 0x7c
23 #define CMU_MASTER_CDN_O BIT(24)
24
25 #define COMLANE_R138 0xb38
26 #define CONFIG_VERSION_REG_MASK GENMASK(23, 16)
27 #define CONFIG_VERSION_REG_SHIFT 16
28 #define VERSION 0x70
29
30 #define COMLANE_R190 0xb90
31 #define L1_MASTER_CDN_O BIT(9)
32
33 #define COMLANE_R194 0xb94
34 #define CMU_OK_I_0 BIT(19)
35
36 #define SERDES_CTRL 0x1fd0
37 #define POR_EN BIT(29)
38
39 #define WIZ_LANEXCTL_STS 0x1fe0
40 #define TX0_ENABLE_OVL BIT(31)
41 #define TX0_ENABLE_MASK GENMASK(30, 29)
42 #define TX0_ENABLE_SHIFT 29
43 #define TX0_DISABLE_STATE 0x0
44 #define TX0_SLEEP_STATE 0x1
45 #define TX0_SNOOZE_STATE 0x2
46 #define TX0_ENABLE_STATE 0x3
47 #define RX0_ENABLE_OVL BIT(15)
48 #define RX0_ENABLE_MASK GENMASK(14, 13)
49 #define RX0_ENABLE_SHIFT 13
50 #define RX0_DISABLE_STATE 0x0
51 #define RX0_SLEEP_STATE 0x1
52 #define RX0_SNOOZE_STATE 0x2
53 #define RX0_ENABLE_STATE 0x3
54
55 #define WIZ_PLL_CTRL 0x1ff4
56 #define PLL_ENABLE_OVL BIT(31)
57 #define PLL_ENABLE_MASK GENMASK(30, 29)
58 #define PLL_ENABLE_SHIFT 29
59 #define PLL_DISABLE_STATE 0x0
60 #define PLL_SLEEP_STATE 0x1
61 #define PLL_SNOOZE_STATE 0x2
62 #define PLL_ENABLE_STATE 0x3
63 #define PLL_OK BIT(28)
64
65 #define PLL_LOCK_TIME 1000 /* in milliseconds */
66 #define SLEEP_TIME 100 /* in microseconds */
67
68 #define LANE_USB3 0x0
69 #define LANE_PCIE0_LANE0 0x1
70
71 #define LANE_PCIE1_LANE0 0x0
72 #define LANE_PCIE0_LANE1 0x1
73
74 #define SERDES_NUM_CLOCKS 3
75
76 /* SERDES control MMR bit offsets */
77 #define SERDES_CTL_LANE_FUNC_SEL_SHIFT 0
78 #define SERDES_CTL_LANE_FUNC_SEL_MASK GENMASK(1, 0)
79 #define SERDES_CTL_CLK_SEL_SHIFT 4
80 #define SERDES_CTL_CLK_SEL_MASK GENMASK(7, 4)
81
82 /**
83 * struct serdes_am654_mux_clk_data - clock controller information structure
84 */
85 struct serdes_am654_mux_clk_data {
86 struct regmap *regmap;
87 struct clk_bulk parents;
88 };
89
serdes_am654_mux_clk_probe(struct udevice * dev)90 static int serdes_am654_mux_clk_probe(struct udevice *dev)
91 {
92 struct serdes_am654_mux_clk_data *data = dev_get_priv(dev);
93 struct udevice *syscon;
94 struct regmap *regmap;
95 int ret;
96
97 debug("%s(dev=%s)\n", __func__, dev->name);
98
99 if (!data)
100 return -ENOMEM;
101
102 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
103 "ti,serdes-clk", &syscon);
104 if (ret) {
105 dev_err(dev, "unable to find syscon device\n");
106 return ret;
107 }
108
109 regmap = syscon_get_regmap(syscon);
110 if (IS_ERR(regmap)) {
111 dev_err(dev, "Fail to get Syscon regmap\n");
112 return PTR_ERR(regmap);
113 }
114
115 data->regmap = regmap;
116
117 ret = clk_get_bulk(dev, &data->parents);
118 if (ret) {
119 dev_err(dev, "Failed to obtain parent clocks\n");
120 return ret;
121 }
122
123 return 0;
124 }
125
126 static int mux_table[SERDES_NUM_CLOCKS][3] = {
127 /*
128 * The entries represent values for selecting between
129 * {left input, external reference clock, right input}
130 * Only one of Left Output or Right Output should be used since
131 * both left and right output clock uses the same bits and modifying
132 * one clock will impact the other.
133 */
134 { BIT(2), 0, BIT(0) }, /* Mux of CMU refclk */
135 { -1, BIT(3), BIT(1) }, /* Mux of Left Output */
136 { BIT(1), BIT(3) | BIT(1), -1 }, /* Mux of Right Output */
137 };
138
serdes_am654_mux_clk_set_parent(struct clk * clk,struct clk * parent)139 static int serdes_am654_mux_clk_set_parent(struct clk *clk, struct clk *parent)
140 {
141 struct serdes_am654_mux_clk_data *data = dev_get_priv(clk->dev);
142 u32 val;
143 int i;
144
145 debug("%s(clk=%s, parent=%s)\n", __func__, clk->dev->name,
146 parent->dev->name);
147
148 /*
149 * Since we have the same device-tree node represent both the
150 * clock and serdes device, we have two devices associated with
151 * the serdes node. assigned-clocks for this node is processed twice,
152 * once for the clock device and another time for the serdes
153 * device. When it is processed for the clock device, it is before
154 * the probe for clock device has been called. We ignore this case
155 * and rely on assigned-clocks to be processed correctly for the
156 * serdes case.
157 */
158 if (!data->regmap)
159 return 0;
160
161 for (i = 0; i < data->parents.count; i++) {
162 if (clk_is_match(&data->parents.clks[i], parent))
163 break;
164 }
165
166 if (i >= data->parents.count)
167 return -EINVAL;
168
169 val = mux_table[clk->id][i];
170 val <<= SERDES_CTL_CLK_SEL_SHIFT;
171
172 regmap_update_bits(data->regmap, 0, SERDES_CTL_CLK_SEL_MASK, val);
173
174 return 0;
175 }
176
177 static struct clk_ops serdes_am654_mux_clk_ops = {
178 .set_parent = serdes_am654_mux_clk_set_parent,
179 };
180
181 U_BOOT_DRIVER(serdes_am654_mux_clk) = {
182 .name = "ti-serdes-am654-mux-clk",
183 .id = UCLASS_CLK,
184 .probe = serdes_am654_mux_clk_probe,
185 .priv_auto_alloc_size = sizeof(struct serdes_am654_mux_clk_data),
186 .ops = &serdes_am654_mux_clk_ops,
187 };
188
189 struct serdes_am654 {
190 struct regmap *regmap;
191 struct regmap *serdes_ctl;
192 };
193
serdes_am654_enable_pll(struct serdes_am654 * phy)194 static int serdes_am654_enable_pll(struct serdes_am654 *phy)
195 {
196 u32 mask = PLL_ENABLE_OVL | PLL_ENABLE_MASK;
197 u32 val = PLL_ENABLE_OVL | (PLL_ENABLE_STATE << PLL_ENABLE_SHIFT);
198
199 regmap_update_bits(phy->regmap, WIZ_PLL_CTRL, mask, val);
200
201 return regmap_read_poll_timeout(phy->regmap, WIZ_PLL_CTRL, val,
202 val & PLL_OK, 1000, PLL_LOCK_TIME);
203 }
204
serdes_am654_disable_pll(struct serdes_am654 * phy)205 static void serdes_am654_disable_pll(struct serdes_am654 *phy)
206 {
207 u32 mask = PLL_ENABLE_OVL | PLL_ENABLE_MASK;
208
209 regmap_update_bits(phy->regmap, WIZ_PLL_CTRL, mask, 0);
210 }
211
serdes_am654_enable_txrx(struct serdes_am654 * phy)212 static int serdes_am654_enable_txrx(struct serdes_am654 *phy)
213 {
214 u32 mask;
215 u32 val;
216
217 /* Enable TX */
218 mask = TX0_ENABLE_OVL | TX0_ENABLE_MASK;
219 val = TX0_ENABLE_OVL | (TX0_ENABLE_STATE << TX0_ENABLE_SHIFT);
220 regmap_update_bits(phy->regmap, WIZ_LANEXCTL_STS, mask, val);
221
222 /* Enable RX */
223 mask = RX0_ENABLE_OVL | RX0_ENABLE_MASK;
224 val = RX0_ENABLE_OVL | (RX0_ENABLE_STATE << RX0_ENABLE_SHIFT);
225 regmap_update_bits(phy->regmap, WIZ_LANEXCTL_STS, mask, val);
226
227 return 0;
228 }
229
serdes_am654_disable_txrx(struct serdes_am654 * phy)230 static int serdes_am654_disable_txrx(struct serdes_am654 *phy)
231 {
232 u32 mask;
233
234 /* Disable TX */
235 mask = TX0_ENABLE_OVL | TX0_ENABLE_MASK;
236 regmap_update_bits(phy->regmap, WIZ_LANEXCTL_STS, mask, 0);
237
238 /* Disable RX */
239 mask = RX0_ENABLE_OVL | RX0_ENABLE_MASK;
240 regmap_update_bits(phy->regmap, WIZ_LANEXCTL_STS, mask, 0);
241
242 return 0;
243 }
244
serdes_am654_power_on(struct phy * x)245 static int serdes_am654_power_on(struct phy *x)
246 {
247 struct serdes_am654 *phy = dev_get_priv(x->dev);
248 int ret;
249 u32 val;
250
251 ret = serdes_am654_enable_pll(phy);
252 if (ret) {
253 dev_err(x->dev, "Failed to enable PLL\n");
254 return ret;
255 }
256
257 ret = serdes_am654_enable_txrx(phy);
258 if (ret) {
259 dev_err(x->dev, "Failed to enable TX RX\n");
260 return ret;
261 }
262
263 return regmap_read_poll_timeout(phy->regmap, COMLANE_R194, val,
264 val & CMU_OK_I_0, SLEEP_TIME,
265 PLL_LOCK_TIME);
266 }
267
serdes_am654_power_off(struct phy * x)268 static int serdes_am654_power_off(struct phy *x)
269 {
270 struct serdes_am654 *phy = dev_get_priv(x->dev);
271
272 serdes_am654_disable_txrx(phy);
273 serdes_am654_disable_pll(phy);
274
275 return 0;
276 }
277
serdes_am654_init(struct phy * x)278 static int serdes_am654_init(struct phy *x)
279 {
280 struct serdes_am654 *phy = dev_get_priv(x->dev);
281 u32 mask;
282 u32 val;
283
284 mask = CONFIG_VERSION_REG_MASK;
285 val = VERSION << CONFIG_VERSION_REG_SHIFT;
286 regmap_update_bits(phy->regmap, COMLANE_R138, mask, val);
287
288 val = CMU_MASTER_CDN_O;
289 regmap_update_bits(phy->regmap, CMU_R07C, val, val);
290
291 val = L1_MASTER_CDN_O;
292 regmap_update_bits(phy->regmap, COMLANE_R190, val, val);
293
294 return 0;
295 }
296
serdes_am654_reset(struct phy * x)297 static int serdes_am654_reset(struct phy *x)
298 {
299 struct serdes_am654 *phy = dev_get_priv(x->dev);
300 u32 val;
301
302 val = POR_EN;
303 regmap_update_bits(phy->regmap, SERDES_CTRL, val, val);
304 mdelay(1);
305 regmap_update_bits(phy->regmap, SERDES_CTRL, val, 0);
306
307 return 0;
308 }
309
serdes_am654_of_xlate(struct phy * x,struct ofnode_phandle_args * args)310 static int serdes_am654_of_xlate(struct phy *x,
311 struct ofnode_phandle_args *args)
312 {
313 struct serdes_am654 *phy = dev_get_priv(x->dev);
314
315 if (args->args_count != 2) {
316 dev_err(phy->dev, "Invalid DT PHY argument count: %d\n",
317 args->args_count);
318 return -EINVAL;
319 }
320
321 if (args->args[0] != PHY_TYPE_PCIE) {
322 dev_err(phy->dev, "Unrecognized PHY type: %d\n",
323 args->args[0]);
324 return -EINVAL;
325 }
326
327 x->id = args->args[0] | (args->args[1] << 16);
328
329 /* Setup mux mode using second argument */
330 regmap_update_bits(phy->serdes_ctl, 0, SERDES_CTL_LANE_FUNC_SEL_MASK,
331 args->args[1]);
332
333 return 0;
334 }
335
serdes_am654_bind(struct udevice * dev)336 static int serdes_am654_bind(struct udevice *dev)
337 {
338 int ret;
339
340 ret = device_bind_driver_to_node(dev->parent,
341 "ti-serdes-am654-mux-clk",
342 dev_read_name(dev), dev->node,
343 NULL);
344 if (ret) {
345 dev_err(dev, "%s: not able to bind clock driver\n", __func__);
346 return ret;
347 }
348
349 return 0;
350 }
351
serdes_am654_probe(struct udevice * dev)352 static int serdes_am654_probe(struct udevice *dev)
353 {
354 struct serdes_am654 *phy = dev_get_priv(dev);
355 struct power_domain serdes_pwrdmn;
356 struct regmap *serdes_ctl;
357 struct regmap *map;
358 int ret;
359
360 ret = regmap_init_mem(dev_ofnode(dev), &map);
361 if (ret)
362 return ret;
363
364 phy->regmap = map;
365
366 serdes_ctl = syscon_regmap_lookup_by_phandle(dev, "ti,serdes-clk");
367 if (IS_ERR(serdes_ctl)) {
368 dev_err(dev, "unable to find syscon device\n");
369 return PTR_ERR(serdes_ctl);
370 }
371
372 phy->serdes_ctl = serdes_ctl;
373
374 ret = power_domain_get_by_index(dev, &serdes_pwrdmn, 0);
375 if (ret) {
376 dev_err(dev, "failed to get power domain\n");
377 return ret;
378 }
379
380 ret = power_domain_on(&serdes_pwrdmn);
381 if (ret) {
382 dev_err(dev, "Power domain on failed\n");
383 return ret;
384 }
385
386 return 0;
387 }
388
389 static const struct udevice_id serdes_am654_phy_ids[] = {
390 {
391 .compatible = "ti,phy-am654-serdes",
392 },
393 };
394
395 static const struct phy_ops serdes_am654_phy_ops = {
396 .reset = serdes_am654_reset,
397 .init = serdes_am654_init,
398 .power_on = serdes_am654_power_on,
399 .power_off = serdes_am654_power_off,
400 .of_xlate = serdes_am654_of_xlate,
401 };
402
403 U_BOOT_DRIVER(am654_serdes_phy) = {
404 .name = "am654_serdes_phy",
405 .id = UCLASS_PHY,
406 .of_match = serdes_am654_phy_ids,
407 .bind = serdes_am654_bind,
408 .ops = &serdes_am654_phy_ops,
409 .probe = serdes_am654_probe,
410 .priv_auto_alloc_size = sizeof(struct serdes_am654),
411 };
412