Home
last modified time | relevance | path

Searched refs:Rd (Results 1 – 25 of 94) sorted by relevance

1234

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrThumb2.td438 bits<4> Rd;
441 let Inst{11-8} = Rd;
451 bits<4> Rd;
455 let Inst{11-8} = Rd;
477 bits<4> Rd;
480 let Inst{11-8} = Rd;
490 bits<4> Rd;
493 let Inst{11-8} = Rd;
516 bits<4> Rd;
519 let Inst{11-8} = Rd;
[all …]
DARMInstrInfo.td1392 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1399 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
1400 iii, opc, "\t$Rd, $Rn, $imm",
1401 [(set GPR:$Rd, (opnode GPR:$Rn, mod_imm:$imm))]>,
1403 bits<4> Rd;
1408 let Inst{15-12} = Rd;
1412 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1413 iir, opc, "\t$Rd, $Rn, $Rm",
1414 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1416 bits<4> Rd;
[all …]
DARMInstrThumb.td395 // ADD <Rd>, sp, #<imm8>
889 bits<3> Rd;
891 let Inst{2-0} = Rd;
899 bits<3> Rd;
902 let Inst{2-0} = Rd;
910 bits<3> Rd;
913 let Inst{2-0} = Rd;
919 bits<3> Rd;
922 let Inst{2-0} = Rd;
955 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64PBQPRegAlloc.cpp158 bool A57ChainingConstraint::addIntraChainConstraint(PBQPRAGraph &G, unsigned Rd, in addIntraChainConstraint() argument
160 if (Rd == Ra) in addIntraChainConstraint()
165 if (Register::isPhysicalRegister(Rd) || Register::isPhysicalRegister(Ra)) { in addIntraChainConstraint()
167 << Register::isPhysicalRegister(Rd) << '\n'); in addIntraChainConstraint()
173 PBQPRAGraph::NodeId node1 = G.getMetadata().getNodeIdForVReg(Rd); in addIntraChainConstraint()
186 const LiveInterval &ld = LIs.getInterval(Rd); in addIntraChainConstraint()
242 void A57ChainingConstraint::addInterChainConstraint(PBQPRAGraph &G, unsigned Rd, in addInterChainConstraint() argument
248 if (Rd != Ra) { in addInterChainConstraint()
250 << " to " << printReg(Rd, TRI) << '\n';); in addInterChainConstraint()
252 Chains.insert(Rd); in addInterChainConstraint()
[all …]
DAArch64InstrFormats.td1701 def : InstAlias<asm # "\t$Rd, $imm, $target",
1702 (!cast<Instruction>(NAME#"W") GPR32as64:$Rd,
1747 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm, "\t$Rd, $Rn", "",
1748 [(set regtype:$Rd, (node regtype:$Rn))]>,
1750 bits<5> Rd;
1756 let Inst{4-0} = Rd;
1782 : I<(outs GPR64:$Rd), (ins GPR64sp:$Rn), asm, "\t$Rd, $Rn", "",
1785 bits<5> Rd;
1791 let Inst{4-0} = Rd;
1795 : I<(outs GPR64:$Rd), (ins), asm, "\t$Rd", "", []>, Sched<[]> {
[all …]
DAArch64PBQPRegAlloc.h32 bool addIntraChainConstraint(PBQPRAGraph &G, unsigned Rd, unsigned Ra);
35 void addInterChainConstraint(PBQPRAGraph &G, unsigned Rd, unsigned Ra);
DAArch64InstrInfo.td685 def SPACE : Pseudo<(outs GPR64:$Rd), (ins i32imm:$size, GPR64:$Rn),
686 [(set GPR64:$Rd, (int_aarch64_space imm:$size, GPR64:$Rn))]>,
920 [(set GPR32:$Rd,
1040 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movw_symbol_g3:$sym, 48)>;
1041 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movw_symbol_g2:$sym, 32)>;
1042 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movw_symbol_g1:$sym, 16)>;
1043 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movw_symbol_g0:$sym, 0)>;
1045 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movw_symbol_g3:$sym, 48)>;
1046 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movw_symbol_g2:$sym, 32)>;
1047 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movw_symbol_g1:$sym, 16)>;
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonRegisterInfo.td36 // Rd - 64-bit registers.
37 class Rd<bits<5> num, string n, list<Register> subregs,
98 def D0 : Rd< 0, "r1:0", [R0, R1]>, DwarfRegNum<[32]>;
99 def D1 : Rd< 2, "r3:2", [R2, R3]>, DwarfRegNum<[34]>;
100 def D2 : Rd< 4, "r5:4", [R4, R5]>, DwarfRegNum<[36]>;
101 def D3 : Rd< 6, "r7:6", [R6, R7]>, DwarfRegNum<[38]>;
102 def D4 : Rd< 8, "r9:8", [R8, R9]>, DwarfRegNum<[40]>;
103 def D5 : Rd<10, "r11:10", [R10, R11]>, DwarfRegNum<[42]>;
104 def D6 : Rd<12, "r13:12", [R12, R13]>, DwarfRegNum<[44]>;
105 def D7 : Rd<14, "r15:14", [R14, R15]>, DwarfRegNum<[46]>;
[all …]
DHexagonPseudo.td65 def CONST32 : CONSTLDInst<(outs IntRegs:$Rd), (ins i32imm:$v),
66 "$Rd = CONST32(#$v)", []>;
67 def CONST64 : CONSTLDInst<(outs DoubleRegs:$Rd), (ins i64imm:$v),
68 "$Rd = CONST64(#$v)", []>;
249 def PS_aligna : Pseudo<(outs IntRegs:$Rd), (ins u32_0Imm:$A), "", []>;
260 def PS_fi : Pseudo<(outs IntRegs:$Rd),
263 def PS_fia : Pseudo<(outs IntRegs:$Rd),
313 def PS_alloca: Pseudo <(outs IntRegs:$Rd),
332 def PS_pselect: InstHexagon<(outs DoubleRegs:$Rd),
497 def PS_vmulw : PseudoM<(outs DoubleRegs:$Rd),
[all …]
DHexagonConstExtenders.cpp325 Register Rd; member
395 OffsetRange getOffsetRange(Register Rd) const;
498 if (ED.Rd.Reg != 0) in operator <<()
499 OS << printReg(ED.Rd.Reg, &HRI, ED.Rd.Sub); in operator <<()
1128 OffsetRange HCE::getOffsetRange(Register Rd) const { in getOffsetRange()
1130 for (const MachineOperand &Op : MRI->use_operands(Rd.Reg)) { in getOffsetRange()
1134 if (Rd != Register(Op)) in getOffsetRange()
1136 Range.intersect(getOffsetRange(Rd, *Op.getParent())); in getOffsetRange()
1163 ED.Rd = MI.getOperand(OpNum-1); in recordExtender()
1183 ED.Rd = MI.getOperand(0); in recordExtender()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/
DLanaiInstrInfo.td277 def LO : InstRI<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, LoExt:$imm16),
278 !strconcat(AsmStr, "\t$Rs1, $imm16, $Rd"),
281 def HI : InstRI<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, HiExt:$imm16),
282 !strconcat(AsmStr, "\t$Rs1, $imm16, $Rd"),
293 def R : InstRR<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, GPR:$Rs2, pred:$DDDI),
294 !strconcat(AsmStr, "$DDDI\t$Rs1, $Rs2, $Rd"),
295 [(set GPR:$Rd, (OpNode GPR:$Rs1, GPR:$Rs2))]>;
301 [(set GPR:$Rd, (OpNode GPR:$Rs1, LoExt:$imm16))],
302 [(set GPR:$Rd, (OpNode GPR:$Rs1, HiExt:$imm16))]>;
306 def R : InstRR<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, GPR:$Rs2, pred:$DDDI),
[all …]
DLanaiInstrFormats.td34 // opcode Rd Rs1 constant (16)
37 // Rd <- Rs1 op constant
83 // A Jump is accomplished by `Rd' being `pc', and it has one shadow.
90 bits<5> Rd;
98 let Inst{27 - 23} = Rd;
112 // opcode Rd Rs1 Rs2 \ operation /
115 // `Rd <- Rs1 op Rs2' iff condition DDDI is true.
131 // instructions in *Note RI::). For the SELECT operation, Rd gets Rs1 if
145 // A Jump is accomplished by `Rd' being `pc', and it has one shadow.
150 bits<5> Rd;
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/
DAVRInstrInfo.td366 // ADD Rd, Rr
376 // ADDW Rd+1:Rd, Rr+1:Rr
380 // add Rd, Rr
381 // adc Rd+1, Rr+1
388 // ADC Rd, Rr
399 // ADCW Rd+1:Rd, Rr+1:Rr
404 // adc Rd, Rr
405 // adc Rd+1, Rr+1
413 // AIDW Rd, k
414 // Adds an immediate 6-bit value K to Rd, placing the result in Rd.
[all …]
/third_party/flutter/skia/third_party/externals/sdl/src/test/
DSDL_test_compare.c48 Uint8 Rd, Gd, Bd, Ad; in SDLTest_CompareSurfaces() local
80 SDL_GetRGBA(*(Uint32*)p_reference, referenceSurface->format, &Rd, &Gd, &Bd, &Ad); in SDLTest_CompareSurfaces()
83 dist += (R-Rd)*(R-Rd); in SDLTest_CompareSurfaces()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
DSparcRegisterInfo.td43 // Rd - Slots in the FP register file for 64-bit floating-point values.
44 class Rd<bits<16> Enc, string n, list<Register> subregs> : SparcReg<Enc, n> {
195 def D0 : Rd< 0, "F0", [F0, F1]>, DwarfRegNum<[72]>;
196 def D1 : Rd< 2, "F2", [F2, F3]>, DwarfRegNum<[73]>;
197 def D2 : Rd< 4, "F4", [F4, F5]>, DwarfRegNum<[74]>;
198 def D3 : Rd< 6, "F6", [F6, F7]>, DwarfRegNum<[75]>;
199 def D4 : Rd< 8, "F8", [F8, F9]>, DwarfRegNum<[76]>;
200 def D5 : Rd<10, "F10", [F10, F11]>, DwarfRegNum<[77]>;
201 def D6 : Rd<12, "F12", [F12, F13]>, DwarfRegNum<[78]>;
202 def D7 : Rd<14, "F14", [F14, F15]>, DwarfRegNum<[79]>;
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenGlobalISel.inc1238 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1252 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1280 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1308 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1322 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1336 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1379 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1404 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1417 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1451 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Disassembler/
DAArch64Disassembler.cpp845 unsigned Rd = fieldFromInstruction(Insn, 0, 5); in DecodeFMOVLaneInstruction() local
850 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder); in DecodeFMOVLaneInstruction()
853 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder); in DecodeFMOVLaneInstruction()
936 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeThreeAddrSRegInstruction() local
964 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); in DecodeThreeAddrSRegInstruction()
985 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); in DecodeThreeAddrSRegInstruction()
998 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeMoveImmInstruction() local
1010 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); in DecodeMoveImmInstruction()
1015 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); in DecodeMoveImmInstruction()
1507 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeAddSubERegInstruction() local
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp2196 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeQADDInstruction() local
2204 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) in DecodeQADDInstruction()
2422 unsigned Rd = fieldFromInstruction(Insn, 8, 4); in DecodeT2MOVTWInstruction() local
2431 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) in DecodeT2MOVTWInstruction()
2433 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) in DecodeT2MOVTWInstruction()
2446 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeArmMOVTWInstruction() local
2454 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) in DecodeArmMOVTWInstruction()
2457 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) in DecodeArmMOVTWInstruction()
2473 unsigned Rd = fieldFromInstruction(Insn, 16, 4); in DecodeSMLAInstruction() local
2482 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) in DecodeSMLAInstruction()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/
DIceAssemblerARM32.cpp797 IValueT Rd, IValueT Imm12, in emitType01() argument
803 verifyRegNotPcWhenSetFlags(Rd, SetFlags, InstName); in emitType01()
806 assert(Rd < RegARM32::getNumGPRegs()); in emitType01()
811 (Rn << kRnShift) | (Rd << kRdShift) | Imm12; in emitType01()
819 IValueT Rd = encodeGPRegister(OpRd, "Rd", InstName); in emitType01() local
821 emitType01(Cond, Opcode, Rd, Rn, OpSrc1, SetFlags, RuleChecks, InstName); in emitType01()
825 IValueT Rd, IValueT Rn, const Operand *OpSrc1, in emitType01() argument
843 emitType01(Cond, kInstTypeDataRegister, Opcode, SetFlags, Rn, Rd, Src1Value, in emitType01()
849 emitType01(Cond, kInstTypeDataRegister, Opcode, SetFlags, Rn, Rd, Src1Value, in emitType01()
869 emitType01(Cond, kInstTypeDataImmediate, Opcode, SetFlags, Rn, Rd, in emitType01()
[all …]
DIceAssemblerMIPS32.cpp271 const IValueT Rd = encodeGPRegister(OpRd, "Rd", InsnName); in emitRdRtSa() local
275 Opcode |= Rd << 11; in emitRdRtSa()
284 const IValueT Rd = encodeGPRegister(OpRd, "Rd", InsnName); in emitRdRsRt() local
290 Opcode |= Rd << 11; in emitRdRsRt()
527 const IValueT Rd = encodeGPRegister(OpRd, "Rd", "clz"); in clz() local
529 Opcode |= Rd << 11; in clz()
530 Opcode |= Rd << 16; in clz()
657 const IValueT Rd = in jalr() local
659 Opcode |= Rd << 11; in jalr()
774 IValueT Rd = encodeGPRegister(OpRd, "Rd", "mfhi"); in mfhi() local
[all …]
/third_party/skia/third_party/externals/opengl-registry/extensions/NV/
DNV_blend_square.txt80 DST_COLOR (Rd, Gd, Bd, Ad)
81 ONE_MINUS_DST_COLOR (1, 1, 1, 1) - (Rd, Gd, Bd, Ad)
101 DST_COLOR (Rd, Gd, Bd, Ad) NEW
102 ONE_MINUS_DST_COLOR (1, 1, 1, 1) - (Rd, Gd, Bd, Ad) NEW
/third_party/openGLES/extensions/NV/
DNV_blend_square.txt80 DST_COLOR (Rd, Gd, Bd, Ad)
81 ONE_MINUS_DST_COLOR (1, 1, 1, 1) - (Rd, Gd, Bd, Ad)
101 DST_COLOR (Rd, Gd, Bd, Ad) NEW
102 ONE_MINUS_DST_COLOR (1, 1, 1, 1) - (Rd, Gd, Bd, Ad) NEW
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/Disassembler/
DRISCVDisassembler.cpp296 unsigned Rd = fieldFromInstruction(Insn, 7, 5); in decodeRVCInstrRdRs2() local
298 DecodeGPRRegisterClass(Inst, Rd, Address, Decoder); in decodeRVCInstrRdRs2()
306 unsigned Rd = fieldFromInstruction(Insn, 7, 5); in decodeRVCInstrRdRs1Rs2() local
308 DecodeGPRRegisterClass(Inst, Rd, Address, Decoder); in decodeRVCInstrRdRs1Rs2()
/third_party/skia/third_party/externals/opengl-registry/extensions/OES/
DOES_blend_subtract.txt103 FUNC_ADD_OES R = Rs * Sr + Rd * Dr
108 FUNC_SUBTRACT_OES R = Rs * Sr - Rd * Dr
113 FUNC_REVERSE_SUBTRACT_OES R = Rd * Dr - Rs * Sr
/third_party/skia/third_party/externals/opengl-registry/extensions/EXT/
DEXT_blend_equation_separate.txt164 FUNC_ADD Rc = Rs * Sr + Rd * Dr Ac = As * Sa + Ad * Da
168 FUNC_SUBTRACT Rc = Rs * Sr - Rd * Dr Ac = As * Sa - Ad * Da
172 FUNC_REVERSE_SUBTRACT Rc = Rd * Sr - Rs * Dr Ac = Ad * Sa - As * Da
176 MIN Rc = min(Rs, Rd) Ac = min(As, Ad)
180 MAX Rc = max(Rs, Rd) Ac = max(As, Ad)
231 LOGIC_OP Rc = Rs OP Rd Ac = As OP Ad

1234