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Searched refs:Regs (Results 1 – 25 of 66) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DCallingConvLower.h344 unsigned getFirstUnallocated(ArrayRef<MCPhysReg> Regs) const { in getFirstUnallocated() argument
345 for (unsigned i = 0; i < Regs.size(); ++i) in getFirstUnallocated()
346 if (!isAllocated(Regs[i])) in getFirstUnallocated()
348 return Regs.size(); in getFirstUnallocated()
371 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs) { in AllocateReg() argument
372 unsigned FirstUnalloc = getFirstUnallocated(Regs); in AllocateReg()
373 if (FirstUnalloc == Regs.size()) in AllocateReg()
377 unsigned Reg = Regs[FirstUnalloc]; in AllocateReg()
385 unsigned AllocateRegBlock(ArrayRef<MCPhysReg> Regs, unsigned RegsRequired) { in AllocateRegBlock() argument
386 if (RegsRequired > Regs.size()) in AllocateRegBlock()
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DRegisterPressure.h275 RegSet Regs; variable
297 RegSet::const_iterator I = Regs.find(SparseIndex); in contains()
298 if (I == Regs.end()) in contains()
307 auto InsertRes = Regs.insert(IndexMaskPair(SparseIndex, Pair.LaneMask)); in insert()
320 RegSet::iterator I = Regs.find(SparseIndex); in erase()
321 if (I == Regs.end()) in erase()
329 return Regs.size(); in size()
334 for (const IndexMaskPair &P : Regs) { in appendTo()
411 void addLiveRegs(ArrayRef<RegisterMaskPair> Regs);
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/Disassembler/
DSystemZDisassembler.cpp83 const unsigned *Regs, unsigned Size) { in decodeRegisterClass() argument
85 RegNo = Regs[RegNo]; in decodeRegisterClass()
292 const unsigned *Regs) { in decodeBDAddr12Operand() argument
296 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr12Operand()
302 const unsigned *Regs) { in decodeBDAddr20Operand() argument
306 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr20Operand()
312 const unsigned *Regs) { in decodeBDXAddr12Operand() argument
317 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDXAddr12Operand()
319 Inst.addOperand(MCOperand::createReg(Index == 0 ? 0 : Regs[Index])); in decodeBDXAddr12Operand()
324 const unsigned *Regs) { in decodeBDXAddr20Operand() argument
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/
DCallLowering.h47 SmallVector<Register, 4> Regs; member
56 ArgInfo(ArrayRef<Register> Regs, Type *Ty,
59 : Regs(Regs.begin(), Regs.end()), Ty(Ty),
61 if (!Regs.empty() && Flags.empty())
64 assert((Ty->isVoidTy() == (Regs.empty() || Regs[0] == 0)) &&
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86CallLowering.cpp64 assert(OrigArg.Regs.size() == 1 && "Can't handle multple regs yet"); in splitToValueTypes()
74 SplitArgs.emplace_back(OrigArg.Regs[0], VT.getTypeForEVT(Context), in splitToValueTypes()
89 SplitRegs.push_back(Info.Regs[0]); in splitToValueTypes()
212 [&](ArrayRef<Register> Regs) { in lowerReturn() argument
213 MIRBuilder.buildUnmerge(Regs, VRegs[i]); in lowerReturn()
357 [&](ArrayRef<Register> Regs) { in lowerFormalArguments() argument
358 MIRBuilder.buildMerge(VRegs[Idx][0], Regs); in lowerFormalArguments()
414 if (OrigArg.Regs.size() > 1) in lowerCall()
418 [&](ArrayRef<Register> Regs) { in lowerCall() argument
419 MIRBuilder.buildUnmerge(Regs, OrigArg.Regs[0]); in lowerCall()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
DCallLowering.cpp228 Args[i].OrigRegs.push_back(Args[i].Regs[0]); in handleAssignments()
229 Args[i].Regs.clear(); in handleAssignments()
246 Args[i].Regs.push_back(Reg); in handleAssignments()
262 Register LargeReg = Args[i].Regs[0]; in handleAssignments()
268 Args[i].Regs.clear(); in handleAssignments()
279 Args[i].Regs.push_back(Unmerge.getReg(PartIdx)); in handleAssignments()
301 Register ArgReg = Args[i].Regs[0]; in handleAssignments()
309 unsigned NumArgRegs = Args[i].Regs.size(); in handleAssignments()
318 Handler.assignValueToReg(Args[i].Regs[Part], VA.getLocReg(), VA); in handleAssignments()
323 MIRBuilder.buildMerge(Args[i].OrigRegs[0], Args[i].Regs); in handleAssignments()
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DIRTranslator.cpp164 auto *Regs = VMap.getVRegs(Val); in allocateVRegs() local
170 Regs->push_back(0); in allocateVRegs()
171 return *Regs; in allocateVRegs()
870 ArrayRef<Register> Regs = getOrCreateVRegs(LI); in translateLoad() local
878 assert(Regs.size() == 1 && "swifterror should be single pointer"); in translateLoad()
881 MIRBuilder.buildCopy(Regs[0], VReg); in translateLoad()
886 Regs.size() == 1 ? LI.getMetadata(LLVMContext::MD_range) : nullptr; in translateLoad()
887 for (unsigned i = 0; i < Regs.size(); ++i) { in translateLoad()
896 Ptr, Flags, (MRI->getType(Regs[i]).getSizeInBits() + 7) / 8, in translateLoad()
899 MIRBuilder.buildLoad(Regs[i], Addr, *MMO); in translateLoad()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/
DARMUnwindOpAsm.cpp107 for (uint32_t Regs : {VFPRegSave & 0xffff0000u, VFPRegSave & 0x0000ffffu}) { in EmitVFPRegSave()
108 while (Regs) { in EmitVFPRegSave()
110 auto RangeMSB = 32 - countLeadingZeros(Regs); in EmitVFPRegSave()
111 auto RangeLen = countLeadingOnes(Regs << (32 - RangeMSB)); in EmitVFPRegSave()
121 Regs &= ~(-1u << RangeLSB); in EmitVFPRegSave()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MCA/
DHWEventListener.h74 HWInstructionDispatchedEvent(const InstRef &IR, ArrayRef<unsigned> Regs, in HWInstructionDispatchedEvent() argument
77 UsedPhysRegs(Regs), MicroOpcodes(UOps) {} in HWInstructionDispatchedEvent()
95 HWInstructionRetiredEvent(const InstRef &IR, ArrayRef<unsigned> Regs) in HWInstructionRetiredEvent() argument
97 FreedPhysRegs(Regs) {} in HWInstructionRetiredEvent()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPUCallLowering.cpp166 assert(OrigArg.Regs.size() == SplitVTs.size()); in splitToValueTypes()
178 SplitArgs.emplace_back(OrigArg.Regs[SplitIdx], Ty, in splitToValueTypes()
281 [&](ArrayRef<Register> Regs, LLT LLTy, LLT PartLLT, int VTSplitIdx) { in lowerReturnVal() argument
282 unpackRegsToOrigType(B, Regs, VRegs[VTSplitIdx], LLTy, PartLLT); in lowerReturnVal()
491 ArrayRef<Register> Regs, in packSplitRegsToOrigType() argument
495 B.buildMerge(OrigRegs[0], Regs); in packSplitRegsToOrigType()
505 B.buildConcatVectors(OrigRegs[0], Regs); in packSplitRegsToOrigType()
512 auto RoundedConcat = B.buildConcatVectors(RoundedDestTy, Regs); in packSplitRegsToOrigType()
535 for (Register Reg : Regs) in packSplitRegsToOrigType()
539 B.buildBuildVector(OrigRegs[0], Regs); in packSplitRegsToOrigType()
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DSIMachineFunctionInfo.cpp344 auto Regs = RC.getRegisters(); in allocateVGPRSpillToAGPR() local
367 SmallVectorImpl<MCPhysReg>::const_iterator NextSpillReg = Regs.begin(); in allocateVGPRSpillToAGPR()
370 NextSpillReg, Regs.end(), [&MRI, &OtherUsedRegs](MCPhysReg Reg) { in allocateVGPRSpillToAGPR()
375 if (NextSpillReg == Regs.end()) { // Registers exhausted in allocateVGPRSpillToAGPR()
DSILoadStoreOptimizer.cpp520 const unsigned Regs = getRegs(I->getOpcode(), TII); in setMI() local
522 if (Regs & ADDR) { in setMI()
526 if (Regs & SBASE) { in setMI()
530 if (Regs & SRSRC) { in setMI()
534 if (Regs & SOFFSET) { in setMI()
538 if (Regs & VADDR) { in setMI()
542 if (Regs & SSAMP) { in setMI()
1236 const unsigned Regs = getRegs(Opcode, *TII); in mergeBufferLoadPair() local
1238 if (Regs & VADDR) in mergeBufferLoadPair()
1298 const unsigned Regs = getRegs(Opcode, *TII); in mergeTBufferLoadPair() local
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/Utils/
DAMDGPUPALMetadata.cpp161 auto Regs = getRegisters(); in getRegister() local
162 auto It = Regs.find(MsgPackDoc.getNode(Reg)); in getRegister()
163 if (It == Regs.end()) in getRegister()
555 auto Regs = getRegisters(); in toString() local
556 for (auto I = Regs.begin(), E = Regs.end(); I != E; ++I) { in toString()
557 if (I != Regs.begin()) in toString()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/AsmParser/
DSystemZAsmParser.cpp410 bool parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs,
414 RegisterGroup Group, const unsigned *Regs,
427 MemoryKind MemKind, const unsigned *Regs,
742 const unsigned *Regs, bool IsAddress) { in parseRegister() argument
747 if (Regs && Regs[Reg.Num] == 0) in parseRegister()
751 if (Regs) in parseRegister()
752 Reg.Num = Regs[Reg.Num]; in parseRegister()
759 const unsigned *Regs, RegisterKind Kind) { in parseRegister() argument
765 if (parseRegister(Reg, Group, Regs, IsAddress)) in parseRegister()
897 const unsigned *Regs, RegisterKind RegKind) { in parseAddress() argument
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DAggressiveAntiDepBreaker.cpp85 std::vector<unsigned> &Regs, in GetGroupRegs() argument
90 Regs.push_back(Reg); in GetGroupRegs()
562 std::vector<unsigned> Regs; in FindSuitableFreeRegisters() local
563 State->GetGroupRegs(AntiDepGroupIndex, Regs, &RegRefs); in FindSuitableFreeRegisters()
564 assert(!Regs.empty() && "Empty register group!"); in FindSuitableFreeRegisters()
565 if (Regs.empty()) in FindSuitableFreeRegisters()
575 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { in FindSuitableFreeRegisters()
576 unsigned Reg = Regs[i]; in FindSuitableFreeRegisters()
598 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { in FindSuitableFreeRegisters()
599 unsigned Reg = Regs[i]; in FindSuitableFreeRegisters()
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DExecutionDomainFix.cpp329 SmallVector<int, 4> Regs; in visitSoftInstr() local
341 auto I = partition_point(Regs, [&](int I) { in visitSoftInstr()
344 Regs.insert(I, rx); in visitSoftInstr()
350 while (!Regs.empty()) { in visitSoftInstr()
352 dv = LiveRegs[Regs.pop_back_val()]; in visitSoftInstr()
359 DomainValue *Latest = LiveRegs[Regs.pop_back_val()]; in visitSoftInstr()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DRDFRegisters.cpp324 auto AliasedRegs = [this] (uint32_t Unit, BitVector &Regs) { in makeRegRef() argument
327 Regs.set(*S); in makeRegRef()
334 BitVector Regs(PRI.getTRI().getNumRegs()); in makeRegRef() local
335 AliasedRegs(U, Regs); in makeRegRef()
343 Regs &= AR; in makeRegRef()
351 int F = Regs.find_first(); in makeRegRef()
DHexagonGenInsert.cpp999 RegisterSet Regs[2]; in findRemovableRegisters() local
1002 Regs[S].insert(VR); in findRemovableRegisters()
1004 while (!Regs[S].empty()) { in findRemovableRegisters()
1007 Regs[OtherS].clear(); in findRemovableRegisters()
1008 for (unsigned R = Regs[S].find_first(); R; R = Regs[S].find_next(R)) { in findRemovableRegisters()
1009 Regs[S].remove(R); in findRemovableRegisters()
1032 getInstrUses(DefI, Regs[OtherS]); in findRemovableRegisters()
1481 SmallVector<unsigned,2> Regs; in removeDeadCode() local
1490 Regs.push_back(R); in removeDeadCode()
1496 for (unsigned I = 0, N = Regs.size(); I != N; ++I) in removeDeadCode()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMCallLowering.cpp142 assert(Arg.Regs.size() == 1 && "Can't handle multple regs yet"); in assignCustomValue()
160 MIRBuilder.buildUnmerge(NewRegs, Arg.Regs[0]); in assignCustomValue()
200 assert(OrigArg.Regs.size() == SplitVTs.size() && "Regs / types mismatch"); in splitToValueTypes()
207 SplitArgs.emplace_back(OrigArg.Regs[0], SplitVTs[0].getTypeForEVT(Ctx), in splitToValueTypes()
230 Register PartReg = OrigArg.Regs[i]; in splitToValueTypes()
366 assert(Arg.Regs.size() == 1 && "Can't handle multple regs yet"); in assignCustomValue()
392 MIRBuilder.buildMerge(Arg.Regs[0], NewRegs); in assignCustomValue()
DARMFrameLowering.cpp986 SmallVector<RegAndKill, 4> Regs; in emitPushInst() local
1013 Regs.push_back(std::make_pair(Reg, /*isKill=*/!isLiveIn)); in emitPushInst()
1016 if (Regs.empty()) in emitPushInst()
1019 llvm::sort(Regs, [&](const RegAndKill &LHS, const RegAndKill &RHS) { in emitPushInst()
1023 if (Regs.size() > 1 || StrOpc== 0) { in emitPushInst()
1028 for (unsigned i = 0, e = Regs.size(); i < e; ++i) in emitPushInst()
1029 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second)); in emitPushInst()
1030 } else if (Regs.size() == 1) { in emitPushInst()
1032 .addReg(Regs[0].first, getKillRegState(Regs[0].second)) in emitPushInst()
1038 Regs.clear(); in emitPushInst()
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DARMLoadStoreOptimizer.cpp176 ArrayRef<std::pair<unsigned, bool>> Regs,
182 ArrayRef<std::pair<unsigned, bool>> Regs,
612 static bool ContainsReg(const ArrayRef<std::pair<unsigned, bool>> &Regs, in ContainsReg() argument
614 for (const std::pair<unsigned, bool> &R : Regs) in ContainsReg()
627 ArrayRef<std::pair<unsigned, bool>> Regs, in CreateLoadStoreMulti() argument
629 unsigned NumRegs = Regs.size(); in CreateLoadStoreMulti()
643 if (isThumb1 && ContainsReg(Regs, Base)) { in CreateLoadStoreMulti()
683 NewBase = Regs[NumRegs-1].first; in CreateLoadStoreMulti()
691 for (const std::pair<unsigned, bool> &R : Regs) in CreateLoadStoreMulti()
725 (!isi32Store(Opcode) || !ContainsReg(Regs, Base)); in CreateLoadStoreMulti()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVFrameLowering.cpp388 const MCPhysReg * Regs = MF.getRegInfo().getCalleeSavedRegs(); in determineCalleeSaves() local
390 for (unsigned i = 0; Regs[i]; ++i) in determineCalleeSaves()
391 if (RISCV::FPR32RegClass.contains(Regs[i]) || in determineCalleeSaves()
392 RISCV::FPR64RegClass.contains(Regs[i])) in determineCalleeSaves()
393 SavedRegs.set(Regs[i]); in determineCalleeSaves()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/
DWebAssemblyRegisterInfo.cpp135 static const unsigned Regs[2][2] = { in getFrameRegister() local
140 return Regs[TFI->hasFP(MF)][TT.isArch64Bit()]; in getFrameRegister()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64ISelDAGToDAG.cpp1117 SDValue AArch64DAGToDAGISel::createDTuple(ArrayRef<SDValue> Regs) { in createDTuple() argument
1123 return createTuple(Regs, RegClassIDs, SubRegs); in createDTuple()
1126 SDValue AArch64DAGToDAGISel::createQTuple(ArrayRef<SDValue> Regs) { in createQTuple() argument
1132 return createTuple(Regs, RegClassIDs, SubRegs); in createQTuple()
1135 SDValue AArch64DAGToDAGISel::createTuple(ArrayRef<SDValue> Regs, in createTuple() argument
1140 if (Regs.size() == 1) in createTuple()
1141 return Regs[0]; in createTuple()
1143 assert(Regs.size() >= 2 && Regs.size() <= 4); in createTuple()
1145 SDLoc DL(Regs[0]); in createTuple()
1151 CurDAG->getTargetConstant(RegClassIDs[Regs.size() - 2], DL, MVT::i32)); in createTuple()
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DAArch64CallLowering.cpp235 SplitArgs.emplace_back(OrigArg.Regs[0], SplitVTs[0].getTypeForEVT(Ctx), in splitToValueTypes()
241 assert(OrigArg.Regs.size() == SplitVTs.size() && "Regs / types mismatch"); in splitToValueTypes()
247 SplitArgs.emplace_back(OrigArg.Regs[i], SplitTy, OrigArg.Flags[0], in splitToValueTypes()
352 if (CurVReg != CurArgInfo.Regs[0]) { in lowerReturn()
353 CurArgInfo.Regs[0] = CurVReg; in lowerReturn()
631 if (OutInfo.Regs.size() > 1) { in areCalleeOutgoingArgsTailCallable()
640 MachineInstr *RegDef = getDefIgnoringCopies(OutInfo.Regs[0], MRI); in areCalleeOutgoingArgsTailCallable()

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