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Searched refs:TIMING_CFG1_PRETOACT_SHIFT (Results 1 – 19 of 19) sorted by relevance

/third_party/uboot/u-boot-2020.01/include/configs/km/
Dkm-mpc8360.h70 (3 << TIMING_CFG1_PRETOACT_SHIFT))
Dkm-mpc832x.h73 (3 << TIMING_CFG1_PRETOACT_SHIFT))
Dkm-mpc8309.h108 (3 << TIMING_CFG1_PRETOACT_SHIFT))
/third_party/uboot/u-boot-2020.01/include/configs/
Dmpc8308_p1m.h74 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
DMPC832XEMDS.h49 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
Dve8313.h62 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
DMPC8308RDB.h70 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
Dids8313.h69 #define CONFIG_SYS_DDR_TIMING_1 ((4 << TIMING_CFG1_PRETOACT_SHIFT) |\
DMPC8323ERDB.h49 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
DMPC8313ERDB_NOR.h85 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
DMPC8313ERDB_NAND.h113 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
DMPC8315ERDB.h67 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
DMPC837XEMDS.h78 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
DMPC837XERDB.h92 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
Dhrcon.h59 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
Dstrider.h59 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
/third_party/uboot/u-boot-2020.01/board/tqc/tqm834x/
Dtqm834x.c354 (4 << TIMING_CFG1_PRETOACT_SHIFT) | in set_ddr_config()
/third_party/uboot/u-boot-2020.01/drivers/ram/
Dmpc83xx_sdram.c43 static const uint TIMING_CFG1_PRETOACT_SHIFT = (31 - 3); variable
679 timing_cfg_1 = precharge_to_activate << TIMING_CFG1_PRETOACT_SHIFT | in mpc83xx_sdram_probe()
/third_party/uboot/u-boot-2020.01/include/
Dmpc83xx.h1179 #define TIMING_CFG1_PRETOACT_SHIFT 28 macro