1 /* SPDX-License-Identifier: GPL-2.0+ */
2 #ifndef _UFS_H
3 #define _UFS_H
4 #ifndef CONFIG_UFS
5 /**
6 * ufs_probe() - initialize all devices in the UFS uclass
7 *
8 * @return 0 if Ok, -ve on error
9 */
10 int ufs_probe(void);
11
12 /**
13 * ufs_probe_dev() - initialize a particular device in the UFS uclass
14 *
15 * @index: index in the uclass sequence
16 *
17 * @return 0 if successfully probed, -ve on error
18 */
19 int ufs_probe_dev(int index);
20
21 /*
22 * ufs_scsi_bind() - Create a new scsi device as a child of the UFS device and
23 * bind it to the ufs_scsi driver
24 * @ufs_dev: UFS device
25 * @scsi_devp: Pointer to scsi device
26 *
27 * @return 0 if Ok, -ve on error
28 */
29 int ufs_scsi_bind(struct udevice *ufs_dev, struct udevice **scsi_devp);
30 #else
31
32 #include <common.h>
33 #include <asm/io.h>
34
35 #define MAX_DEVICE 1
36 #define find_device_index() (0)
37 #define get_local_dwc_host() \
38 struct dwc_ufs_hba *dwc_host = &g_dwc_host[find_device_index()];
39
40 #define UFS_OK 0
41 #define UFS_ERR (-1)
42
43 #define bytes_align_128(x) ((x + 128 - 1) & ~(128 - 1))
44 #define bytes_align_1024(x) ((x + 1024 - 1) & ~(1024 - 1))
45
46 /* UFSHCD Registers Offsets */
47 #define UFS_CAP_OFF 0x00
48 #define UFS_VER_OFF 0x08
49 #define UFS_HCPID_OFF 0x10
50 #define UFS_HCMID_OFF 0x14
51 #define UFS_AHIT_OFF 0x18
52 #define UFS_IS_OFF 0x20
53 #define UFS_IE_OFF 0x24
54 #define UFS_HCS_OFF 0x30
55 #define UFS_HCE_OFF 0x34
56 #define UFS_UECPA_OFF 0x38
57 #define UFS_UECDL_OFF 0x3C
58 #define UFS_UECN_OFF 0x40
59 #define UFS_UECT_OFF 0x44
60 #define UFS_UECDME_OFF 0x48
61 #define UFS_UTRIACR_OFF 0x4C
62 #define UFS_UTRLBA_OFF 0x50
63 #define UFS_UTRLBAU_OFF 0x54
64 #define UFS_UTRLDBR_OFF 0x58
65 #define UFS_UTRLCLR_OFF 0x5C
66 #define UFS_UTRLRSR_OFF 0x60
67 #define UFS_UTMRLBA_OFF 0x70
68 #define UFS_UTMRLBAU_OFF 0x74
69 #define UFS_UTMRLDBR_OFF 0x78
70 #define UFS_UTMRLCLR_OFF 0x7C
71 #define UFS_UTMRLRSR_OFF 0x80
72 #define UFS_UICCMD_OFF 0x90
73 #define UFS_UICCMDARG1_OFF 0x94
74 #define UFS_UICCMDARG2_OFF 0x98
75 #define UFS_UICCMDARG3_OFF 0x9C
76 #define UFS_BUSTHRTL_OFF 0xC0
77 #define UFS_OOCPR_OFF 0xC4
78 #define UFS_FEIE_OFF 0xC8
79 #define UFS_CDACFG_OFF 0xD0
80 #define UFS_CDATX1_OFF 0xD4
81 #define UFS_CDATX2_OFF 0xD8
82 #define UFS_CDARX1_OFF 0xDC
83 #define UFS_CDARX2_OFF 0xE0
84 #define UFS_CDASTA_OFF 0xE4
85 #define UFS_LBMCFG_OFF 0xF0
86 #define UFS_LBMSTA_OFF 0xF4
87 #define UFS_DBG_OFF 0xF8
88 #define UFS_HCLKDIV_OFF 0xFC
89
90 /* Controller capability masks and shift value */
91 #define DWC_UFS_NUTRS_MASK 0x0000001f
92 #define DWC_UFS_NUTMRS_MASK 0x00070000
93 #define DWC_UFS_NUTMRS_SHIFT 16
94 #define DWC_UFS_AUTOH8 0x00800000
95 #define DWC_UFS_AUTOH8_SHIFT 23
96
97 /* GenSelectorIndex */
98 #define MTX_L0 0x0000
99 #define MTX_L1 0x0001
100 #define MRX_L0 0x0004
101 #define MRX_L1 0x0005
102
103 #define ATTR_M_SHIFT 16
104 #define attr_mtx0(x) ((x << ATTR_M_SHIFT) | MTX_L0)
105 #define attr_mtx1(x) ((x << ATTR_M_SHIFT) | MTX_L1)
106 #define attr_mrx0(x) ((x << ATTR_M_SHIFT) | MRX_L0)
107 #define attr_mrx1(x) ((x << ATTR_M_SHIFT) | MRX_L1)
108 #define attr_mcb(x) ((u32)((u16)(x) << ATTR_M_SHIFT))
109
110 /*
111 * Register Fields
112 */
113 #define UFS_AUTO_HIBERNATE_BIT BIT(23)
114 #define UFS_CAPS_64AS_BIT BIT(24)
115 #define UFS_HCE_RESET_BIT BIT(0)
116 #define UFS_HCS_DP_BIT BIT(0)
117 #define UFS_HCS_UCRDY_BIT BIT(3)
118 #define UFS_HCS_UPMCRS_OFF (8)
119 #define UFS_HCS_UPMCRS_MASK (0x3 << UFS_HCS_UPMCRS_OFF)
120 #define UFS_IS_UE_BIT BIT(2)
121 #define UFS_IS_UPMS_BIT BIT(4)
122 #define UFS_IS_UHXS_BIT BIT(5)
123 #define UFS_IS_UHES_BIT BIT(6)
124 #define UFS_IS_ULSS_BIT BIT(8)
125 #define UFS_IS_UCCS_BIT BIT(10)
126 #define UFS_UTP_RUN_BIT BIT(0)
127 #define UFS_LBMCFG_DEFAULT_VALUE 0xb01
128 #define UFS_HCLKDIV_NORMAL_VALUE 0xFA
129 #define UFS_HCLKDIV_SLOW_VALUE 0x14
130 #define UFS_HCLKDIV_FPGA_VALUE 0x12
131
132 #define UFS_AHIT_AH8ITV_MASK (0x3FF)
133 #define UFS_AHIT_AUTOH8_TIMER (0x1001)
134
135 #define UIC_LINK_STARTUP_CMD 0x16
136 #define NOP_TRANS_TYPE 0x20
137 #define BAD_SLOT 0x55
138 #define NOP_TRANS_TYPE 0x20
139 #define PRDT_BUFFER_SIZE 0x40000
140 #define UNIT_DESCS_COUNT 8
141 #define CAPACITY_DATA_LENGTH 8
142 #define SENSE_DATA_LENGTH 20
143 #define SENSE_KEY_INDEX 36
144 #define RPMB_DATA_SIZE 256
145 #define RPMB_FRAME_SIZE 512
146 #define LOGICAL_BLK_SIZE 4096
147 #define UFS_DWORD_SHIFT 2
148
149 #define QUERY_DESC_MANUFACTURER_NAME_MAX_SIZE 0x12
150 #define QUERY_DESC_PRODUCT_NAME_MAX_SIZE 0x22
151 #define QUERY_DESC_STRING_MAX_SIZE 0xFE
152
153 #ifdef UFS_DEBUG
154 #define ufs_pr_dbg(fmt, s...) printf(fmt, ##s)
155 #define ufs_pr_mem(fmt, s...) printf(fmt, ##s)
156 #define ufs_pr_reg(fmt, s...) printf(fmt, ##s)
157 #define ufs_pos() printf("pos -- %s: %d\n", __func__, __LINE__)
158 #else
159 #define ufs_pr_dbg(s...)
160 #define ufs_pr_mem(s...)
161 #define ufs_pr_reg(s...)
162 #define ufs_pos()
163 #endif
164
165 /* Data structure sizes in bytes */
166 enum {
167 DWC_UFS_BASIC_UPIU_SIZE = 32,
168 DWC_UFS_UTRD_SIZE = 32,
169 DWC_UFS_TSF_SIZE = 16,
170 DWC_UFS_PRD_SIZE = 16,
171
172 DWC_UFSHCD_MAX_PRD_SIZE = 8, /* 128 (Linux) */
173
174 DWC_MAX_QUERY_DATA = 256,
175 DWC_UFS_CDB_SIZE = 16,
176 DWC_UFS_SENSE_DATA_SIZE = 18,
177
178 DWC_UFS_UTMRD_HDR_SIZE = 16,
179 };
180
181 /* Alignment Requirement in bytes */
182 enum {
183 DWC_UTRL_BASE_ALIGN = 1024,
184 DWC_UCD_ALIGN = 512,
185 DWC_CMD_BASE_ALIGN = 128,
186 };
187
188 /* Rate */
189 enum UFS_RATE {
190 UFS_RATE_A = 1,
191 UFS_RATE_B = 2
192 };
193
194 /* Power mode */
195 enum POWER_MODE {
196 FAST_MODE = 0x11,
197 SLOW_MODE = 0x22,
198 FASTAUTO_MODE = 0x44,
199 SLOWAUTO_MODE = 0x55,
200 INVALID_MODE = 0xFF
201 };
202
203 enum ufs_pwm_gear_tag {
204 UFS_PWM_DONT_CHANGE,
205 UFS_PWM_G1,
206 UFS_PWM_G2,
207 UFS_PWM_G3,
208 UFS_PWM_G4,
209 UFS_PWM_G5,
210 UFS_PWM_G6,
211 UFS_PWM_G7,
212 };
213
214 enum ufs_hs_gear_tag {
215 UFS_HS_DONT_CHANGE,
216 UFS_HS_G1,
217 UFS_HS_G2,
218 UFS_HS_G3,
219 };
220
221 struct pwr_mode_params {
222 uint8_t tx_gear;
223 uint8_t rx_gear;
224 uint8_t hs_series;
225 uint8_t tx_lanes;
226 uint8_t rx_lanes;
227 uint8_t pwr_mode;
228 };
229
230 #define WELL_BOOT_LU_A 0x01
231 #define WELL_BOOT_LU_B 0x02
232
233 #define DEFAULT_BOOT_LUN WELL_BOOT_LU_A
234 #define DEFAULT_ACTIVE_LUN 3
235
236 #define DEFAULT_MODE FAST_MODE
237 #define DEFAULT_GEAR UFS_HS_G3
238 #define DEFAULT_RATE UFS_RATE_B
239 #define DEFAULT_LANE 2
240
241 #pragma pack(push)
242 #pragma pack(1)
243
244 /*
245 * Command UPIU Structure
246 */
247 struct dwc_ufs_cmd_upiu {
248 uint8_t trans_type;
249 uint8_t flags;
250 uint8_t lun;
251 uint8_t task_tag;
252 uint8_t cmd_set_type;
253 uint8_t reserved_1_0;
254 uint8_t reserved_1_1;
255 uint8_t reserved_1_2;
256 uint8_t tot_ehs_len;
257 uint8_t reserved_2;
258 uint16_t data_seg_len;
259 uint32_t exp_data_xfer_len;
260 uint8_t cdb[16]; /* 16 cdb size */
261 };
262
263 /*
264 * Query UPIU Structure
265 */
266 struct dwc_ufs_query_upiu {
267 uint8_t trans_type;
268 uint8_t flags;
269 uint8_t reserved_1;
270 uint8_t task_tag;
271 uint8_t reserved_2;
272 uint8_t query_func;
273 uint8_t query_resp;
274 uint8_t reserved_3;
275 uint8_t tot_ehs_len;
276 uint8_t reserved_4;
277 uint16_t data_seg_len;
278 uint8_t tsf[16]; /* 16 tsf size */
279 uint32_t reserved_5;
280 };
281
282 /*
283 * NOP OUT UPIU Structure
284 */
285 struct dwc_ufs_nop_req_upiu {
286 uint8_t trans_type;
287 uint8_t flags;
288 uint8_t reserved_1;
289 uint8_t task_tag;
290 uint32_t reserved_2;
291 uint8_t tot_ehs_len;
292 uint8_t reserved_3;
293 uint16_t data_seg_len;
294 uint8_t reserved_4[20]; /* 20 reserved */
295 };
296
297 /*
298 * NOP IN UPIU Structure
299 */
300 struct dwc_ufs_nop_resp_upiu {
301 uint8_t trans_type;
302 uint8_t flags;
303 uint8_t reserved_1;
304 uint8_t task_tag;
305 uint8_t reserved_2_0;
306 uint8_t reserved_2_1;
307 uint8_t response;
308 uint8_t reserved_3;
309 uint8_t tot_ehs_len;
310 uint8_t device_info;
311 uint16_t data_seg_len;
312 uint8_t reserved_4[20]; /* 20 reserved */
313 };
314
315 /*
316 * Transfer Response UPIU Structure
317 */
318 struct dwc_ufs_resp_upiu {
319 uint8_t trans_type;
320 uint8_t flags;
321 uint8_t lun;
322 uint8_t task_tag;
323 uint8_t cmd_set_type;
324 uint8_t reserved_1;
325 uint8_t response;
326 uint8_t status;
327 uint8_t tot_ehs_len;
328 uint8_t device_info;
329 uint16_t data_seg_len;
330 uint32_t residual_xfer_count;
331 uint32_t reserved_2;
332 uint32_t reserved_3;
333 uint32_t reserved_4;
334 uint32_t reserved_5;
335 uint16_t sense_data_len;
336 uint8_t sense_data[18]; /* 18 sense size */
337 };
338
339 struct dwc_ufs_prd {
340 uint32_t base_addr;
341 uint32_t upper_addr;
342 uint32_t reserved1;
343 uint32_t size;
344 };
345
346 /**
347 * dwc_ufs_ucd
348 * UTP Command Descriptor (UCD) structure.
349 * Every UTRD contains a pointer for this data structure
350 * This structure logically consists of 3 parts
351 * 1. "Transfer Request" or "Command UPIU" (SCSI, Native UFS & DM)
352 * 2. "Transfer Response" or "Response UPIU"
353 * 3. "Physical Region Description Table"(PRDT).
354 * The data structure should support 32 bit or 64 bit memory buffer address
355 * space.
356 * "Transfer Request" and "Transfer Response" are in BIG ENDIAN Format
357 * "PRDT" is in LITTLE ENDIAN Format
358 */
359 struct dwc_ufs_ucd {
360 uint8_t cmd_upiu[DWC_UCD_ALIGN];
361 uint8_t resp_upiu[DWC_UCD_ALIGN];
362 struct dwc_ufs_prd prdt[DWC_UFSHCD_MAX_PRD_SIZE];
363 };
364
365 struct dwc_ufs_utrd {
366 uint8_t reserved_1_0:8;
367 uint8_t reserved_1_1:8;
368 uint8_t reserved_1_2:8;
369 uint8_t ct_and_flags:8;
370 uint32_t reserved_2:32;
371 uint8_t ocs:8;
372 uint8_t reserved_3_0:8;
373 uint8_t reserved_3_1:8;
374 uint8_t reserved_3_2:8;
375 uint32_t reserved_4:32;
376
377 /* Only bits 31:7 are valid; 128B Aligned addr */
378 uint32_t ucdba:32;
379 uint32_t ucdbau:32;
380 uint16_t resp_upiu_length:16;
381 uint16_t resp_upiu_offset:16;
382
383 uint16_t prdt_length:16;
384 uint16_t prdt_offset:16;
385 };
386
387 /**
388 * dwc_ufs_tm_req_upiu
389 * Task Management Request UPIU structure
390 * Size of this structure is 32 bytes
391 * The data structure should support 32 bit or 64 bit memory buffer address
392 * space. This structure is in BIG ENDINA Format
393 */
394 struct dwc_ufs_tm_req_upiu { /* BIG ENDIAN */
395 uint8_t trans_type;
396 uint8_t flags;
397 uint8_t lun;
398 uint8_t task_tag;
399 uint8_t reserved_1;
400 uint8_t tm_fn;
401 uint8_t reserved_2_0;
402 uint8_t reserved_2_1;
403 uint8_t tot_ehs_len;
404 uint8_t reserved_3;
405 uint16_t data_seg_len;
406 uint32_t input_param_1;
407 uint32_t input_param_2;
408 uint32_t input_param_3;
409 uint32_t reserved_4;
410 uint32_t reserved_5;
411 };
412
413 /**
414 * dwc_ufs_tm_resp_upiu
415 * Task Management Response UPIU structure
416 * Size of this structure is 32 bytes
417 * The data structure should support 32 bit or 64 bit memory buffer address
418 * space. This structure is in BIG ENDINA Format
419 */
420 struct dwc_ufs_tm_resp_upiu { /* BIG ENDIAN */
421 uint8_t trans_type;
422 uint8_t flags;
423 uint8_t lun;
424 uint8_t task_tag;
425 uint8_t reserved_1_0;
426 uint8_t reserved_1_1;
427 uint8_t response;
428 uint8_t reserved_2;
429 uint8_t tot_ehs_len;
430 uint8_t reserved_3;
431 uint16_t data_seg_len;
432 uint32_t output_param_1;
433 uint32_t output_param_2;
434 uint32_t reserved_4;
435 uint32_t reserved_5;
436 uint32_t reserved_6;
437 };
438
439 struct dwc_ufs_utmrd {
440 uint8_t reserved_1_0:8;
441 uint8_t reserved_1_1:8;
442 uint8_t reserved_1_2:8;
443 uint8_t intr_flag:8;
444 uint32_t reserved_2:32;
445 uint8_t ocs:8;
446 uint8_t reserved_3_0:8;
447 uint8_t reserved_3_1:8;
448 uint8_t reserved_3_2:8;
449 uint32_t reserved_4:32;
450
451 struct dwc_ufs_tm_req_upiu tm_req_upiu;
452 struct dwc_ufs_tm_resp_upiu tm_resp_upiu;
453 };
454
455 struct query_param {
456 uint8_t opcode;
457 uint8_t idn;
458 uint8_t index;
459 uint8_t selector;
460 };
461
462 struct cmd_param {
463 uint64_t addr;
464 uint64_t src;
465 uint32_t size;
466 };
467
468 #pragma pack(pop)
469
470 struct partition_desc {
471 uint8_t boot_lun_id;
472 uint8_t write_protect;
473 uint8_t memory_type;
474 uint8_t data_reliability;
475 uint8_t block_size;
476 uint8_t prov_type;
477 uint16_t context_capabilities;
478 uint32_t lu_capacity;
479 #define UFS_MAX_LU_CAP 0xFFFFFFFF
480 uint32_t num_alloc_units;
481 };
482
483 struct configuration_header {
484 uint8_t b_boot_enable;
485 uint8_t b_descr_access_en;
486 uint8_t b_init_power_mode;
487 uint8_t b_high_priority_lun;
488 uint8_t b_secure_removal_type;
489 uint8_t b_init_active_icc_level;
490 uint16_t w_periodic_rtc_update;
491 };
492
493 struct partition_desc_table {
494 uint8_t b_number_lu;
495 uint8_t b_allocation_unit_size;
496 uint32_t d_segment_size;
497 uint64_t q_total_raw_device_capacity;
498 uint8_t b_data_ordering;
499 uint8_t b_max_contex_id_number;
500 uint16_t w_supported_memory_types;
501 uint32_t d_system_code_max_alloc_u;
502 uint16_t w_system_code_cap_adj_fac;
503 uint32_t d_non_persist_max_alloc_u;
504 uint16_t w_non_persist_cap_adj_fac;
505 uint32_t d_enhanced1_max_alloc_u;
506 uint16_t w_enhanced1_cap_adj_fac;
507 uint32_t d_enhanced2_max_alloc_u;
508 uint16_t w_enhanced2_cap_adj_fac;
509 struct configuration_header *p_conf_header;
510 struct partition_desc *partition_desc_ptr[UNIT_DESCS_COUNT];
511 };
512
513 struct desc_params {
514 void *req_upiu;
515 struct configuration_header *conf_head;
516 struct partition_desc **part_desc;
517 uint8_t opcode;
518 uint8_t desc_idn;
519 uint8_t desc_index;
520 uint16_t length;
521 };
522
523 /* UFS: Device descriptor */
524 struct ufs_device_descriptor {
525 uint8_t b_length;
526 uint8_t b_descriptor_idn;
527 uint8_t b_device;
528 uint8_t b_device_class;
529 uint8_t b_device_sub_class;
530 uint8_t b_protocol;
531 uint8_t b_number_lu;
532 uint8_t b_number_wlu;
533 uint8_t b_boot_enable;
534 uint8_t b_descr_access_en;
535 uint8_t b_init_power_mode;
536 uint8_t b_high_priority_lun;
537 uint8_t b_secure_removal_type;
538 uint8_t b_security_lu;
539 uint8_t b_background_ops_term_lat;
540 uint8_t b_init_active_icc_level;
541 uint16_t w_spec_version;
542 uint16_t w_manufacture_date;
543 uint8_t i_manufacturer_name;
544 uint8_t i_product_name;
545 uint8_t i_serial_number;
546 uint8_t i_oem_id;
547 uint16_t w_manufacturer_id;
548 uint8_t b_ud_0base_offset;
549 uint8_t b_ud_config_plength;
550 uint8_t b_device_rtt_cap;
551 uint16_t w_periodic_rtc_update;
552 uint8_t b_ufs_feature_support;
553 uint8_t b_ffu_timeout;
554 uint8_t b_queue_depth;
555 uint16_t w_device_version;
556 uint8_t b_num_secure_wp_area;
557 uint32_t d_psa_max_data_size;
558 uint8_t b_psa_state_timeout;
559 uint8_t i_product_revision_level;
560 uint8_t reserved[5]; /* 5 reserved */
561 uint8_t reserved_ume[16]; /* 16 reserved */
562 } __attribute__ ((packed));
563
564 /* UFS: Geometry descriptor */
565 struct ufs_geometry_descriptor {
566 uint8_t b_length;
567 uint8_t b_descriptor_idn;
568 uint8_t b_media_technology;
569 uint8_t reserved;
570 uint64_t q_total_raw_device_capacity;
571 uint8_t b_max_number_lu;
572 uint32_t d_segment_size;
573 uint8_t b_allocation_unit_size;
574 uint8_t b_min_addr_block_size;
575 uint8_t b_optimal_read_block_size;
576 uint8_t b_optimal_write_block_size;
577 uint8_t b_max_in_buffer_size;
578 uint8_t b_max_out_buffer_size;
579 uint8_t b_rpmb_read_write_size;
580 uint8_t b_dynamic_capacity_resource_policy;
581 uint8_t b_data_ordering;
582 uint8_t b_max_contex_id_number;
583 uint8_t b_sys_data_tag_unit_size;
584 uint8_t b_sys_data_tag_res_size;
585 uint8_t b_supported_sec_rtypes;
586 uint16_t w_supported_memory_types;
587 uint32_t d_system_code_max_alloc_u;
588 uint16_t w_system_code_cap_adj_fac;
589 uint32_t d_non_persist_max_alloc_u;
590 uint16_t w_non_persist_cap_adj_fac;
591 uint32_t d_enhanced1_max_alloc_u;
592 uint16_t w_enhanced1_cap_adj_fac;
593 uint32_t d_enhanced2_max_alloc_u;
594 uint16_t w_enhanced2_cap_adj_fac;
595 uint32_t d_enhanced3_max_alloc_u;
596 uint16_t w_enhanced3_cap_adj_fac;
597 uint32_t d_enhanced4_max_alloc_u;
598 uint16_t w_enhanced4_cap_adj_fac;
599 uint32_t d_optimal_logical_block_size;
600 } __attribute__ ((packed));
601
602 /* UFS: String descriptor */
603 struct ufs_string_descriptor {
604 char manufacturer_name[QUERY_DESC_MANUFACTURER_NAME_MAX_SIZE];
605 char product_name[QUERY_DESC_PRODUCT_NAME_MAX_SIZE];
606 char serial_number[QUERY_DESC_STRING_MAX_SIZE];
607 char oem_id[QUERY_DESC_STRING_MAX_SIZE];
608 };
609
610 /* UFS: Health descriptor */
611 struct ufs_health_descriptor {
612 uint8_t b_length;
613 uint8_t b_descriptor_idn;
614 uint8_t b_pre_eol_info;
615 uint8_t b_device_life_time_est_a;
616 uint8_t b_device_life_time_est_b;
617 uint8_t reserved[32]; /* 32 reserved */
618 } __attribute__ ((packed));
619
620 /* UFS: Interconnect descriptor */
621 struct ufs_interconnect_descriptor {
622 uint8_t b_length;
623 uint8_t b_descriptor_idn;
624 uint16_t bcd_unipro_version;
625 uint16_t bcd_mphy_version;
626 } __attribute__ ((packed));
627
628 struct ufs_unit_index_descriptror {
629 uint8_t b_length;
630 uint8_t b_descriptor_idn;
631 uint8_t b_unit_index;
632 uint8_t b_lu_enable;
633 uint8_t b_boot_lun_id;
634 uint8_t b_lu_write_protect;
635 uint8_t b_lu_queue_depth;
636 uint8_t b_psa_sensitive;
637 uint8_t b_memory_type;
638 uint8_t b_data_reliability;
639 uint8_t b_logical_block_size;
640 uint64_t q_logical_block_count;
641 uint32_t d_erase_block_size;
642 uint8_t b_provisioning_type;
643 uint64_t q_phy_mem_resource_count;
644 uint16_t w_context_capabilities;
645 uint8_t b_large_unit_granularity_m1;
646 } __attribute__ ((packed));
647
648 struct ufs_unit_rpmb_descriptror {
649 uint8_t b_length;
650 uint8_t b_descriptor_idn;
651 uint8_t b_unit_index;
652 uint8_t b_lu_enable;
653 uint8_t b_boot_lun_id;
654 uint8_t b_lu_write_protect;
655 uint8_t b_lu_queue_depth;
656 uint8_t b_psa_sensitive;
657 uint8_t b_memory_type;
658 uint8_t reserved1;
659 uint8_t b_logical_block_size;
660 uint64_t q_logical_block_count;
661 uint32_t d_erase_block_size;
662 uint8_t b_provisioning_type;
663 uint64_t q_phy_mem_resource_count;
664 uint8_t reserved2[3]; /* 3 reserved */
665 } __attribute__ ((packed));
666
667 struct ufs_unit_descriptor {
668 struct ufs_unit_index_descriptror unit_index_desc[UNIT_DESCS_COUNT];
669 struct ufs_unit_rpmb_descriptror unit_rpmb_desc;
670 } __attribute__ ((packed));
671
672 struct ufs_dev_desc_configuration_param {
673 uint8_t b_length;
674 uint8_t b_descriptor_idn;
675 uint8_t b_conf_desc_continue;
676 uint8_t b_boot_enable;
677 uint8_t b_descr_access_en;
678 uint8_t b_init_power_mode;
679 uint8_t b_high_priority_lun;
680 uint8_t b_secure_removal_type;
681 uint8_t b_init_active_icc_level;
682 uint16_t w_periodic_rtc_update;
683 uint8_t reserved[5]; /* 5 reserved, 11 in ufs3.1 */
684 } __attribute__ ((packed));
685
686 struct ufs_unit_desc_configuration_param {
687 uint8_t b_lu_enable;
688 uint8_t b_boot_lun_id;
689 uint8_t b_lu_write_protect;
690 uint8_t b_memory_type;
691 uint32_t d_num_alloc_units;
692 uint8_t b_data_reliability;
693 uint8_t b_logical_block_size;
694 uint8_t b_provisioning_type;
695 uint16_t w_context_capabilities;
696 uint8_t reserved[3]; /* 3 reserved, 13 in ufs3.1 */
697 } __attribute__ ((packed));
698
699 struct ufs_configuration_descriptor {
700 struct ufs_dev_desc_configuration_param dev_desc_conf_param;
701 struct ufs_unit_desc_configuration_param unit_desc_conf_param[UNIT_DESCS_COUNT];
702 } __attribute__ ((packed));
703
704 struct ufs_descriptor {
705 uint32_t desc_is_init;
706 struct ufs_device_descriptor dev_desc;
707 struct ufs_string_descriptor str_desc;
708 struct ufs_geometry_descriptor geo_desc;
709 struct ufs_unit_descriptor unit_desc;
710 struct ufs_configuration_descriptor conf_desc;
711 struct ufs_health_descriptor heal_desc;
712 struct ufs_interconnect_descriptor intr_desc;
713 };
714
715 /**
716 * struct dwc_ufs_hcd_lrb
717 * Local Reference Block for application commands (eg:scsi)
718 * Maintained for every utrd slot
719 * @command_type: Maintained to abstract the application layer out of core
720 * @data_direction: whether command is a read/write or no-data command
721 * @ocs: ocs from utrd is read and kept here for future analysis
722 * @xfer_command_status: holds the response from response-upiu(eg: Scsi status)
723 * @transfer_size: total size of transfer in bytes
724 * @task_tag: task_tag
725 * @lun: lun
726 * @scmd: scsi command; should be null if its not a scsi command
727 * @utrd: transfer descriptor address pointer
728 * @cmd_upiu: address of command upiu
729 * @resp_upiu: address of response upiu
730 * @prdt: base address of prd table
731 * @sense_buffer_len: sense buffer length in bytes
732 * @sense_buffer: pointer to sense buffer for the command
733 */
734 struct dwc_ufs_hcd_lrb {
735 uint8_t command_type;
736 uint8_t data_direction;
737 uint8_t read_write_flags;
738 uint8_t ocs;
739 uint8_t xfer_command_status;
740
741 uint32_t transfer_size;
742 uint32_t task_tag;
743 uint32_t lun;
744
745 struct dwc_ufs_utrd *utrd;
746 struct dwc_ufs_cmd_upiu *cmd_upiu;
747 struct dwc_ufs_resp_upiu *resp_upiu;
748 struct dwc_ufs_prd *prdt;
749
750 uint16_t sense_buffer_len;
751 uint8_t *sense_buffer;
752 };
753
754 /**
755 * struct dwc_ufshcd_dm_lrb
756 * Local Reference Block for Device management commands (eg: nopout, query ..)
757 * Maintained one per driver instance
758 * @trans_type: Transaction Type (query/nopout ..)
759 * @flags:flags indicating Read/Write
760 * @lun: lun to be addressed through this command
761 * @query_fn: query_function
762 * @tot_ehs_len: total ehs length
763 * @data_seg_len: data segment length for this command
764 * @tsf: transaction specific field for this command
765 * @dm_cmd_results: Device management function result updated after
766 * post processing
767 */
768 struct dwc_ufshcd_dm_lrb {
769 uint8_t trans_type;
770 uint8_t flags;
771 uint8_t lun;
772 /* We cant fix task tag; it is dynamically set */
773 uint8_t query_fn;
774 uint8_t tot_ehs_len;
775 uint16_t data_seg_len;
776 uint8_t tsf[DWC_UFS_TSF_SIZE];
777
778 int dm_cmd_results;
779 };
780
781 /**
782 * struct dwc_ufs_hba
783 * Private structure of the host bus adapter
784 * @caps: DWC UFS HC capabilities stored here for reference
785 * @ufs_version: UFS version read adn kept here
786 * @nutrs: Transfer Request Queue depth supported by DWC UFS HC
787 * @nutmrs: Task Management Queue depth supported by DWC UFS HC
788 * @utrl_base_addr: UTP Transfer Request Descriptor List base address (virtual)
789 * @utmrl_base_addr: UTP Task Management Descriptor List base address (virtual)
790 * @ucdl_base_addr: UFS Command Descriptor List Base Address (virtual)
791 * @lrb: pointer to local reference block list
792 * @dm_lrb: local reference block device management commands
793 * @outstanding_xfer_reqs: outstanding transfer requests to be processed
794 */
795 struct dwc_ufs_hba {
796 uint32_t caps;
797 uint8_t nutrs;
798 uint8_t nutmrs;
799 uint8_t autoh8;
800
801 uint8_t active_lun;
802 uint8_t active_bootlun;
803 uint8_t lu_request_sense_sent[UNIT_DESCS_COUNT];
804 uint8_t unit_offset;
805 uint8_t unit_length;
806 uint16_t manufacturer_id;
807 #define UFS_MANUFACTURER_ID_TOSHIBA 0x0198
808 #define UFS_MANUFACTURER_ID_HYNIX 0x01AD
809 #define UFS_MANUFACTURER_ID_SAMSUNG 0x01CE
810 #define UFS_MANUFACTURER_ID_HI1861 0x08B6
811 #define UFS_MANUFACTURER_ID_MICRON 0x012C
812 #define UFS_MANUFACTURER_ID_SANDISK 0x0145
813 uint16_t dev_spec_version;
814 uint16_t manufacturer_date;
815
816 /* Virtual memory reference for driver */
817 void *mem_pool;
818 void *wr_buf;
819 struct dwc_ufs_utrd *utrl_base_addr;
820 struct dwc_ufs_utmrd *utmrl_base_addr;
821 struct dwc_ufs_ucd *ucdl_base_addr;
822
823 struct dwc_ufs_hcd_lrb *lrb;
824 struct dwc_ufshcd_dm_lrb dm_lrb;
825
826 /* Outstanding requests */
827 uint32_t outstanding_xfer_reqs;
828
829 uint8_t is_init;
830 };
831
832 /* Byte swap u16 */
swap_16(uint16_t val)833 static inline uint16_t swap_16(uint16_t val)
834 {
835 return (uint16_t)((val << 8) | (val >> 8)); /* shift 8 */
836 }
837
838 /* Byte swap unsigned int */
swap_32(uint32_t val)839 static inline uint32_t swap_32(uint32_t val)
840 {
841 val = ((val << 8) & 0xFF00FF00) | ((val >> 8) & 0xFF00FF); /* shift 8 */
842 return (uint32_t)((val << 16) | (val >> 16)); /* shift 16 */
843 }
844
to_bigendian32(uint32_t val)845 static inline uint32_t to_bigendian32(uint32_t val)
846 {
847 #ifdef HOST_BIG_ENDIAN
848 return val;
849 #else
850 return swap_32(val);
851 #endif
852 }
853
to_littleendian32(uint32_t val)854 static inline uint32_t to_littleendian32(uint32_t val)
855 {
856 #ifdef HOST_BIG_ENDIAN
857 return swap_32(val);
858 #else
859 return val;
860 #endif
861 }
862
to_bigendian16(uint16_t val)863 static inline uint16_t to_bigendian16(uint16_t val)
864 {
865 #ifdef HOST_BIG_ENDIAN
866 return val;
867 #else
868 return swap_16(val);
869 #endif
870 }
871
to_littleendian16(uint16_t val)872 static inline uint16_t to_littleendian16(uint16_t val)
873 {
874 #ifdef HOST_BIG_ENDIAN
875 return swap_16(val);
876 #else
877 return val;
878 #endif
879 }
880
ufs_waitms(uint32_t delay)881 static inline void ufs_waitms(uint32_t delay)
882 {
883 while (delay--)
884 udelay(1000); /* delay 1000us */
885 }
886
887 /* UFS Command Opcodes */
888 #define READ_DESC_OPCODE 0x1
889 #define WRITE_DESC_OPCODE 0x2
890 #define READ_ATTR_OPCODE 0x3
891 #define WRITE_ATTR_OPCODE 0x4
892 #define READ_FLAG_OPCODE 0x5
893 #define SET_FLAG_OPCODE 0x6
894 #define CLEAR_FLAG_OPCODE 0x7
895 #define TOGGLE_FLAG_OPCODE 0x8
896
897 /* Descriptor Idn's */
898 #define DEVICE_DESC 0x00
899 #define CONFIGURATION_DESC 0x01
900 #define UNIT_DESC 0x02
901 #define INTERCONNECT_DESC 0x04
902 #define STRING_DESC 0x05
903 #define GEOMETRY_DESC 0x07
904 #define POWER_DESC 0x08
905 #define HEALTH_DESC 0x09
906
907 #define DEVICE_DESC_LENGTH 0x40
908 #define UNIT_DESC_LENGTH 0x23
909 #define GEOMETRY_DESC_LENGTH 0x44
910 #define CONFIGURATION_DESC_LENGTH 0x90
911 #define INTERCONNECT_DESC_LENGTH 0x06
912 #define STRING_DESC_LENGTH 0xFE
913 #define POWER_DESC_LENGTH 0x62
914 #define HEALTH_DESC_LENGTH 0x25
915 #define MAX_DESC_LENGTH 0xFF
916
917 #define STANDARD_RD_REQ 0x01
918 #define STANDARD_WR_REQ 0x81
919
920 #define QUERY_RESPONSE_HEAD_OFFSET 32
921 #define QUERY_RESPONSE_DATA_OFFSET 2
922
923 #define UTP_UFS_STORAGE_COMMAND (1 << 4)
924
925 enum info_show_type {
926 UFS_INFO_SHOW_DEVICE_DESC = 0x00,
927 UFS_INFO_SHOW_CONFIGURATION_DESC = 0x01,
928 UFS_INFO_SHOW_UNIT_DESC = 0x02,
929 UFS_INFO_SHOW_INTERCONNECT_DESC = 0x04,
930 UFS_INFO_SHOW_STRING_DESC = 0x05,
931 UFS_INFO_SHOW_GEOMETRY_DESC = 0x07,
932 UFS_INFO_SHOW_HEALTH_DESC = 0x09,
933 UFS_INFO_SHOW_ALL = 0x0E,
934 UFS_INFO_SHOW_BASIC = 0x0F,
935 };
936
937 /*
938 * UFS Status/Error Macros used as return values for all functions
939 */
940 enum {
941 UFS_SUCCESS = 0x00,
942 UFS_FAILURE = -0x01,
943 UFS_LINK_STARTUP_FAIL = -0x02,
944 UFS_UTRD_DOORBELL_TIMEOUT = -0x03,
945 UFS_NOP_RESP_FAIL = -0x04,
946 UFS_INVALID_NOP_IN = -0x05,
947 UFS_UTMRD_DOORBELL_TIMEOUT = -0x06,
948 UFS_FDEVICE_INIT_FAIL = -0x07,
949
950 UFS_SOFTWARE_ERROR = -0x0F,
951
952 /* response upiu status error */
953 RESP_STAT_CONDITION_MET = -0x14,
954 RESP_STAT_BUSY = -0x15,
955 RESP_STAT_RESERVATION_CONFLICT = -0x16,
956 RESP_STAT_TASK_SET_FULL = -0x17,
957 RESP_STAT_ACA_ACTIVE = -0x18,
958 RESP_STAT_TASK_ABORTED = -0x19,
959 RESP_STAT_UNKNOWN = -0x1F,
960
961 #define RET_SENSE_KEY_OFF (0x20)
962 /* sense key */
963 NO_SENSE = -0x20,
964 RECOVERED_ERROR = -0x21,
965 NOT_READY = -0x22,
966 MEDIUM_ERROR = -0x23,
967 HARDWARE_ERROR = -0x24,
968 ILLEGAL_REQUEST = -0x25,
969 UNIT_ATTENTION = -0x26,
970 DATA_PROTECT = -0x27,
971 BLANK_CHECK = -0x28,
972 VENDOR_SPECIFIC = -0x29,
973 ABORTED_COMMAND = -0x2B,
974 VOLUME_OVERFLOW = -0x2D,
975 MISCOMPARE = -0x2E,
976
977 /* RPMB Operation Results */
978 UFS_RPMB_GENERAL_FAILURE = -0x31,
979 UFS_AUTHENTICATION_FAILURE = -0x32,
980 UFS_COUNTER_FAILURE = -0x33,
981 UFS_ADDRESS_FAILURE = -0x34,
982 UFS_WRITE_FAILURE = -0x35,
983 UFS_READ_FAILURE = -0x36,
984 UFS_AUTH_KEY_NOT_PROGRAMMED = -0x37,
985 UFS_RPMB_WR_COUNTER_EXPIRED = -0x38,
986 UFS_NONCE_MISMATCH = -0x39,
987 UFS_MAC_MISMATCH = -0x3a,
988
989 #define RET_UIC_CONFIG_ERROR_OFF (0xA0)
990 /* UIC Config Result Error */
991 UFS_UIC_TIMEOUT = -0xA0,
992 INVALID_MIB_ATTRIBUTE = -0xA1,
993 INVALID_MIB_ATTRIBUTE_VALUE = -0xA2,
994 READ_ONLY_MIB_ATTRIBUTE = -0xA3,
995 WRITE_ONLY_MIB_ATTRIBUTE = -0xA4,
996 BAD_INDEX = -0xA5,
997 LOCKED_MIB_ATTRIBUTE = -0xA6,
998 BAD_TEST_FEATURE_INDEX = -0xA7,
999 PEER_COMMUNICATION_FAILURE = -0xA8,
1000 BUSY = -0xA9,
1001 DME_FAILURE = -0xAA,
1002
1003 #define RET_UTRD_OCS_ERROR_OFF (0xB0)
1004 /* utrd ocs error */
1005 INVALID_COMMAND_TABLE_ATTRIBUTES = -0xB1,
1006 INVALID_PRDT_ATTRIBUTES = -0xB2,
1007 MISMATCH_DATA_BUFFER_SIZE = -0xB3,
1008 MISMATCH_RESPONSE_UPIU_SIZE = -0xB4,
1009 COMMUNICATION_FAILURE = -0xB5,
1010 ABORTED = -0xB6,
1011 FATAL_ERROR = -0xB7,
1012 INVALID_OCS_VALUE = -0xBF,
1013
1014 /* Query response code */
1015 QUERY_PARAMETER_NOT_READABLE = -0xF6,
1016 QUERY_PARAMETER_NOT_WRITEABLE = -0xF7,
1017 QUERY_PARAMETER_ALREADY_WRITTEN = -0xF8,
1018 QUERY_INVALID_LENGTH = -0xF9,
1019 QUERY_INVALID_VALUE = -0xFA,
1020 QUERY_INVALID_SELECTOR = -0xFB,
1021 QUERY_INVALID_INDEX = -0xFC,
1022 QUERY_INVALID_IDN = -0xFD,
1023 QUERY_INVALID_OPCODE = -0xFE,
1024 QUERY_GENERAL_FAILURE = -0xFF
1025 };
1026
1027 /* DME Commands */
1028 enum {
1029 DWC_UFS_DME_GET = 0x01,
1030 DWC_UFS_DME_SET = 0x02,
1031 DWC_UFS_DME_PEER_GET = 0x03,
1032 DWC_UFS_DME_PEER_SET = 0x04,
1033 DWC_UFS_DME_POWERON = 0x10,
1034 DWC_UFS_DME_POWEROFF = 0x11,
1035 DWC_UFS_DME_ENABLE = 0x12,
1036 DWC_UFS_DME_RESET = 0x14,
1037 DWC_UFS_DME_ENDPOINTRESET = 0x15,
1038 DWC_UFS_DME_LINKSTARTUP = 0x16,
1039 DWC_UFS_DME_HIBERNATE_ENTER = 0x17,
1040 DWC_UFS_DME_HIBERNATE_EXIT = 0x18,
1041 DWC_UFS_DME_TEST_MODE = 0x1A,
1042 };
1043
1044 /* DME Result Codes */
1045 enum {
1046 DWC_UFS_DME_SUCCESS = 0x00,
1047 DWC_UFS_DME_INV_MIB_ATTR = 0x01,
1048 DWC_UFS_DME_INV_MIB_ATTR_VAL = 0x02,
1049 DWC_UFS_DME_READ_ONLY_MIB_ATTR = 0x03,
1050 DWC_UFS_DME_WRITE_ONLY_MIB_ATTR = 0x04,
1051 DWC_UFS_DME_BAD_INDEX = 0x05,
1052 DWC_UFS_DME_LOCKED_MIB_ATTR = 0x06,
1053 DWC_UFS_DME_BAD_TEST_FEAT_INDEX = 0x07,
1054 DWC_UFS_DME_PEER_COMM_FAILURE = 0x08,
1055 DWC_UFS_DME_BUSY = 0x09,
1056 DWC_UFS_DME_FAILURE = 0x0a,
1057
1058 DWC_UFS_DME_RESULT_CODE_MASK = 0xff,
1059 };
1060
1061 /* UTP Transfer Request Data Direction (DD) */
1062 enum {
1063 UTP_NO_DATA_TRANSFER = 0x00,
1064 UTP_HOST_TO_DEVICE = 0x02,
1065 UTP_DEVICE_TO_HOST = 0x04
1066 };
1067
1068 /* UPIU Read/Write flags */
1069 enum {
1070 UPIU_CMD_FLAGS_NONE = 0x00,
1071 UPIU_CMD_FLAGS_WRITE = 0x20,
1072 UPIU_CMD_FLAGS_READ = 0x40
1073 };
1074
1075 enum flags_id {
1076 FDEVICE_INIT = 0x1,
1077 FPERMANANT_WPEN = 0x2,
1078 FPOWERON_WPEN = 0x3,
1079 FBG_OPSEN = 0x4,
1080 FPURGE_OPSEN = 0x6,
1081 FPHYRES_REMOVAL = 0x8,
1082 FBUSY_RTC = 0x9
1083 };
1084
1085 /* use for unipro & M-PHY 's configuration and control */
1086 enum uic_dme_type {
1087 /* Configuration */
1088 DME_GET = 0x01,
1089 DME_SET = 0x02,
1090 DME_PEER_GET = 0x03,
1091 DME_PEER_SET = 0x04,
1092 /* Control */
1093 DME_POWERON = 0x10,
1094 DME_POWEROFF = 0x11,
1095 DME_ENABLE = 0x12,
1096
1097 DME_RESERVE_1 = 0x13,
1098 DME_RESET = 0x14,
1099 DME_ENDPOINTRESET = 0x15,
1100 DME_LINKSTARTUP = 0x16,
1101 DME_HIBERNATE_ENTER = 0x17,
1102 DME_HIBERNATE_EXIT = 0x18,
1103 DME_RESERVE_2 = 0x19,
1104 DME_TEST_MODE = 0x1A,
1105 };
1106
1107 enum attr_id {
1108 B_BOOT_LUNEN = 0x0,
1109 B_CURRENT_PM = 0x2,
1110 B_ACTIV_ICC_LEVEL = 0x3,
1111 B_OUT_OF_ORDER_DATAEN = 0x4,
1112 B_BCKGND_OPS_STATUS = 0x5,
1113 B_PURGE_STATUS = 0x6,
1114 B_MAX_DATA_IN_SIZE = 0x7,
1115 B_MAX_DATA_OUT_SIZE = 0x8,
1116 D_DYN_CAP_NEEDED = 0x9,
1117 B_REFCLK_FREQ = 0xA,
1118 B_CONFIG_DESC_LOCK = 0xB,
1119 B_MAX_NUM_OF_RTT = 0xC,
1120 W_EXCEPTION_EVENT_CONTROL = 0xD,
1121 W_EXCEPTION_EVENT_STATUS = 0xE,
1122 D_SECONDS_PASSED = 0xF,
1123 W_CONTEXT_CONF = 0x10,
1124 D_CORR_PRG_BLKNUM = 0x11
1125 };
1126
1127 struct ufs {
1128 uint64_t capacity;
1129 unsigned long long blocksize;
1130 int (*block_read)(uint64_t dest_addr, uint64_t src_offset, uint32_t lenth);
1131 int (*block_write)(uint64_t src_addr, uint64_t dest_offset, uint32_t lenth);
1132 int (*boot_block_write)(uint64_t src_addr, uint64_t dest_offset, uint32_t lenth);
1133 };
1134
1135 unsigned int *ufs_pack_cid(void);
1136 struct ufs *get_ufs_info(void);
1137 int ufs_read_capacity(uint32_t *lba);
1138
1139 int ufs_set_bootlun(uint8_t lun);
1140 int ufs_set_active_lun(uint8_t lun);
1141
1142 int ufs_read_boot_storage(uint64_t dest_addr, uint64_t src_offset, uint32_t size);
1143 int ufs_write_boot_storage(uint64_t dest_addr, uint64_t src_offset, uint32_t size);
1144
1145 int ufs_read_storage(uint64_t dest_addr, uint64_t src_offset, uint32_t size);
1146 int ufs_write_storage(uint64_t src_addr, uint64_t dest_offset, uint32_t size);
1147 void send_uic_command(uint32_t command, uint32_t arg1, uint32_t arg2, uint32_t arg3);
1148 uint32_t uic_cmd_read(uint32_t command, uint32_t arg1);
1149 void ufs_readreg_all(void);
1150
1151 int ufs_set_flag(enum flags_id idn, uint8_t *flags_ret);
1152 int ufs_read_flag(enum flags_id idn, uint8_t *flags_ret);
1153
1154 int read_descriptor(const void *req_upiu, void **resp_upiu);
1155 int write_descriptor(const void *req_upiu);
1156
1157 int read_attribute(enum attr_id idn, uint8_t indexx, uint8_t selector, uint32_t *ret_value);
1158 int write_attribute(enum attr_id idn, uint8_t indexx, uint8_t selector, uint32_t *value);
1159
1160 int ufs_storage_init(void);
1161
1162 int ufs_hibernate_exit(void);
1163 int ufs_hibernate_enter(void);
1164
1165 int do_mode_change(const struct pwr_mode_params *pmp);
1166 int ufs_show_desc_info(enum info_show_type type);
1167
1168 void modify_desc_upiu(const struct desc_params *params);
1169 void ufs_reg_dump(void);
1170 void ufs_reinit(void);
1171 #ifdef CONFIG_EXT4_SPARSE
1172 int ufs_ext4_unsparse(const u8 *pbuf, u32 blk, u32 cnt);
1173 #endif
1174 #endif
1175 #endif
1176