1 #ifndef __USB3_HW_H__ 2 #define __USB3_HW_H__ 3 4 #include "usb3.h" 5 6 /****************************************************************************/ 7 /* Core Global Registers */ 8 9 /** 10 * This enum represents the bit fields of the Core SoC Bus Configuration 0 11 * Register (GSBUSCFG0). 12 */ 13 typedef enum gsbuscfg0_data { 14 /** Bus Burst Len <i>Access: R_W</i>. 15 * - 0: single 16 * - 1: incr 17 * - 3: incr4 18 * - 7: incr8 19 * - 15: incr16 20 * - 31: incr32 (non-AHB mode only) 21 * - 63: incr64 (non-AHB mode only) 22 * - 127: incr128 (non-AHB mode only) 23 * - 255: incr256 (non-AHB mode only) 24 */ 25 USB3_SBUSCFG0_HBURSTLEN_BITS = 0x000000ff, 26 USB3_SBUSCFG0_HBURSTLEN_SHIFT = 0, 27 28 USB3_SBUSCFG0_INT_DMA_BURST_SINGLE = 0, 29 USB3_SBUSCFG0_INT_DMA_BURST_INCR = 1, 30 USB3_SBUSCFG0_INT_DMA_BURST_INCR4 = 3, 31 USB3_SBUSCFG0_INT_DMA_BURST_INCR8 = 7, 32 USB3_SBUSCFG0_INT_DMA_BURST_INCR16 = 15, 33 USB3_SBUSCFG0_INT_DMA_BURST_INCR32 = 31, 34 USB3_SBUSCFG0_INT_DMA_BURST_INCR64 = 63, 35 USB3_SBUSCFG0_INT_DMA_BURST_INCR128 = 127, 36 USB3_SBUSCFG0_INT_DMA_BURST_INCR256 = 255, 37 38 /** Descriptor Write is Posted <i>Access: R_W</i> */ 39 USB3_SBUSCFG0_DES_WR_POST_BIT = 0x00000100, 40 USB3_SBUSCFG0_DES_WR_POST_SHIFT = 8, 41 42 /** Data Write is Posted <i>Access: R_W</i> */ 43 USB3_SBUSCFG0_DAT_WR_POST_BIT = 0x00000200, 44 USB3_SBUSCFG0_DAT_WR_POST_SHIFT = 9, 45 46 /** Descriptor Access is Big-Endian <i>Access: R_W</i> */ 47 USB3_SBUSCFG0_DES_BIG_END_BIT = 0x00000400, 48 USB3_SBUSCFG0_DES_BIG_END_SHIFT = 10, 49 50 /** Data Access is Big-Endian <i>Access: R_W</i> */ 51 USB3_SBUSCFG0_DAT_BIG_END_BIT = 0x00000800, 52 USB3_SBUSCFG0_DAT_BIG_END_SHIFT = 11, 53 54 /** Store and Forward Mode <i>Access: R_W</i> */ 55 USB3_SBUSCFG0_STORE_AND_FORWARD_BIT = 0x00001000, 56 USB3_SBUSCFG0_STORE_AND_FORWARD_SHIFT = 12, 57 58 /** Force Single Request <i>Access: R_W</i> */ 59 USB3_SBUSCFG0_SING_REQ_BIT = 0x00004000, 60 USB3_SBUSCFG0_SING_REQ_SHIFT = 14, 61 62 /** Descriptor Readback Enable <i>Access: R_W</i> */ 63 USB3_SBUSCFG0_READ_AFTER_WRITE_BIT = 0x00008000, 64 USB3_SBUSCFG0_READ_AFTER_WRITE_SHIFT = 15, 65 66 /** Descriptor Write Request Info <i>Access: R_W</i> */ 67 USB3_SBUSCFG0_DES_WR_REQ_INFO_BITS = 0x000f0000, 68 USB3_SBUSCFG0_DES_WR_REQ_INFO_SHIFT = 16, 69 70 /** Data Write Request Info <i>Access: R_W</i> */ 71 USB3_SBUSCFG0_DAT_WR_REQ_INFO_BITS = 0x00f00000, 72 USB3_SBUSCFG0_DAT_WR_REQ_INFO_SHIFT = 20, 73 74 /** Descriptor Read Request Info <i>Access: R_W</i> */ 75 USB3_SBUSCFG0_DES_RD_REQ_INFO_BITS = 0x0f000000, 76 USB3_SBUSCFG0_DES_RD_REQ_INFO_SHIFT = 24, 77 78 /** Data Read Request Info <i>Access: R_W</i> */ 79 USB3_SBUSCFG0_DAT_RD_REQ_INFO_BITS = 0xf0000000, 80 USB3_SBUSCFG0_DAT_RD_REQ_INFO_SHIFT = 28, 81 } gsbuscfg0_data_t; 82 83 /** 84 * This enum represents the bit fields of the Core SoC Bus Configuration 1 85 * Register (GSBUSCFG1). 86 */ 87 typedef enum gsbuscfg1_data { 88 /** OCP Address Space For Descriptor <i>Access: R_W</i> */ 89 USB3_SBUSCFG1_DES_ADDR_SPC_BITS = 0x0000000f, 90 USB3_SBUSCFG1_DES_ADDR_SPC_SHIFT = 0, 91 92 /** OCP Address Space For Data <i>Access: R_W</i> */ 93 USB3_SBUSCFG1_DAT_ADDR_SPC_BITS = 0x000000f0, 94 USB3_SBUSCFG1_DAT_ADDR_SPC_SHIFT = 4, 95 } gsbuscfg1_data_t; 96 97 /** 98 * This enum represents the bit fields of the Core Tx Threshold Control 99 * Register (GTXTHRCFG). 100 */ 101 typedef enum gtxthrcfg_data { 102 /** SoC Bus Transmit Threshold Length <i>Access: R_W</i> */ 103 USB3_TXTHRCFG_SBUS_THR_LEN_BITS = 0x000007ff, 104 USB3_TXTHRCFG_SBUS_THR_LEN_SHIFT = 0, 105 106 /** SoC Bus Non-ISO Transmit Threshold Enable <i>Access: R_W</i> */ 107 USB3_TXTHRCFG_SBUS_NON_ISO_THR_EN_BIT = 0x00004000, 108 USB3_TXTHRCFG_SBUS_NON_ISO_THR_EN_SHIFT = 14, 109 110 /** SoC Bus ISO Transmit Threshold Enable <i>Access: R_W</i> */ 111 USB3_TXTHRCFG_SBUS_ISO_THR_EN_BIT = 0x00008000, 112 USB3_TXTHRCFG_SBUS_ISO_THR_EN_SHIFT = 15, 113 114 /** USB Transmit Threshold Length <i>Access: R_W</i> */ 115 USB3_TXTHRCFG_USB_THR_LEN_BITS = 0x1fff0000, 116 USB3_TXTHRCFG_USB_THR_LEN_SHIFT = 16, 117 118 /** USB Non-ISO Transmit Threshold Enable <i>Access: R_W</i> */ 119 USB3_TXTHRCFG_USB_NON_ISO_THR_EN_BIT = 0x40000000, 120 USB3_TXTHRCFG_USB_NON_ISO_THR_EN_SHIFT = 30, 121 122 /** USB ISO Transmit Threshold Enable <i>Access: R_W</i> */ 123 USB3_TXTHRCFG_USB_ISO_THR_EN_BIT = 0x80000000, 124 USB3_TXTHRCFG_USB_ISO_THR_EN_SHIFT = 31, 125 } gtxthrcfg_data_t; 126 127 /** 128 * This enum represents the bit fields of the Core Rx Threshold Control 129 * Register (GRXTHRCFG). 130 */ 131 typedef enum grxthrcfg_data { 132 /** Receive Threshold Length <i>Access: R_W</i> */ 133 USB3_RXTHRCTL_THR_LEN_BITS = 0x07ff, 134 USB3_RXTHRCTL_THR_LEN_SHIFT = 0, 135 136 /** Receive Threshold Enable <i>Access: R_W</i> */ 137 USB3_RXTHRCTL_THR_EN_BIT = 0x8000, 138 USB3_RXTHRCTL_THR_EN_SHIFT = 15, 139 } grxthrcfg_data_t; 140 141 /** 142 * This enum represents the bit fields of the Core Control 143 * Register (GCTL). 144 */ 145 typedef enum gctl_data { 146 /** Disable Clock Gating <i>Access: R_W</i> */ 147 USB3_GCTL_DSBL_CLCK_GTNG_BIT = 0x00000001, 148 USB3_GCTL_DSBL_CLCK_GTNG_SHIFT = 0, 149 150 /** Global Hibernation Enable <i>Access: R_W</i> */ 151 USB3_GCTL_GBL_HIBER_EN_BIT = 0x00000002, 152 USB3_GCTL_GBL_HIBER_EN_SHIFT = 1, 153 154 /** U2Exit LFPS <i>Access: R_W</i> */ 155 USB3_GCTL_GBL_U2EXIT_LFPS = 0x00000004, 156 USB3_GCTL_GBL_U2EXIT_LFPS_SHIFT = 2, 157 158 /** Disable Scrambling <i>Access: R_W</i> */ 159 USB3_GCTL_DIS_SCRAMBLE_BIT = 0x00000008, 160 USB3_GCTL_DIS_SCRAMBLE_SHIFT = 3, 161 162 /** Scale-down Mode <i>Access: R_W</i> */ 163 USB3_GCTL_SCALE_DOWN_BITS = 0x00000030, 164 USB3_GCTL_SCALE_DOWN_SHIFT = 4, 165 166 /** RAM Clock Select <i>Access: R_W</i> */ 167 USB3_GCTL_RAM_CLK_SEL_BITS = 0x000000c0, 168 USB3_GCTL_RAM_CLK_SEL_SHIFT = 6, 169 170 /** Debug Attach <i>Access: R_W</i> */ 171 USB3_GCTL_DEBUG_ATTACH_BIT = 0x00000100, 172 USB3_GCTL_DEBUG_ATTACH_SHIFT = 8, 173 174 /** Loopback Enable <i>Access: R_W</i> */ 175 USB3_GCTL_LPBK_EN_BIT = 0x00000200, 176 USB3_GCTL_LPBK_EN_SHIFT = 9, 177 178 /** Local Loopback Enable <i>Access: R_W</i> */ 179 USB3_GCTL_LOCAL_LPBK_EN_BIT = 0x00000400, 180 USB3_GCTL_LOCAL_LPBK_EN_SHIFT = 10, 181 182 /** Core Soft Reset <i>Access: R_W</i> */ 183 USB3_GCTL_CORE_SOFT_RST_BIT = 0x00000800, 184 USB3_GCTL_CORE_SOFT_RST_SHIFT = 11, 185 186 /** Port Capability Direction <i>Access: R_W</i> */ 187 USB3_GCTL_PRT_CAP_DIR_BITS = 0x00003000, 188 USB3_GCTL_PRT_CAP_DIR_SHIFT = 12, 189 190 /** Port Capability Values */ 191 USB3_GCTL_PRT_CAP_HOST = 1, 192 USB3_GCTL_PRT_CAP_DEVICE = 2, 193 USB3_GCTL_PRT_CAP_OTG = 3, 194 195 /** Frame Scale Down <i>Access: R_W</i> */ 196 USB3_GCTL_FRMSCLDWN_BITS = 0x0000c000, 197 USB3_GCTL_FRMSCLDWN_SHIFT = 14, 198 199 /** U2 Reset ECN <i>Access: R_W</i> */ 200 USB3_GCTL_U2RSTECN_BIT = 0x00010000, 201 USB3_GCTL_U2RSTECN_SHIFT = 16, 202 203 /** Power Down Scale <i>Access: R_W</i> */ 204 USB3_GCTL_PWR_DN_SCALE_BITS = 0xfff80000, 205 USB3_GCTL_PWR_DN_SCALE_SHIFT = 19, 206 } gctl_data_t; 207 208 /** 209 * This enum represents the bit fields of the Core Interrupt Mask 210 * Register (GEVTEN). 211 */ 212 typedef enum gevten_data { 213 /** ULPI Carkit Event Enable <i>Access: R_W</i> */ 214 USB3_GEVTEN_ULPI_CK_EVT_EN_BIT = 0x00000001, 215 USB3_GEVTEN_ULPI_CK_EVT_SHIFT = 0, 216 217 /** I2C Event Enable <i>Access: R_W</i> */ 218 USB3_GEVTEN_I2C_EVT_EN_BIT = 0x00000002, 219 USB3_GEVTEN_I2C_EVT_EN_SHIFT = 1, 220 } gevten_data_t; 221 222 /** 223 * This enum represents the bit fields of the Core Status 224 * Register (GSTS). 225 */ 226 typedef enum gsts_data { 227 /** Current Mode <i>Access: RO</i>. 228 * - 0: Device Mode 229 * - 1: Host Mode 230 * - 2: DRD Mode 231 */ 232 USB3_GSTS_CURMODE_BITS = 0x00000003, 233 USB3_GSTS_CURMODE_SHIFT = 0, 234 235 USB3_GSTS_DEVICE_MODE = 0, 236 USB3_GSTS_HOST_MODE = 1, 237 USB3_GSTS_DRD_MODE = 2, 238 239 /** Bus Error Address Valid <i>Access: RO</i> */ 240 USB3_GSTS_BUS_ERR_ADDR_VLD_BIT = 0x00000010, 241 USB3_GSTS_BUS_ERR_ADDR_VLD_SHIFT = 4, 242 243 /** CSR Timeout */ 244 USB3_GSTS_CSR_TIMEOUT_BIT = 0x00000020, 245 USB3_GSTS_CSR_TIMEOUT_SHIFT = 5, 246 247 /** Device Interrupt Pending */ 248 USB3_GSTS_DEV_EVT_PENDING_BIT = 0x00000040, 249 USB3_GSTS_DEV_EVT_PENDING_SHIFT = 6, 250 251 /** Host Interrupt Pending */ 252 USB3_GSTS_HOST_EVT_PENDING_BIT = 0x00000080, 253 USB3_GSTS_HOST_EVT_PENDING_SHIFT = 7, 254 255 /** ADP Interrupt Pending */ 256 USB3_GSTS_ADP_EVT_PENDING_BIT = 0x00000100, 257 USB3_GSTS_ADP_EVT_PENDING_SHIFT = 8, 258 259 /** BC Interrupt Pending */ 260 USB3_GSTS_BC_EVT_PENDING_BIT = 0x00000200, 261 USB3_GSTS_BC_EVT_PENDING_SHIFT = 9, 262 263 /** OTG Interrupt Pending */ 264 USB3_GSTS_OTG_EVT_PENDING_BIT = 0x00000400, 265 USB3_GSTS_OTG_EVT_PENDING_SHIFT = 10, 266 267 /** Current BELT Value <i>Access: RO</i> */ 268 USB3_GSTS_CBELT_BITS = 0xfff00000, 269 USB3_GSTS_CBELT_SHIFT = 20, 270 } gsts_data_t; 271 272 /** 273 * This enum represents the bit fields of the Hardware Parameters 0 274 * Register (GHWPARAMS0). 275 */ 276 typedef enum ghwparams0_data { 277 USB3_HWP0_MODE_BITS = 0x00000007, 278 USB3_HWP0_MODE_SHIFT = 0, 279 280 USB3_HWP0_MBUS_TYPE_BITS = 0x00000038, 281 USB3_HWP0_MBUS_TYPE_SHIFT = 3, 282 283 USB3_HWP0_SBUS_TYPE_BITS = 0x000000c0, 284 USB3_HWP0_SBUS_TYPE_SHIFT = 6, 285 286 USB3_HWP0_MDWIDTH_BITS = 0x0000ff00, 287 USB3_HWP0_MDWIDTH_SHIFT = 8, 288 289 USB3_HWP0_SDWIDTH_BITS = 0x00ff0000, 290 USB3_HWP0_SDWIDTH_SHIFT = 16, 291 292 USB3_HWP0_AWIDTH_BITS = 0x3f000000, 293 USB3_HWP0_AWIDTH_SHIFT = 24, 294 } ghwparams0_data_t; 295 296 /** 297 * This enum represents the bit fields of the Hardware Parameters 1 298 * Register (GHWPARAMS1). 299 */ 300 typedef enum ghwparams1_data { 301 USB3_HWP1_IDWIDTH_M1_BITS = 0x00000007, 302 USB3_HWP1_IDWIDTH_M1_SHIFT = 0, 303 304 USB3_HWP1_BURSTWIDTH_M1_BITS = 0x00000038, 305 USB3_HWP1_BURSTWIDTH_M1_SHIFT = 3, 306 307 USB3_HWP1_DATAINFOWIDTH_BITS = 0x000001c0, 308 USB3_HWP1_DATAINFOWIDTH_SHIFT = 6, 309 310 USB3_HWP1_REQINFOWIDTH_BITS = 0x00000e00, 311 USB3_HWP1_REQINFOWIDTH_SHIFT = 9, 312 313 USB3_HWP1_ASPACEWIDTH_BITS = 0x00007000, 314 USB3_HWP1_ASPACEWIDTH_SHIFT = 12, 315 316 USB3_HWP1_DEV_NUM_INT_BITS = 0x001f8000, 317 USB3_HWP1_DEV_NUM_INT_SHIFT = 15, 318 319 USB3_HWP1_NUM_RAMS_BITS = 0x00600000, 320 USB3_HWP1_NUM_RAMS_SHIFT = 21, 321 322 USB3_HWP1_SPRAM_TYP_BIT = 0x00800000, 323 USB3_HWP1_SPRAM_TYP_SHIFT = 23, 324 325 USB3_HWP1_EN_PWROPT_BITS = 0x03000000, 326 USB3_HWP1_EN_PWROPT_SHIFT = 24, 327 328 USB3_EN_PWROPT_NONE = 0, 329 USB3_EN_PWROPT_CLK_GATING_ONLY = 1, 330 USB3_EN_PWROPT_HIBERNATION = 2, 331 332 USB3_HWP1_MAC_PHY_CLKS_SYNC_BIT = 0x04000000, 333 USB3_HWP1_MAC_PHY_CLKS_SYNC_SHIFT = 26, 334 335 USB3_HWP1_MAC_RAM_CLKS_SYNC_BIT = 0x08000000, 336 USB3_HWP1_MAC_RAM_CLKS_SYNC_SHIFT = 27, 337 338 USB3_HWP1_RAM_BUS_CLKS_SYNC_BIT = 0x10000000, 339 USB3_HWP1_RAM_BUS_CLKS_SYNC_SHIFT = 28, 340 341 USB3_HWP1_RM_OPT_FEATURES_BIT = 0x40000000, 342 USB3_HWP1_RM_OPT_FEATURES_SHIFT = 30, 343 } ghwparams1_data_t; 344 345 /** 346 * This enum represents the bit fields of the Hardware Parameters 2 347 * Register (GHWPARAMS2). 348 */ 349 typedef enum ghwparams2_data { 350 USB3_HWP2_USERID_BITS = 0xffffffff, 351 USB3_HWP2_USERID_SHIFT = 0, 352 } ghwparams2_data_t; 353 354 /** 355 * This enum represents the bit fields of the Hardware Parameters 3 356 * Register (GHWPARAMS3). 357 */ 358 typedef enum ghwparams3_data { 359 USB3_HWP3_SSPHY_IFC_BITS = 0x00000003, 360 USB3_HWP3_SSPHY_IFC_SHIFT = 0, 361 362 USB3_HWP3_HSPHY_IFC_BITS = 0x0000000c, 363 USB3_HWP3_HSPHY_IFC_SHIFT = 2, 364 365 USB3_HWP3_FSPHY_IFC_BITS = 0x00000030, 366 USB3_HWP3_FSPHY_IFC_SHIFT = 4, 367 368 USB3_HWP3_HSPHY_DWIDTH_BITS = 0x000000c0, 369 USB3_HWP3_HSPHY_DWIDTH_SHIFT = 6, 370 371 USB3_HWP3_VEND_CTL_IFC_BIT = 0x00000400, 372 USB3_HWP3_VEND_CTL_IFC_SHIFT = 10, 373 374 USB3_HWP3_ULPI_CARKIT_BIT = 0x00000800, 375 USB3_HWP3_ULPI_CARKIT_SHIFT = 11, 376 377 USB3_HWP3_NUM_EPS_BITS = 0x0003f000, 378 USB3_HWP3_NUM_EPS_SHIFT = 12, 379 380 USB3_HWP3_NUM_IN_EPS_BITS = 0x007c0000, 381 USB3_HWP3_NUM_IN_EPS_SHIFT = 18, 382 383 USB3_HWP3_TOT_XFR_RSRC_BITS = 0x7f800000, 384 USB3_HWP3_TOT_XFR_RSRC_SHIFT = 23, 385 } ghwparams3_data_t; 386 387 /** 388 * This enum represents the bit fields of the Hardware Parameters 4 389 * Register (GHWPARAMS4). 390 */ 391 typedef enum ghwparams4_data { 392 USB3_HWP4_TRBS_PER_XFER_BITS = 0x0000003f, 393 USB3_HWP4_TRBS_PER_XFER_SHIFT = 0, 394 395 USB3_HWP4_HIBER_SPAD_BITS = 0x0001e000, 396 USB3_HWP4_HIBER_SPAD_SHIFT = 13, 397 398 USB3_HWP4_NUM_SS_USB_INST_BITS = 0x001e0000, 399 USB3_HWP4_NUM_SS_USB_INST_SHIFT = 17, 400 401 USB3_HWP4_EN_ISOC_SUPT_BIT = 0x00800000, 402 USB3_HWP4_EN_ISOC_SUPT_SHIFT = 23, 403 404 USB3_HWP4_BMU_PTL_DEPTH_BITS = 0x0f000000, 405 USB3_HWP4_BMU_PTL_DEPTH_SHIFT = 24, 406 407 USB3_HWP4_BMU_LSP_DEPTH_BITS = 0xf0000000, 408 USB3_HWP4_BMU_LSP_DEPTH_SHIFT = 28, 409 } ghwparams4_data_t; 410 411 /** 412 * This enum represents the bit fields of the Hardware Parameters 5 413 * Register (GHWPARAMS5). 414 */ 415 typedef enum ghwparams5_data { 416 USB3_HWP5_BMU_BUSGM_DEPTH_BITS = 0x0000000f, 417 USB3_HWP5_BMU_BUSGM_DEPTH_SHIFT = 0, 418 419 USB3_HWP5_RXQ_FIFO_DEPTH_BITS = 0x000003f0, 420 USB3_HWP5_RXQ_FIFO_DEPTH_SHIFT = 4, 421 422 USB3_HWP5_TXQ_FIFO_DEPTH_BITS = 0x0000fc00, 423 USB3_HWP5_TXQ_FIFO_DEPTH_SHIFT = 10, 424 425 USB3_HWP5_DWQ_FIFO_DEPTH_BITS = 0x003f0000, 426 USB3_HWP5_DWQ_FIFO_DEPTH_SHIFT = 16, 427 428 USB3_HWP5_DFQ_FIFO_DEPTH_BITS = 0x0fc00000, 429 USB3_HWP5_DFQ_FIFO_DEPTH_SHIFT = 22, 430 } ghwparams5_data_t; 431 432 /** 433 * This enum represents the bit fields of the Hardware Parameters 6 434 * Register (GHWPARAMS6). 435 */ 436 typedef enum ghwparams6_data { 437 USB3_HWP6_PSQ_FIFO_DEPTH_BITS = 0x0000003f, 438 USB3_HWP6_PSQ_FIFO_DEPTH_SHIFT = 0, 439 440 USB3_HWP6_EN_DBG_PORTS_BIT = 0x00000040, 441 USB3_HWP6_EN_DBG_PORTS_SHIFT = 6, 442 443 USB3_HWP6_EN_FPGA_BIT = 0x00000080, 444 USB3_HWP6_EN_FPGA_SHIFT = 7, 445 446 USB3_HWP6_EN_SRP_BIT = 0x00000400, 447 USB3_HWP6_EN_SRP_SHIFT = 10, 448 449 USB3_HWP6_EN_HNP_BIT = 0x00000800, 450 USB3_HWP6_EN_HNP_SHIFT = 11, 451 452 USB3_HWP6_EN_ADP_BIT = 0x00001000, 453 USB3_HWP6_EN_ADP_SHIFT = 12, 454 455 USB3_HWP6_EN_OTG_BIT = 0x00002000, 456 USB3_HWP6_EN_OTG_SHIFT = 13, 457 458 USB3_HWP6_EN_BC_BIT = 0x00004000, 459 USB3_HWP6_EN_BC_SHIFT = 14, 460 461 USB3_HWP6_EN_BUS_FILTERS_BIT = 0x00008000, 462 USB3_HWP6_EN_BUS_FILTERS_SHIFT = 15, 463 464 USB3_HWP6_RAM0_DEPTH_BITS = 0xffff0000, 465 USB3_HWP6_RAM0_DEPTH_SHIFT = 16, 466 } ghwparams6_data_t; 467 468 /** 469 * This enum represents the bit fields of the Hardware Parameters 7 470 * Register (GHWPARAMS7). 471 */ 472 typedef enum ghwparams7_data { 473 USB3_HWP7_RAM1_DEPTH_BITS = 0x0000ffff, 474 USB3_HWP7_RAM1_DEPTH_SHIFT = 0, 475 476 USB3_HWP7_RAM2_DEPTH_BITS = 0xffff0000, 477 USB3_HWP7_RAM2_DEPTH_SHIFT = 16, 478 } ghwparams7_data_t; 479 480 /** 481 * This enum represents the bit fields of the Hardware Parameters 8 482 * Register (GHWPARAMS8). 483 */ 484 typedef enum ghwparams8_data { 485 USB3_HWP8_DCACHE_DEPTH_BITS = 0xffffffff, 486 USB3_HWP8_DCACHE_DEPTH_SHIFT = 0, 487 } ghwparams8_data_t; 488 489 /** 490 * This enum represents the bit fields of the Debug Queue/FIFO Space 491 * Register (GDBGFIFOSPACE). 492 */ 493 typedef enum gdbgfifospace_data { 494 /** FIFO/Queue Select <i>Access: R_W</i> */ 495 USB3_DBGFIFOSPACE_FIFO_QUEUE_SEL_BITS = 0x000000ff, 496 USB3_DBGFIFOSPACE_FIFO_QUEUE_SEL_SHIFT = 0, 497 498 /* 0 - 31 TxFIFO Number */ 499 /* 32 - 63 RxFIFO Number */ 500 /* 64 - 95 TxReqQ Number */ 501 /* 96 - 127 RxReqQ Number */ 502 /* 128 - 159 RxInfoQ Number */ 503 /* 160 DescFetchQ */ 504 /* 161 EventQ */ 505 /* 162 ProtocolStatusQ */ 506 507 /** Space Available <i>Access: R</i> */ 508 USB3_DBGFIFOSPACE_SPACE_AVAIL_BITS = 0xffff0000, 509 USB3_DBGFIFOSPACE_SPACE_AVAIL_SHIFT = 16, 510 } gdbgfifospace_data_t; 511 512 /** 513 * This enum represents the bit fields of the Debug LTSSM 514 * Register (GDBGLTSSM). 515 */ 516 typedef enum gdbgltssm_data { 517 /** Pipe Status <i>Access: R</i> */ 518 USB3_DBGLTSSM_PIPE_STATUS_BITS = 0x0003ffff, 519 USB3_DBGLTSSM_PIPE_STATUS_SHIFT = 0, 520 521 /** LTDB SubState <i>Access: R</i> */ 522 USB3_DBGLTSSM_LTDB_SUB_STATE_BITS = 0x003c0000, 523 USB3_DBGLTSSM_LTDB_SUB_STATE_SHIFT = 18, 524 525 /** LTDB State <i>Access: R</i> */ 526 USB3_DBGLTSSM_LTDB_STATE_BITS = 0x03c00000, 527 USB3_DBGLTSSM_LTDB_STATE_SHIFT = 22, 528 529 /** LTDB Timeout <i>Access: R</i> */ 530 USB3_DBGLTSSM_LTDB_TIMEOUT_BIT = 0x04000000, 531 USB3_DBGLTSSM_LTDB_TIMEOUT_SHIFT = 26, 532 } gdbgltssm_data_t; 533 534 /** 535 * This enum represents the bit fields of the Core USB2 PHY Configuration 536 * Registers (GUSB2PHYCFGn). 537 */ 538 typedef enum gusb2phycfg_data { 539 /** HS/FS Timeout Calibration <i>Access: R_W</i> */ 540 USB3_USB2PHYCFG_TOUT_CAL_BITS = 0x00000007, 541 USB3_USB2PHYCFG_TOUT_CAL_SHIFT = 0, 542 543 /** UTMI+ PHY Intf Width (8-bit/16-bit) SelecT <i>Access: R_W</i> */ 544 USB3_USB2PHYCFG_PHY_IF_BIT = 0x00000008, 545 USB3_USB2PHYCFG_PHY_IF_SHIFT = 3, 546 /*--------*/ 547 /** ULPI DDR Select <i>Access: R_W</i> */ 548 USB3_USB2PHYCFG_DDR_SEL_BIT = 0x00000008, 549 USB3_USB2PHYCFG_DDR_SEL_SHIFT = 3, 550 551 /** UTMI+ / ULPI Select <i>Access: R_W</i> */ 552 USB3_USB2PHYCFG_UTMI_ULPI_BIT = 0x00000010, 553 USB3_USB2PHYCFG_UTMI_ULPI_SHIFT = 4, 554 555 /** Full-speed Serial Interface Select <i>Access: R_W</i> */ 556 USB3_USB2PHYCFG_FSINTF_BIT = 0x00000020, 557 USB3_USB2PHYCFG_FSINTF_SHIFT = 5, 558 559 /** Suspend USB2 Phy <i>Access: R_W</i> */ 560 USB3_USB2PHYCFG_SUS_PHY_BIT = 0x00000040, 561 USB3_USB2PHYCFG_SUS_PHY_SHIFT = 6, 562 563 /** USB2.0 HS PHY/USB1.1 FS Serial Xcvr Select <i>Access: R_W</i> */ 564 USB3_USB2PHYCFG_PHY_SEL_BIT = 0x00000080, 565 USB3_USB2PHYCFG_PHY_SEL_SHIFT = 7, 566 567 /** Enable UTMI Sleep <i>Access: R_W</i> */ 568 USB3_USB2PHYCFG_ENBL_SLP_M_BIT = 0x00000100, 569 USB3_USB2PHYCFG_ENBL_SLP_M_SHIFT = 8, 570 571 /** USB2.0 Turnaround Time <i>Access: R_W</i> */ 572 USB3_USB2PHYCFG_USB_TRD_TIM_BITS = 0x00003c00, 573 USB3_USB2PHYCFG_USB_TRD_TIM_SHIFT = 10, 574 575 /** PHY Low-power Clock Select <i>Access: R_W</i> */ 576 USB3_USB2PHYCFG_PHY_LPWR_CLK_SEL_BIT = 0x00004000, 577 USB3_USB2PHYCFG_PHY_LPWR_CLK_SEL_SHIFT = 14, 578 579 /** ULPI Auto Resume <i>Access: R_W</i> */ 580 USB3_USB2PHYCFG_ULPI_AUTO_RES_BIT = 0x00008000, 581 USB3_USB2PHYCFG_ULPI_AUTO_RES_SHIFT = 15, 582 583 /** ULPI Clock SuspendM <i>Access: R_W</i> */ 584 USB3_USB2PHYCFG_ULPI_CLK_SUS_M_BIT = 0x00010000, 585 USB3_USB2PHYCFG_ULPI_CLK_SUS_M_SHIFT = 16, 586 587 /** ULPI External Vbus Drive <i>Access: R_W</i> */ 588 USB3_USB2PHYCFG_ULPI_EXT_VBUS_DRV_BIT = 0x00020000, 589 USB3_USB2PHYCFG_ULPI_EXT_VBUS_DRV_SHIFT = 17, 590 591 /** ULPI External Vbus Indicator <i>Access: R_W</i> */ 592 USB3_USB2PHYCFG_ULPI_EXT_VBUS_IND_BIT = 0x00040000, 593 USB3_USB2PHYCFG_ULPI_EXT_VBUS_IND_SHIFT = 18, 594 595 /** PHY Interrupt Number <i>Access: R_W</i> */ 596 USB3_USB2PHYCFG_PHY_INTR_NUM_BITS = 0x01f80000, 597 USB3_USB2PHYCFG_PHY_INTR_NUM_SHIFT = 19, 598 599 /** OTG Interrupt Number <i>Access: R_W</i> */ 600 USB3_USB2PHYCFG_OTG_INTR_NUM_BITS = 0x7e000000, 601 USB3_USB2PHYCFG_OTG_INTR_NUM_SHIFT = 25, 602 603 /** PHY Soft Reset <i>Access: R_W</i> */ 604 USB3_USB2PHYCFG_PHY_SOFT_RST_BIT = 0x80000000, 605 USB3_USB2PHYCFG_PHY_SOFT_RST_SHIFT = 31, 606 } gusb2phycfg_data_t; 607 608 /** 609 * This enum represents the bit fields in the USB2 I2C Control 610 * Registers (GUSB2I2CCTLn). 611 */ 612 typedef enum gusb2i2cctl_data { 613 /** All bits are reserved */ 614 USB3_USB2I2C_RSVD_BITS = 0xffffffff, 615 USB3_USB2I2C_RSVD_SHIFT = 0, 616 } gusb2i2cctl_data_t; 617 618 /** 619 * This enum represents the bit fields in the USB2 Phy Vendor Control 620 * Registers (GUSB2PHYACCn). 621 */ 622 typedef enum gusb2phyacc_data { 623 /** Register Data <i>Access: R_W</i> */ 624 USB3_USB2PHY_REGDATA_BITS = 0x000000ff, 625 USB3_USB2PHY_REGDATA_SHIFT = 0, 626 627 /** UTMI+ Vendor Ctrl Register Address <i>Access: R_W</i> */ 628 USB3_USB2PHY_VCTRL_BITS = 0x0000ff00, 629 USB3_USB2PHY_VCTRL_SHIFT = 8, 630 /*--------*/ 631 /** ULPI Extended Register Address <i>Access: R_W</i> */ 632 USB3_USB2PHY_EXTREGADDR_BITS = 0x00003f00, 633 USB3_USB2PHY_EXTREGADDR_SHIFT = 8, 634 635 /** Register Address <i>Access: R_W</i> */ 636 USB3_USB2PHY_REGADDR_BITS = 0x003f0000, 637 USB3_USB2PHY_REGADDR_SHIFT = 16, 638 639 /** Register Write <i>Access: R_W</i> */ 640 USB3_USB2PHY_REGWR_BIT = 0x00400000, 641 USB3_USB2PHY_REGWR_SHIFT = 22, 642 643 /** VStatus Busy <i>Access: RO</i> */ 644 USB3_USB2PHY_VSTSBSY_BIT = 0x00800000, 645 USB3_USB2PHY_VSTSBSY_SHIFT = 23, 646 647 /** VStatus Done <i>Access: R_SS_SC</i> */ 648 USB3_USB2PHY_VSTSDONE_BIT = 0x01000000, 649 USB3_USB2PHY_VSTSDONE_SHIFT = 24, 650 651 /** New Register Request <i>Access: R_WS_SC</i> */ 652 USB3_USB2PHY_NEWREGREQ_BIT = 0x02000000, 653 USB3_USB2PHY_NEWREGREQ_SHIFT = 25, 654 655 /** Disable ULPI Drivers <i>Access: R_WS_SC</i> */ 656 USB3_USB2PHY_DIS_ULPI_DRVR_BIT = 0x04000000, 657 USB3_USB2PHY_DIS_ULPI_DRVR_SHIFT = 26, 658 } gusb2phyacc_data_t; 659 660 /** 661 * This enum represents the bit fields of the USB3 Pipe Control 662 * Registers (GUSB3PIPECTLn). 663 */ 664 typedef enum gusb3pipectl_data { 665 /** Elastic Buffer Mode <i>Access: R_W</i> */ 666 USB3_PIPECTL_ELAS_BUF_MODE_BIT = 0x00000001, 667 USB3_PIPECTL_ELAS_BUF_MODE_SHIFT = 0, 668 669 /** Tx De-Emphasis <i>Access: R_W</i> */ 670 USB3_PIPECTL_TX_DEMPH_BITS = 0x00000006, 671 USB3_PIPECTL_TX_DEMPH_SHIFT = 1, 672 673 /** Tx Margin <i>Access: R_W</i> */ 674 USB3_PIPECTL_TX_MARGIN_BITS = 0x00000038, 675 USB3_PIPECTL_TX_MARGIN_SHIFT = 3, 676 677 /** Tx Swing <i>Access: R_W</i> */ 678 USB3_PIPECTL_TX_SWING_BIT = 0x00000040, 679 USB3_PIPECTL_TX_SWING_SHIFT = 6, 680 681 /** Port Operation Direction <i>Access: R_W</i> */ 682 USB3_PIPECTL_PRT_OP_DIR_BITS = 0x00000180, 683 USB3_PIPECTL_PRT_OP_DIR_SHIFT = 7, 684 685 /** LFPS Filter <i>Access: R_W</i> */ 686 USB3_PIPECTL_LFPS_FILTER_BIT = 0x00000200, 687 USB3_PIPECTL_LFPS_FILTER_SHIFT = 9, 688 689 /** P3 Exit Signal In P2 <i>Access: R_W</i> */ 690 USB3_PIPECTL_P3_EX_SIG_P2_BIT = 0x00000400, 691 USB3_PIPECTL_P3_EX_SIG_P2_SHIFT = 10, 692 693 /** P3-P2 Transitions OK <i>Access: R_W</i> */ 694 USB3_PIPECTL_P3_P2_TRAN_OK_BIT = 0x00000800, 695 USB3_PIPECTL_P3_P2_TRAN_OK_SHIFT = 11, 696 697 /** LFPS P0 Align <i>Access: R_W</i> */ 698 USB3_PIPECTL_LFPS_P0_ALGN_BIT = 0x00001000, 699 USB3_PIPECTL_LFPS_P0_ALGN_SHIFT = 12, 700 701 /** Pipe Data Width <i>Access: R_W</i> */ 702 USB3_PIPECTL_DATA_WIDTH_BITS = 0x00018000, 703 USB3_PIPECTL_DATA_WIDTH_SHIFT = 15, 704 705 /** Suspend USB3 Phy <i>Access: R_W</i> */ 706 USB3_PIPECTL_SUS_PHY_BIT = 0x00020000, 707 USB3_PIPECTL_SUS_PHY_SHIFT = 17, 708 709 /** PHY Soft Reset <i>Access: R_W</i> */ 710 USB3_PIPECTL_PHY_SOFT_RST_BIT = 0x80000000, 711 USB3_PIPECTL_PHY_SOFT_RST_SHIFT = 31, 712 } gusb3pipectl_data_t; 713 714 /** 715 * This enum represents the bit fields in the FIFO Size Registers. 716 */ 717 typedef enum gfifosize_data { 718 /** Depth <i>Access: R_W</i> */ 719 USB3_FIFOSZ_DEPTH_BITS = 0x0000ffff, 720 USB3_FIFOSZ_DEPTH_SHIFT = 0, 721 722 /** Starting Address <i>Access: RO or R_W</i> */ 723 USB3_FIFOSZ_STARTADDR_BITS = 0xffff0000, 724 USB3_FIFOSZ_STARTADDR_SHIFT = 16, 725 } gfifosize_data_t; 726 727 /** 728 * This enum represents the bit fields of the Event Buffer Size 729 * Registers (GEVENTSIZn). 730 */ 731 typedef enum geventsiz_data { 732 /** Event Buffer Size <i>Access: R_W</i> */ 733 USB3_EVENTSIZ_SIZ_BITS = 0x0000ffff, 734 USB3_EVENTSIZ_SIZ_SHIFT = 0, 735 736 /** Event Interrupt Mask (1 == disable) <i>Access: R_W</i> */ 737 USB3_EVENTSIZ_INT_MSK_BIT = 0x80000000, 738 USB3_EVENTSIZ_INT_MSK_SHIFT = 31, 739 } geventsiz_data_t; 740 741 /** 742 * This enum represents the bit fields of the Event Buffer Count 743 * Registers (GEVENTCNTn). 744 */ 745 typedef enum geventcnt_data { 746 /** Event Count <i>Access: R_W</i> */ 747 USB3_EVENTCNT_CNT_BITS = 0x0000ffff, 748 USB3_EVENTCNT_CNT_SHIFT = 0, 749 } geventcnt_data_t; 750 751 /** 752 * This enum represents the bit fields of a generic Event Buffer entry. 753 */ 754 typedef enum gevent_data { 755 /** Non-Endpoint Specific Event flag */ 756 USB3_EVENT_NON_EP_BIT = 0x01, 757 USB3_EVENT_NON_EP_SHIFT = 0, 758 759 /** Non-Endpoint Specific Event Type */ 760 USB3_EVENT_INTTYPE_BITS = 0xfe, 761 USB3_EVENT_INTTYPE_SHIFT = 1, 762 763 /** Non-Endpoint Specific Event Type values */ 764 USB3_EVENT_DEV_INT = 0, /** @< */ 765 USB3_EVENT_OTG_INT = 1, /** @< */ 766 USB3_EVENT_CARKIT_INT = 3, /** @< */ 767 USB3_EVENT_I2C_INT = 4, 768 } gevent_data_t; 769 770 /** 771 * This enum represents the non-generic bit fields of an Event Buffer entry 772 * for Device Specific events (DEVT). 773 */ 774 typedef enum devt_data { 775 /** Device Specific Event Type */ 776 USB3_DEVT_BITS = 0x00000f00, 777 USB3_DEVT_SHIFT = 8, 778 779 /** Device Specific Event Type values */ 780 USB3_DEVT_DISCONN = 0, /** @< */ 781 USB3_DEVT_USBRESET = 1, /** @< */ 782 USB3_DEVT_CONNDONE = 2, /** @< */ 783 USB3_DEVT_ULST_CHNG = 3, /** @< */ 784 USB3_DEVT_WKUP = 4, /** @< */ 785 USB3_DEVT_HIBER_REQ = 5, /** @< */ 786 USB3_DEVT_EOPF = 6, /** @< */ 787 USB3_DEVT_SOF = 7, /** @< */ 788 USB3_DEVT_ERRATICERR = 9, /** @< */ 789 USB3_DEVT_CMD_CMPL = 10, /** @< */ 790 USB3_DEVT_OVERFLOW = 11, /** @< */ 791 USB3_DEVT_VNDR_DEV_TST_RCVD = 12, /** @< */ 792 USB3_DEVT_INACT_TIMEOUT_RCVD = 13, 793 794 /** Event Information */ 795 USB3_DEVT_EVT_INFO_BITS = 0xffff0000, 796 USB3_DEVT_EVT_INFO_SHIFT = 16, 797 798 /** USB/Link State */ 799 USB3_DEVT_ULST_STATE_BITS = 0x000f0000, 800 USB3_DEVT_ULST_STATE_SHIFT = 16, 801 802 /** USB/Link State values in SS */ 803 USB3_LINK_STATE_U0 = 0, /** @< */ 804 USB3_LINK_STATE_U1 = 1, /** @< */ 805 USB3_LINK_STATE_U2 = 2, /** @< */ 806 USB3_LINK_STATE_U3 = 3, /** @< */ 807 USB3_LINK_STATE_SS_DIS = 4, /** @< */ 808 USB3_LINK_STATE_RX_DET = 5, /** @< */ 809 USB3_LINK_STATE_SS_INACT = 6, /** @< */ 810 USB3_LINK_STATE_POLL = 7, /** @< */ 811 USB3_LINK_STATE_RECOV = 8, /** @< */ 812 USB3_LINK_STATE_HRESET = 9, /** @< */ 813 USB3_LINK_STATE_CMPLY = 10, /** @< */ 814 USB3_LINK_STATE_LPBK = 11, /** @< */ 815 USB3_LINK_STATE_RESET = 14, /** @< */ 816 USB3_LINK_STATE_RESUME = 15, 817 818 /** USB/Link State values in HS/FS/LS */ 819 USB3_LINK_STATE_ON = 0, /** @< */ 820 USB3_LINK_STATE_SLEEP = 2, /** @< */ 821 USB3_LINK_STATE_SUSPEND = 3, /** @< */ 822 USB3_LINK_STATE_EARLY_SUSPEND = 5, 823 824 USB3_DEVT_ULST_SS_BIT = 0x00100000, 825 USB3_DEVT_ULST_SS_SHIFT = 20, 826 827 #define USB3_DEVT_HIBER_STATE_BITS USB3_DEVT_ULST_STATE_BITS 828 #define USB3_DEVT_HIBER_STATE_SHIFT USB3_DEVT_ULST_STATE_SHIFT 829 830 #define USB3_DEVT_HIBER_SS_BIT USB3_DEVT_ULST_SS_BIT 831 #define USB3_DEVT_HIBER_SS_SHIFT USB3_DEVT_ULST_SS_SHIFT 832 833 USB3_DEVT_HIBER_HIRD_BITS = 0x0f000000, 834 USB3_DEVT_HIBER_HIRD_SHIFT = 24, 835 } devt_data_t; 836 837 /** 838 * This enum represents the bit fields of an Event Buffer entry for 839 * Endpoint Specific events (DEPEVT). 840 */ 841 typedef enum depevt_data { 842 /** Endpoint Number */ 843 USB3_DEPEVT_EPNUM_BITS = 0x0000003e, 844 USB3_DEPEVT_EPNUM_SHIFT = 1, 845 846 /** Endpoint Event Type */ 847 USB3_DEPEVT_INTTYPE_BITS = 0x000003c0, 848 USB3_DEPEVT_INTTYPE_SHIFT = 6, 849 850 /** Endpoint Event Type values */ 851 USB3_DEPEVT_XFER_CMPL = 1, /** @< */ 852 USB3_DEPEVT_XFER_IN_PROG = 2, /** @< */ 853 USB3_DEPEVT_XFER_NRDY = 3, /** @< */ 854 USB3_DEPEVT_FIFOXRUN = 4, /** @< */ 855 USB3_DEPEVT_STRM_EVT = 6, /** @< */ 856 USB3_DEPEVT_EPCMD_CMPL = 7, 857 858 /** Event Status for Start Xfer Command */ 859 USB3_DEPEVT_NO_MORE_RSCS_BIT = 0x00001000, 860 USB3_DEPEVT_NO_MORE_RSCS_SHIFT = 12, 861 USB3_DEPEVT_ISOC_TIME_PASSED_BIT = 0x00002000, 862 USB3_DEPEVT_ISOC_TIME_PASSED_SHIFT = 13, 863 864 /** Event Status for Stream Event */ 865 USB3_DEPEVT_STRM_EVT_BITS = 0x0000f000, 866 USB3_DEPEVT_STRM_EVT_SHIFT = 12, 867 868 /** Stream Event Status values */ 869 USB3_DEPEVT_STRM_FOUND = 1, /** @< */ 870 USB3_DEPEVT_STRM_NOT_FOUND = 2, 871 872 /** Event Status for Xfer Complete or Xfer In Progress Event */ 873 USB3_DEPEVT_BUS_ERR_BIT = 0x00001000, 874 USB3_DEPEVT_BUS_ERR_SHIFT = 12, 875 USB3_DEPEVT_SHORT_PKT_BIT = 0x00002000, 876 USB3_DEPEVT_SHORT_PKT_SHIFT = 13, 877 USB3_DEPEVT_IOC_BIT = 0x00004000, 878 USB3_DEPEVT_IOC_SHIFT = 14, 879 USB3_DEPEVT_LST_BIT = 0x00008000, 880 USB3_DEPEVT_LST_SHIFT = 15, 881 #define USB3_DEPEVT_MISSED_ISOC_BIT USB3_DEPEVT_LST_BIT 882 #define USB3_DEPEVT_MISSED_ISOC_SHIFT USB3_DEPEVT_LST_SHIFT 883 884 /** Event Status for Xfer Not Ready Event */ 885 USB3_DEPEVT_CTRL_BITS = 0x00003000, 886 USB3_DEPEVT_CTRL_SHIFT = 12, 887 USB3_DEPEVT_XFER_ACTIVE_BIT = 0x00008000, 888 USB3_DEPEVT_XFER_ACTIVE_SHIFT = 15, 889 890 /** Xfer Not Ready Event Status values */ 891 USB3_DEPEVT_CTRL_SETUP = 0, /** @< */ 892 USB3_DEPEVT_CTRL_DATA = 1, /** @< */ 893 USB3_DEPEVT_CTRL_STATUS = 2, 894 895 /** Stream ID */ 896 USB3_DEPEVT_STRM_ID_BITS = 0xffff0000, 897 USB3_DEPEVT_STRM_ID_SHIFT = 16, 898 899 /** Isoc uFrame Number (for Xfer Not Ready on Isoc EP) */ 900 USB3_DEPEVT_ISOC_UFRAME_NUM_BITS = 0xffff0000, 901 USB3_DEPEVT_ISOC_UFRAME_NUM_SHIFT = 16, 902 903 /** Xfer Resource Index (for Start Xfer Command) */ 904 USB3_DEPEVT_XFER_RSC_IDX_BITS = 0x007f0000, 905 USB3_DEPEVT_XFER_RSC_IDX_SHIFT = 16, 906 907 /** Current Data Sequence Number (for Get Endpoint State Command) */ 908 USB3_DEPEVT_CUR_DAT_SEQ_NUM_BITS = 0x001f0000, 909 USB3_DEPEVT_CUR_DAT_SEQ_NUM_SHIFT = 16, 910 911 /** Flow Control State (for Get Endpoint State Command) */ 912 USB3_DEPEVT_FLOW_CTRL_BIT = 0x00200000, 913 USB3_DEPEVT_FLOW_CTRL_SHIFT = 21, 914 } depevt_data_t; 915 916 /** 917 * This enum represents the non-generic bit fields of an Event Buffer entry 918 * for other Core events (GEVT). 919 */ 920 typedef enum gevt_data { 921 /** PHY Port Number */ 922 USB3_GINT_PHY_PORT_BITS = 0xf00, 923 USB3_GINT_PHY_PORT_SHIFT = 8, 924 } gevt_data_t; 925 926 /** 927 * This struct represents the 32-bit register fields of the Event Buffer 928 * Registers (GEVENTBUFn). 929 */ 930 typedef struct geventbuf_data { 931 /** Event Buffer Address Register Low Word */ 932 volatile uint32_t geventadr_lo; 933 934 /** Event Buffer Address Register High Word */ 935 volatile uint32_t geventadr_hi; 936 937 /** Event Buffer Size Register. 938 * Fields defined in enum @ref geventsiz_data. */ 939 volatile uint32_t geventsiz; 940 941 /** Event Buffer Count Register. 942 * Fields defined in enum @ref geventcnt_data. */ 943 volatile uint32_t geventcnt; 944 } geventbuf_data_t; 945 946 #define USB3_CORE_REG_BASE 0xC000 947 948 /** 949 * Core Global Registers <i>Offsets 100h-5FCh</i>. 950 * 951 * The dwc_usb3_core_global_regs structure defines the size 952 * and relative field offsets for the Core Global Registers. 953 */ 954 typedef struct usb3_core_global_regs { 955 956 #define USB3_CORE_GLOBAL_REG_OFFSET 0x100 957 958 /** Core BIU Configuration 0 Register <i>Offset: 100h</i>. 959 * Fields defined in enum @ref gsbuscfg0_data. */ 960 volatile uint32_t gsbuscfg0; 961 962 /** Core BIU Configuration 1 Register <i>Offset: 104h</i>. 963 * Fields defined in enum @ref gsbuscfg1_data. */ 964 volatile uint32_t gsbuscfg1; 965 966 /** Core Tx Threshold Control Register <i>Offset: 108h</i>. 967 * Fields defined in enum @ref gtxthrcfg_data. */ 968 volatile uint32_t gtxthrcfg; 969 970 /** Core Threshold Control Register <i>Offset: 10Ch</i>. 971 * Fields defined in enum @ref grxthrcfg_data. */ 972 volatile uint32_t grxthrcfg; 973 974 /** Core Control Register <i>Offset: 110h</i>. 975 * Fields defined in enum @ref gctl_data. */ 976 volatile uint32_t gctl; 977 978 /** Core Interrupt Mask Register <i>Offset: 114h</i>. 979 * Fields defined in enum @ref gevten_data. */ 980 volatile uint32_t gevten; 981 982 /** Core Status Register <i>Offset: 118h</i>. 983 * Fields defined in enum @ref gsts_data. */ 984 volatile uint32_t gsts; 985 986 /** reserved <i>Offset: 11Ch</i> */ 987 volatile uint32_t reserved0; 988 989 #define USB3_CORE_GSNPSID_REG_OFFSET 0x120 990 991 /** Synopsys ID Register <i>Offset: 120h</i> */ 992 volatile uint32_t gsnpsid; 993 994 /** General Purpose I/O Register <i>Offset: 124h</i> */ 995 volatile uint32_t ggpio; 996 997 /** User ID Register <i>Offset: 128h</i> */ 998 volatile uint32_t guid; 999 1000 /** reserved <i>Offset: 12Ch</i> */ 1001 volatile uint32_t reserved1; 1002 1003 /** Bus Error Address Register <i>Offset: 130h</i> */ 1004 volatile uint32_t gbuserraddrlo; 1005 1006 /** Bus Error Address Register <i>Offset: 134h</i> */ 1007 volatile uint32_t gbuserraddrhi; 1008 1009 /** reserved <i>Offset: 138h-13Ch</i> */ 1010 volatile uint32_t reserved2[2]; 1011 1012 /** Hardware Parameter 0 Register <i>Offset: 140h</i>. 1013 * Fields defined in enum @ref ghwparams0_data. */ 1014 volatile uint32_t ghwparams0; 1015 1016 /** Hardware Parameter 1 Register <i>Offset: 144h</i>. 1017 * Fields defined in enum @ref ghwparams1_data. */ 1018 volatile uint32_t ghwparams1; 1019 1020 /** Hardware Parameter 2 Register <i>Offset: 148h</i>. 1021 * Fields defined in enum @ref ghwparams2_data. */ 1022 volatile uint32_t ghwparams2; 1023 1024 /** Hardware Parameter 3 Register <i>Offset: 14Ch</i>. 1025 * Fields defined in enum @ref ghwparams3_data. */ 1026 volatile uint32_t ghwparams3; 1027 1028 /** Hardware Parameter 4 Register <i>Offset: 150h</i>. 1029 * Fields defined in enum @ref ghwparams4_data. */ 1030 volatile uint32_t ghwparams4; 1031 1032 /** Hardware Parameter 5 Register <i>Offset: 154h</i>. 1033 * Fields defined in enum @ref ghwparams5_data. */ 1034 volatile uint32_t ghwparams5; 1035 1036 /** Hardware Parameter 6 Register <i>Offset: 158h</i>. 1037 * Fields defined in enum @ref ghwparams6_data. */ 1038 volatile uint32_t ghwparams6; 1039 1040 /** Hardware Parameter 7 Register <i>Offset: 15Ch</i>. 1041 * Fields defined in enum @ref ghwparams7_data. */ 1042 volatile uint32_t ghwparams7; 1043 1044 /** Debug Queue/FIFO Space Register <i>Offset: 160h</i>. 1045 * Fields defined in enum @ref gdbgfifospace_data. */ 1046 volatile uint32_t gdbgfifospace; 1047 1048 /** Debug LTSSM Register <i>Offset: 164h</i>. 1049 * Fields defined in enum @ref gdbgltssm_data */ 1050 volatile uint32_t gdbgltssm; 1051 1052 /** reserved <i>Offset: 168h-1FCh</i> */ 1053 volatile uint32_t reserved3[38]; 1054 1055 /** USB2 Configuration Registers <i>Offset: 200h-23Ch</i>. 1056 * Fields defined in enum @ref gusb2phycfg_data. */ 1057 volatile uint32_t gusb2phycfg[16]; 1058 1059 /** USB2 I2C Access Registers <i>Offset: 240h-27Ch</i>. 1060 * Fields defined in enum @ref gusb2i2cctl_data. */ 1061 volatile uint32_t gusb2i2cctl[16]; 1062 1063 /** USB2 PHY Vendor Control Registers <i>Offset: 280h-2BCh</i>. 1064 * Fields defined in enum @ref gusb2phyacc_data. */ 1065 volatile uint32_t gusb2phyacc[16]; 1066 1067 /** USB3 Pipe Control Registers <i>Offset: 2C0h-2FCh</i>. 1068 * Fields defined in enum @ref gusb3pipectl_data. */ 1069 volatile uint32_t gusb3pipectl[16]; 1070 1071 /** Transmit FIFO Size Registers <i>Offset: 300h-37Ch</i>. 1072 * Fields defined in enum @ref gfifosize_data. */ 1073 volatile uint32_t gtxfifosiz[32]; 1074 1075 /** Receive FIFO Size Registers <i>Offset: 380h-3FC0h</i>. 1076 * Fields defined in enum @ref gfifosize_data. */ 1077 volatile uint32_t grxfifosiz[32]; 1078 1079 /** Event Buffer Registers <i>Offset: 400h-5FCh</i>. 1080 * Fields defined in struct @ref geventbuf_data. */ 1081 struct geventbuf_data geventbuf[32]; 1082 1083 /** Hardware Parameter 8 Register <i>Offset: 600h</i>. 1084 * Fields defined in enum @ref ghwparams8_data. */ 1085 volatile uint32_t ghwparams8; 1086 } usb3_core_global_regs_t; 1087 1088 1089 /****************************************************************************/ 1090 /* Device Global Registers */ 1091 1092 /** 1093 * This enum represents the bit fields in the Device Configuration 1094 * Register (DCFG). 1095 */ 1096 typedef enum dcfg_data { 1097 /** Device Speed <i>Access: R_W</i> */ 1098 USB3_DCFG_DEVSPD_BITS = 0x000007, 1099 USB3_DCFG_DEVSPD_SHIFT = 0, 1100 1101 /** Device Speed values */ 1102 USB3_SPEED_HS_PHY_30MHZ_OR_60MHZ = 0, /** @< */ 1103 USB3_SPEED_FS_PHY_30MHZ_OR_60MHZ = 1, /** @< */ 1104 USB3_SPEED_LS_PHY_6MHZ = 2, /** @< */ 1105 USB3_SPEED_FS_PHY_48MHZ = 3, /** @< */ 1106 USB3_SPEED_SS_PHY_125MHZ_OR_250MHZ = 4, 1107 1108 /** Device Address <i>Access: R_W</i> */ 1109 USB3_DCFG_DEVADDR_BITS = 0x0003f8, 1110 USB3_DCFG_DEVADDR_SHIFT = 3, 1111 1112 /** Periodic Frame Interval <i>Access: R_W</i> */ 1113 USB3_DCFG_PER_FR_INTVL_BITS = 0x000c00, 1114 USB3_DCFG_PER_FR_INTVL_SHIFT = 10, 1115 1116 /** Periodic Frame Interval values */ 1117 USB3_DCFG_PER_FR_INTVL_80 = 0, /** @< */ 1118 USB3_DCFG_PER_FR_INTVL_85 = 1, /** @< */ 1119 USB3_DCFG_PER_FR_INTVL_90 = 2, /** @< */ 1120 USB3_DCFG_PER_FR_INTVL_95 = 3, 1121 1122 /** Device Interrupt Number <i>Access: R_W</i> */ 1123 USB3_DCFG_DEV_INTR_NUM_BITS = 0x01f000, 1124 USB3_DCFG_DEV_INTR_NUM_SHIFT = 12, 1125 1126 /** Number of Receive Buffers <i>Access: R_W</i> */ 1127 USB3_DCFG_NUM_RCV_BUF_BITS = 0x3e0000, 1128 USB3_DCFG_NUM_RCV_BUF_SHIFT = 17, 1129 1130 /** LPM Capable <i>Access: R_W</i> */ 1131 USB3_DCFG_LPM_CAP_BIT = 0x400000, 1132 USB3_DCFG_LPM_CAP_SHIFT = 22, 1133 } dcfg_data_t; 1134 1135 /** 1136 * This enum represents the bit fields in the Device Control 1137 * Register (DCTL). 1138 */ 1139 typedef enum dctl_data { 1140 /** Soft Disconnect <i>Access: R_W</i> */ 1141 USB3_DCTL_SFT_DISCONN_BIT = 0x00000001, 1142 USB3_DCTL_SFT_DISCONN_SHIFT = 0, 1143 1144 /** Test Control <i>Access: R_W</i> */ 1145 USB3_DCTL_TSTCTL_BITS = 0x0000001e, 1146 USB3_DCTL_TSTCTL_SHIFT = 1, 1147 1148 /** USB/Link State Change Request <i>Access: R_W</i> */ 1149 USB3_DCTL_ULST_CHNG_REQ_BITS = 0x000001e0, 1150 USB3_DCTL_ULST_CHNG_REQ_SHIFT = 5, 1151 1152 /** Requested Link State Transition/Action In SS Mode */ 1153 USB3_LINK_STATE_REQ_NO_ACTION = 0, 1154 USB3_LINK_STATE_REQ_SS_DISABLED = 4, 1155 USB3_LINK_STATE_REQ_RX_DETECT = 5, 1156 USB3_LINK_STATE_REQ_INACTIVE = 6, 1157 USB3_LINK_STATE_REQ_RECOVERY = 8, 1158 USB3_LINK_STATE_REQ_COMPLIANCE = 10, 1159 USB3_LINK_STATE_REQ_LOOPBACK = 11, 1160 USB3_LINK_STATE_REQ_HOST_MODE_ONLY = 15, 1161 1162 /** Requested Link State Transition/Action In HS/FS/LS Mode */ 1163 USB3_LINK_STATE_REQ_REMOTE_WAKEUP = 8, 1164 1165 /** U1/U2 control <i>Access: R_W</i> */ 1166 USB3_DCTL_ACCEPT_U1_EN_BIT = 0x00000200, 1167 USB3_DCTL_ACCEPT_U1_EN_SHIFT = 9, 1168 USB3_DCTL_INIT_U1_EN_BIT = 0x00000400, 1169 USB3_DCTL_INIT_U1_EN_SHIFT = 10, 1170 USB3_DCTL_ACCEPT_U2_EN_BIT = 0x00000800, 1171 USB3_DCTL_ACCEPT_U2_EN_SHIFT = 11, 1172 USB3_DCTL_INIT_U2_EN_BIT = 0x00001000, 1173 USB3_DCTL_INIT_U2_EN_SHIFT = 12, 1174 1175 /** Controller Save State <i>Access: R_W</i> */ 1176 USB3_DCTL_CSS_BIT = 0x00010000, 1177 USB3_DCTL_CSS_SHIFT = 16, 1178 1179 /** Controller Restore State <i>Access: R_W</i> */ 1180 USB3_DCTL_CRS_BIT = 0x00020000, 1181 USB3_DCTL_CRS_SHIFT = 17, 1182 1183 /** L1 Hibernation Enable <i>Access: R_W</i> */ 1184 USB3_DCTL_L1_HIBER_EN_BIT = 0x00040000, 1185 USB3_DCTL_L1_HIBER_EN_RES_SHIFT = 18, 1186 1187 /** Keep Connect (for hibernation) <i>Access: R_W</i> */ 1188 USB3_DCTL_KEEP_CONNECT_BIT = 0x00080000, 1189 USB3_DCTL_KEEP_CONNECT_SHIFT = 19, 1190 1191 /** LPM Response <i>Access: R_W</i> */ 1192 USB3_DCTL_APP_L1_RES_BIT = 0x00800000, 1193 USB3_DCTL_APP_L1_RES_SHIFT = 23, 1194 1195 /* HIRD Threshold <i>Access: R_W</i> */ 1196 USB3_DCTL_HIRD_THR_BITS = 0x1f000000, 1197 USB3_DCTL_HIRD_THR_SHIFT = 24, 1198 1199 /** Light Soft Reset <i>Access: R_W</i> */ 1200 USB3_DCTL_LSFT_RST_BIT = 0x20000000, 1201 USB3_DCTL_LSFT_RST_SHIFT = 29, 1202 1203 /** Core Soft Reset <i>Access: R_W</i> */ 1204 USB3_DCTL_CSFT_RST_BIT = 0x40000000, 1205 USB3_DCTL_CSFT_RST_SHIFT = 30, 1206 1207 /** Run/Stop <i>Access: R_W</i> */ 1208 USB3_DCTL_RUN_STOP_BIT = 0x80000000, 1209 USB3_DCTL_RUN_STOP_SHIFT = 31, 1210 } dctl_data_t; 1211 1212 /** 1213 * This enum represents the bit fields of the Device Event Enable 1214 * Register (DEVTEN). 1215 */ 1216 typedef enum devten_data { 1217 /** Disconnect Detected Event Enable <i>Access: R_W</i> */ 1218 USB3_DEVTEN_DISCONN_BIT = 0x0001, 1219 USB3_DEVTEN_DISCONN_SHIFT = 0, 1220 1221 /** USB Reset Enable <i>Access: R_W</i> */ 1222 USB3_DEVTEN_USBRESET_BIT = 0x0002, 1223 USB3_DEVTEN_USBRESET_SHIFT = 1, 1224 1225 /** Connect Done Enable <i>Access: R_W</i> */ 1226 USB3_DEVTEN_CONNDONE_BIT = 0x0004, 1227 USB3_DEVTEN_CONNDONE_SHIFT = 2, 1228 1229 /** USB/Link State Change Event Enable <i>Access: R_W</i> */ 1230 USB3_DEVTEN_ULST_CHNG_BIT = 0x0008, 1231 USB3_DEVTEN_ULST_CHNG_SHIFT = 3, 1232 1233 /** Resume/Remote-Wakeup Event Enable <i>Access: R_W</i> */ 1234 USB3_DEVTEN_WKUP_BIT = 0x0010, 1235 USB3_DEVTEN_WKUP_SHIFT = 4, 1236 1237 /** Hibernation Request Event Enable <i>Access: R_W</i> */ 1238 USB3_DEVTEN_HIBER_REQ_EVT_BIT = 0x0020, 1239 USB3_DEVTEN_HIBER_REQ_EVT_SHIFT = 5, 1240 1241 /** End of Periodic Frame Event Enable <i>Access: R_W</i> */ 1242 USB3_DEVTEN_EOPF_BIT = 0x0040, 1243 USB3_DEVTEN_EOPF_SHIFT = 6, 1244 1245 /** Start of (Micro)Frame Enable <i>Access: R_W</i> */ 1246 USB3_DEVTEN_SOF_BIT = 0x0080, 1247 USB3_DEVTEN_SOF_SHIFT = 7, 1248 1249 /** Erratic Error Event Enable <i>Access: R_W</i> */ 1250 USB3_DEVTEN_ERRATICERR_BIT = 0x0200, 1251 USB3_DEVTEN_ERRATICERR_SHIFT = 9, 1252 1253 /** U2 Inactivity Timeout Enable <i>Access: R_W</i> */ 1254 USB3_DEVTEN_INACT_TIMEOUT_BIT = 0x2000, 1255 USB3_DEVTEN_INACT_TIMEOUT_SHIFT = 13, 1256 } devten_data_t; 1257 1258 /** 1259 * This enum represents the bit fields in the Device Status 1260 * Register (DSTS). 1261 */ 1262 typedef enum dsts_data { 1263 /** Connected Speed <i>Access: RO</i>. 1264 * (see enum @ref dcfg_data for values) */ 1265 USB3_DSTS_CONNSPD_BITS = 0x00000007, 1266 USB3_DSTS_CONNSPD_SHIFT = 0, 1267 1268 /** (Micro)Frame Number of Received SOF <i>Access: RO</i> */ 1269 USB3_DSTS_SOF_FN_BITS = 0x0001fff8, 1270 USB3_DSTS_SOF_FN_SHIFT = 3, 1271 1272 /** RX Fifo Empty <i>Access: RO</i> */ 1273 USB3_DSTS_RXFIFO_EMPTY_BIT = 0x00020000, 1274 USB3_DSTS_RXFIFO_EMPTY_SHIFT = 17, 1275 1276 /** USB/Link State <i>Access: RO</i> */ 1277 USB3_DSTS_USBLNK_STATE_BITS = 0x003c0000, 1278 USB3_DSTS_USBLNK_STATE_SHIFT = 18, 1279 1280 /** USB/Link State values same as for devt_data_t */ 1281 1282 /** Device Controller Halted <i>Access: RO</i> */ 1283 USB3_DSTS_DEV_CTRL_HLT_BIT = 0x00400000, 1284 USB3_DSTS_DEV_CTRL_HLT_SHIFT = 22, 1285 1286 /** Core Idle <i>Access: RO</i> */ 1287 USB3_DSTS_CORE_IDLE_BIT = 0x00800000, 1288 USB3_DSTS_CORE_IDLE_SHIFT = 23, 1289 1290 /** Save State Status <i>Access: RO</i> */ 1291 USB3_DSTS_SSS_BIT = 0x01000000, 1292 USB3_DSTS_SSS_SHIFT = 24, 1293 1294 /** Restore State Status <i>Access: RO</i> */ 1295 USB3_DSTS_RSS_BIT = 0x02000000, 1296 USB3_DSTS_RSS_SHIFT = 25, 1297 1298 /** Save/Restore Error <i>Access: RO</i> */ 1299 USB3_DSTS_SRE_BIT = 0x10000000, 1300 USB3_DSTS_SRE_SHIFT = 28, 1301 1302 /** Link-state Not Ready <i>Access: RO</i> */ 1303 USB3_DSTS_LNR_BIT = 0x20000000, 1304 USB3_DSTS_LNR_SHIFT = 29, 1305 } dsts_data_t; 1306 1307 /** 1308 * This enum represents the bit fields in the Device Generic Command Parameter 1309 * Register (DGCMDPARn) for the various commands. 1310 */ 1311 typedef enum dgcmdpar_data { 1312 /** Force Link PM Accept 1313 * (for USB3_DGCMD_XMIT_SET_LINK_FUNC_LMP command) */ 1314 USB3_DGCMDPAR_FORCE_LINK_PM_ACCEPT_BIT = 0x0001, 1315 USB3_DGCMDPAR_FORCE_LINK_PM_ACCEPT_SHIFT = 0, 1316 1317 /** Vendor Specific Test Select 1318 * (for USB3_DGCMD_XMIT_VEND_DEV_TST_LMP command) */ 1319 USB3_DGCMDPAR_VEND_SPEC_TST_BITS = 0x00ff, 1320 USB3_DGCMDPAR_VEND_SPEC_TST_SHIFT = 0, 1321 1322 /** Interface Number (for USB3_DGCMD_XMIT_RMT_WKUP_SIG command) */ 1323 USB3_DGCMDPAR_INTF_NUM_BITS = 0x00ff, 1324 USB3_DGCMDPAR_INTF_NUM_SHIFT = 0, 1325 1326 /** Best Effort Latency Tolerance Value 1327 * (for USB3_DGCMD_XMIT_LAT_TOL_MSG command) */ 1328 USB3_DGCMDPAR_BELT_VALUE_BITS = 0x03ff, 1329 USB3_DGCMDPAR_BELT_VALUE_SHIFT = 0, 1330 1331 /** Best Effort Latency Tolerance Scale 1332 * (for USB3_DGCMD_XMIT_LAT_TOL_MSG command) */ 1333 USB3_DGCMDPAR_BELT_SCALE_BITS = 0x0c00, 1334 USB3_DGCMDPAR_BELT_SCALE_SHIFT = 10, 1335 1336 /** Latency Scale values (ns) */ 1337 USB3_LATENCY_VALUE_MULT_1024 = 1, /** @< */ 1338 USB3_LATENCY_VALUE_MULT_32768 = 2, /** @< */ 1339 USB3_LATENCY_VALUE_MULT_1048576 = 3, 1340 1341 /** Bus Interval Adjustment 1342 * (for USB3_DGCMD_XMIT_BUS_INTVL_ADJ_MSG command) */ 1343 USB3_DGCMDPAR_BUS_INTVL_ADJ_BITS = 0xffff, 1344 USB3_DGCMDPAR_BUS_INTVL_ADJ_SHIFT = 0, 1345 1346 /** Bus Interval Adjustment values (units) */ 1347 USB3_BUS_INTVL_ADJ_DEC_1 = 0xffff, /** @< */ 1348 USB3_BUS_INTVL_ADJ_DEC_32768 = 0x8000, /** @< */ 1349 USB3_BUS_INTVL_ADJ_INC_32767 = 0x7fff, /** @< */ 1350 USB3_BUS_INTVL_ADJ_NO_CHNG = 0x0000, 1351 1352 USB3_DGCMDPAR_HOST_ROLE_REQ_INITIATE = 0x01, 1353 USB3_DGCMDPAR_HOST_ROLE_REQ_CONFIRM = 0x02, 1354 } dgcmdpar_data_t; 1355 1356 /** 1357 * This enum represents the bit fields in the Device Generic Command 1358 * Register (DGCMDn). 1359 */ 1360 typedef enum dgcmd_data { 1361 /** Command Type <i>Access: R_W</i> */ 1362 USB3_DGCMD_TYP_BITS = 0x0ff, 1363 USB3_DGCMD_TYP_SHIFT = 0, 1364 1365 /** Command Type values */ 1366 USB3_DGCMD_XMIT_SET_LINK_FUNC_LMP = 1, /** @< */ 1367 USB3_DGCMD_SET_PERIODIC_PARAMS = 2, /** @< */ 1368 USB3_DGCMD_XMIT_FUNC_WAKE_DEV_NOTIF = 3, /** @< */ 1369 USB3_DGCMD_SET_SCRATCHPAD_ARRAY_ADR_LO = 4, /** @< */ 1370 USB3_DGCMD_SET_SCRATCHPAD_ARRAY_ADR_HI = 5, /** @< */ 1371 USB3_DGCMD_XMIT_HOST_ROLE_REQUEST = 6, /** @< */ 1372 USB3_DGCMD_SET_EP_NRDY = 12, /** @< */ 1373 USB3_DGCMD_RUN_SOC_BUS_LOOPBK_TST = 16, /** @< */ 1374 1375 /** Command Interrupt on Complete <i>Access: R_W</i> */ 1376 USB3_DGCMD_IOC_BIT = 0x100, 1377 USB3_DGCMD_IOC_SHIFT = 8, 1378 1379 /** Command Active <i>Access: R_W</i> */ 1380 USB3_DGCMD_ACT_BIT = 0x400, 1381 USB3_DGCMD_ACT_SHIFT = 10, 1382 1383 /** Command Status <i>Access: R_W</i> */ 1384 USB3_DGCMD_STS_BITS = 0xf000, 1385 USB3_DGCMD_STS_SHIFT = 12, 1386 1387 /** Command Status values */ 1388 USB3_DGCMD_STS_ERROR = 15, 1389 } dgcmd_data_t; 1390 1391 /** 1392 * This enum represents the bit fields in the Device Endpoint Mapping 1393 * Registers (DEPMAPn). 1394 */ 1395 typedef enum depmap_data { 1396 /** Resource Number <i>Access: R_W / RO</i> */ 1397 USB3_EPMAP_RES_NUM_BITS = 0x1f, 1398 USB3_EPMAP_RES_NUM_SHIFT = 0, 1399 } depmap_data_t; 1400 1401 /** 1402 * Device Global Registers <i>Offsets 700h-7FCh</i>. 1403 * 1404 * The following structures define the size and relative field offsets 1405 * for the Device Mode Global Registers. 1406 */ 1407 typedef struct usb3_dev_global_regs { 1408 1409 #define USB3_DEV_GLOBAL_REG_OFFSET 0x700 1410 1411 /** Device Configuration Register <i>Offset: 700h</i>. 1412 * Fields defined in enum @ref dcfg_data. */ 1413 volatile uint32_t dcfg; 1414 1415 /** Device Control Register <i>Offset: 704h</i>. 1416 * Fields defined in enum @ref dctl_data. */ 1417 volatile uint32_t dctl; 1418 1419 /** Device All Endpoints Interrupt Mask Register <i>Offset: 708h</i>. 1420 * Fields defined in enum @ref devten_data. */ 1421 volatile uint32_t devten; 1422 1423 /** Device Status Register <i>Offset: 70Ch</i>. 1424 * Fields defined in enum @ref dsts_data. */ 1425 volatile uint32_t dsts; 1426 1427 /** Device Generic Command Parameter Register <i>Offset: 710h</i>. 1428 * Fields defined in enum @ref dgcmdpar_data. */ 1429 volatile uint32_t dgcmdpar; 1430 1431 /** Device Generic Command Register <i>Offset: 714h</i>. 1432 * Fields defined in enum @ref dgcmd_data. */ 1433 volatile uint32_t dgcmd; 1434 1435 /** reserved <i>Offset: 718h-71Ch</i> */ 1436 volatile uint32_t reserved[2]; 1437 1438 /** Device Active Logical Endpoint Enable Register <i>Offset: 720h</i>. 1439 * One bit per logical endpoint, bit0=EP0 ... bit31=EP31. */ 1440 volatile uint32_t dalepena; 1441 } usb3_dev_global_regs_t; 1442 1443 1444 /****************************************************************************/ 1445 /* Device Endpoint Specific Registers */ 1446 1447 /** 1448 * This enum represents the bit fields in the Device Endpoint Command 1449 * Parameter 1 Register (DEPCMDPAR1n) for the Set Endpoint Configuration 1450 * (DEPCFG) command. 1451 */ 1452 typedef enum depcfgpar1_data { 1453 /** Interrupt number */ 1454 USB3_EPCFG1_INTRNUM_BITS = 0x0000003f, 1455 USB3_EPCFG1_INTRNUM_SHIFT = 0, 1456 1457 /** Stream Completed */ 1458 USB3_EPCFG1_XFER_CMPL_BIT = 0x00000100, 1459 USB3_EPCFG1_XFER_CMPL_SHIFT = 8, 1460 1461 /** Stream In Progress */ 1462 USB3_EPCFG1_XFER_IN_PROG_BIT = 0x00000200, 1463 USB3_EPCFG1_XFER_IN_PROG_SHIFT = 9, 1464 1465 /** Stream Not Ready */ 1466 USB3_EPCFG1_XFER_NRDY_BIT = 0x00000400, 1467 USB3_EPCFG1_XFER_NRDY_SHIFT = 10, 1468 1469 /** Rx FIFO Underrun / Tx FIFO Overrun */ 1470 USB3_EPCFG1_FIFOXRUN_BIT = 0x00000800, 1471 USB3_EPCFG1_FIFOXRUN_SHIFT = 11, 1472 1473 /** Back-to-Back Setup Packets Received */ 1474 USB3_EPCFG1_SETUP_PNDG_BIT = 0x00001000, 1475 USB3_EPCFG1_SETUP_PNDG_SHIFT = 12, 1476 1477 /** Endpoint Command Complete */ 1478 USB3_EPCFG1_EPCMD_CMPL_BIT = 0x00002000, 1479 USB3_EPCFG1_EPCMD_CMPL_SHIFT = 13, 1480 1481 /** Endpoint bInterval */ 1482 USB3_EPCFG1_BINTERVAL_BITS = 0x00ff0000, 1483 USB3_EPCFG1_BINTERVAL_SHIFT = 16, 1484 1485 /** Endpoint Stream Capability */ 1486 USB3_EPCFG1_STRM_CAP_BIT = 0x01000000, 1487 USB3_EPCFG1_STRM_CAP_SHIFT = 24, 1488 1489 /** Endpoint Direction */ 1490 USB3_EPCFG1_EP_DIR_BIT = 0x02000000, 1491 USB3_EPCFG1_EP_DIR_SHIFT = 25, 1492 1493 /** Endpoint Number */ 1494 USB3_EPCFG1_EP_NUM_BITS = 0x3c000000, 1495 USB3_EPCFG1_EP_NUM_SHIFT = 26, 1496 } depcfgpar1_data_t; 1497 1498 /** 1499 * This enum represents the bit fields in the Device Endpoint Command 1500 * Parameter 0 Register (DEPCMDPAR0n) for the Set Endpoint Configuration 1501 * (DWC_EPCMD_SET_EP_CFG) command. 1502 */ 1503 typedef enum depcfgpar0_data { 1504 /** Endpoint Type <i>Access: R_W</i> */ 1505 USB3_EPCFG0_EPTYPE_BITS = 0x00000006, 1506 USB3_EPCFG0_EPTYPE_SHIFT = 1, 1507 1508 /** Endpoint Type values */ 1509 USB3_EP_TYPE_CONTROL = 0, /** @< */ 1510 USB3_EP_TYPE_ISOC = 1, /** @< */ 1511 USB3_EP_TYPE_BULK = 2, /** @< */ 1512 USB3_EP_TYPE_INTR = 3, 1513 1514 /** Maximum Packet Size <i>Access: R_W</i> */ 1515 USB3_EPCFG0_MPS_BITS = 0x00003ff8, 1516 USB3_EPCFG0_MPS_SHIFT = 3, 1517 1518 /** Flow Control State <i>Access: R_W</i> */ 1519 USB3_EPCFG0_FLOW_CTRL_STATE_BIT = 0x00010000, 1520 USB3_EPCFG0_FLOW_CTRL_STATE_SHIFT = 16, 1521 1522 /** Tx Fifo Number (IN endpoints only) <i>Access: R_W</i> */ 1523 USB3_EPCFG0_TXFNUM_BITS = 0x003e0000, 1524 USB3_EPCFG0_TXFNUM_SHIFT = 17, 1525 1526 /** Burst Size <i>Access: R_W</i> */ 1527 USB3_EPCFG0_BRSTSIZ_BITS = 0x03c00000, 1528 USB3_EPCFG0_BRSTSIZ_SHIFT = 22, 1529 1530 /** Data Sequence Num (old) <i>Access: R_W</i> */ 1531 USB3_EPCFG0_DSNUM_BITS = 0x7c000000, 1532 USB3_EPCFG0_DSNUM_SHIFT = 26, 1533 1534 /** Ignore Data Sequence Num (old) <i>Access: R_W</i> */ 1535 USB3_EPCFG0_IGN_DSNUM_BIT = 0x80000000, 1536 USB3_EPCFG0_IGN_DSNUM_SHIFT = 31, 1537 1538 /** Config Action (new) <i>Access: R_W</i> */ 1539 USB3_EPCFG0_CFG_ACTION_BITS = 0xc0000000, 1540 USB3_EPCFG0_CFG_ACTION_SHIFT = 30, 1541 1542 /** Config Action values (new) */ 1543 USB3_CFG_ACTION_INIT = 0, /** @< */ 1544 USB3_CFG_ACTION_RESTORE = 1, /** @< */ 1545 USB3_CFG_ACTION_MODIFY = 2, 1546 } depcfgpar0_data_t; 1547 1548 /** 1549 * This enum represents the bit fields in the Device Endpoint Command 1550 * Register (DEPCMDn). 1551 */ 1552 typedef enum depcmd_data { 1553 /** Command Type <i>Access: R_W</i> */ 1554 USB3_EPCMD_TYP_BITS = 0x0ff, 1555 USB3_EPCMD_TYP_SHIFT = 0, 1556 1557 /** Command Type values */ 1558 USB3_EPCMD_SET_EP_CFG = 1, /** @< */ 1559 USB3_EPCMD_SET_XFER_CFG = 2, /** @< */ 1560 USB3_EPCMD_GET_EP_STATE = 3, /** @< */ 1561 USB3_EPCMD_SET_STALL = 4, /** @< */ 1562 USB3_EPCMD_CLR_STALL = 5, /** @< */ 1563 USB3_EPCMD_START_XFER = 6, /** @< */ 1564 USB3_EPCMD_UPDATE_XFER = 7, /** @< */ 1565 USB3_EPCMD_END_XFER = 8, /** @< */ 1566 USB3_EPCMD_START_NEW_CFG = 9, 1567 1568 /** Command Interrupt on Complete <i>Access: R_W</i> */ 1569 USB3_EPCMD_IOC_BIT = 0x100, 1570 USB3_EPCMD_IOC_SHIFT = 8, 1571 1572 /** Command Active <i>Access: R_W</i> */ 1573 USB3_EPCMD_ACT_BIT = 0x400, 1574 USB3_EPCMD_ACT_SHIFT = 10, 1575 1576 /** High Priority / Force RM Bit <i>Access: R_W</i> */ 1577 USB3_EPCMD_HP_FRM_BIT = 0x800, 1578 USB3_EPCMD_HP_FRM_SHIFT = 11, 1579 1580 /** Command Completion Status <i>Access: R_W</i> */ 1581 USB3_EPCMD_CMPL_STS_BITS = 0xf000, 1582 USB3_EPCMD_CMPL_STS_SHIFT = 12, 1583 1584 /** Stream Number or uFrame (input) <i>Access: R_W</i> */ 1585 USB3_EPCMD_STR_NUM_OR_UF_BITS = 0xffff0000, 1586 USB3_EPCMD_STR_NUM_OR_UF_SHIFT = 16, 1587 1588 /** Transfer Resource Index (output) <i>Access: R_W</i> */ 1589 USB3_EPCMD_XFER_RSRC_IDX_BITS = 0x007f0000, 1590 USB3_EPCMD_XFER_RSRC_IDX_SHIFT = 16, 1591 } depcmd_data_t; 1592 1593 /** 1594 * Device Endpoint Specific Registers <i>Offsets 800h-9ECh for OUT, 1595 * 810h-9FCh for IN</i>. 1596 * There will be one set of endpoint registers per logical endpoint 1597 * implemented. 1598 */ 1599 typedef struct usb3_dev_ep_regs { 1600 1601 #define USB3_DEV_OUT_EP_REG_OFFSET 0x800 1602 #define USB3_DEV_IN_EP_REG_OFFSET 0x810 1603 #define USB3_EP_REG_OFFSET 0x20 1604 1605 /** Device Endpoint Command Parameter 2 Register <i>Offset: 800h/810h + 1606 * (ep_num * 20h) + 00h</i> */ 1607 volatile uint32_t depcmdpar2; 1608 1609 /** Device Endpoint Command Parameter 1 Register <i>Offset: 800h/810h + 1610 * (ep_num * 20h) + 04h</i> */ 1611 volatile uint32_t depcmdpar1; 1612 1613 /** Device Endpoint Command Parameter 0 Register <i>Offset: 800h/810h + 1614 * (ep_num * 20h) + 08h</i> */ 1615 volatile uint32_t depcmdpar0; 1616 1617 /** Device Endpoint Command Register <i>Offset: 800h/810h + 1618 * (ep_num * 20h) + 0Ch</i>. 1619 * Fields defined in enum @ref depcmd_data. */ 1620 volatile uint32_t depcmd; 1621 1622 /** reserved <i>Offset: 800h/810h + 1623 * (ep_num * 20h) + 10h-1Ch</i> */ 1624 volatile uint32_t reserved[4]; 1625 } usb3_dev_ep_regs_t; 1626 1627 1628 /****************************************************************************/ 1629 /* DMA Descriptor Specific Structures */ 1630 1631 /** 1632 * This enum represents the bit fields in the DMA Descriptor 1633 * Status quadlet. 1634 */ 1635 typedef enum desc_sts_data { 1636 /** Transfer Count */ 1637 USB3_DSCSTS_XFRCNT_MAX = 0x1000000, //16MB 1638 USB3_DSCSTS_XFRCNT_BITS = 0x00ffffff, 1639 USB3_DSCSTS_XFRCNT_SHIFT = 0, 1640 1641 /** Packet Count Minus 1 (for HS IN transfers) */ 1642 USB3_DSCSTS_PCM1_BITS = 0x03000000, 1643 USB3_DSCSTS_PCM1_SHIFT = 24, 1644 1645 /** Transfer Request Block Response */ 1646 USB3_DSCSTS_TRBRSP_BITS = 0xf0000000, 1647 USB3_DSCSTS_TRBRSP_SHIFT = 28, 1648 1649 USB3_TRBRSP_MISSED_ISOC_IN = 1, 1650 USB3_TRBRSP_SETUP_PEND = 2, 1651 USB3_TRBRSP_XFER_IN_PROG = 4, 1652 } desc_sts_data_t; 1653 1654 /** 1655 * This enum represents the bit fields in the DMA Descriptor 1656 * Control quadlet. 1657 */ 1658 typedef enum desc_ctl_data { 1659 /** Hardware-Owned bit */ 1660 USB3_DSCCTL_HWO_BIT = 0x00000001, 1661 USB3_DSCCTL_HWO_SHIFT = 0, 1662 1663 /** Last Descriptor bit */ 1664 USB3_DSCCTL_LST_BIT = 0x00000002, 1665 USB3_DSCCTL_LST_SHIFT = 1, 1666 1667 /** Chain Buffer bit */ 1668 USB3_DSCCTL_CHN_BIT = 0x00000004, 1669 USB3_DSCCTL_CHN_SHIFT = 2, 1670 1671 /** Continue on Short Packet bit */ 1672 USB3_DSCCTL_CSP_BIT = 0x00000008, 1673 USB3_DSCCTL_CSP_SHIFT = 3, 1674 1675 /** Transfer Request Block Control field */ 1676 USB3_DSCCTL_TRBCTL_BITS = 0x000003f0, 1677 USB3_DSCCTL_TRBCTL_SHIFT = 4, 1678 1679 /** Transfer Request Block Control types */ 1680 USB3_DSCCTL_TRBCTL_NORMAL = 1, /** @< */ 1681 USB3_DSCCTL_TRBCTL_SETUP = 2, /** @< */ 1682 USB3_DSCCTL_TRBCTL_STATUS_2 = 3, /** @< */ 1683 USB3_DSCCTL_TRBCTL_STATUS_3 = 4, /** @< */ 1684 USB3_DSCCTL_TRBCTL_CTLDATA_1ST = 5, /** @< */ 1685 USB3_DSCCTL_TRBCTL_ISOC_1ST = 6, /** @< */ 1686 USB3_DSCCTL_TRBCTL_ISOC = 7, /** @< */ 1687 USB3_DSCCTL_TRBCTL_LINK = 8, 1688 1689 /** Interrupt on Short Packet bit */ 1690 USB3_DSCCTL_ISP_BIT = 0x00000400, 1691 USB3_DSCCTL_ISP_SHIFT = 10, 1692 #define USB3_DSCCTL_IMI_BIT USB3_DSCCTL_ISP_BIT 1693 #define USB3_DSCCTL_IMI_SHIFT USB3_DSCCTL_ISP_SHIFT 1694 1695 /** Interrupt on Completion bit */ 1696 USB3_DSCCTL_IOC_BIT = 0x00000800, 1697 USB3_DSCCTL_IOC_SHIFT = 11, 1698 1699 /** Stream ID / SOF Number */ 1700 USB3_DSCCTL_STRMID_SOFN_BITS = 0x3fffc000, 1701 USB3_DSCCTL_STRMID_SOFN_SHIFT = 14, 1702 } desc_ctl_data_t; 1703 1704 /** 1705 * DMA Descriptor structure 1706 * 1707 * DMA Descriptor structure contains 4 quadlets: 1708 * Buffer Pointer Low address, Buffer Pointer High address, Status, and Control. 1709 */ 1710 typedef struct usb3_dma_desc { 1711 /** Buffer Pointer - Low address quadlet */ 1712 uint32_t bptl; 1713 1714 /** Buffer Pointer - High address quadlet */ 1715 uint32_t bpth; 1716 1717 /** Status quadlet. Fields defined in enum @ref desc_sts_data. */ 1718 uint32_t status; 1719 1720 /** Control quadlet. Fields defined in enum @ref desc_ctl_data. */ 1721 uint32_t control; 1722 } usb3_dma_desc_t; 1723 1724 #ifdef __cplusplus 1725 } 1726 #endif 1727 1728 #endif /* __USB3_HW_H__ */ 1729 1730