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Searched refs:Vd (Results 1 – 25 of 28) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrNEON.td264 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
274 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
284 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
295 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
305 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
315 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
325 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
335 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
347 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
357 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
[all …]
DARMInstrFormats.td2218 bits<5> Vd;
2222 let Inst{22} = Vd{4};
2223 let Inst{15-12} = Vd{3-0};
2288 bits<5> Vd;
2291 let Inst{15-12} = Vd{3-0};
2292 let Inst{22} = Vd{4};
2314 bits<5> Vd;
2317 let Inst{15-12} = Vd{3-0};
2318 let Inst{22} = Vd{4};
2328 OpcodeStr, Dt, "$Vd, $Vm", "", pattern> {
[all …]
DARMInstrVFP.td1680 // if dp_operation then UInt(D:Vd) else UInt(Vd:D);
1691 // if dp_operation then UInt(D:Vd) else UInt(Vd:D);
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenGlobalISel.inc1623 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1653 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1678 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1703 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1728 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1751 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1774 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1791 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1827 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1856 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
[all …]
DARMGenMCCodeEmitter.inc8296 // op: Vd
8308 // op: Vd
8341 // op: Vd
8353 // op: Vd
8371 // op: Vd
8393 // op: Vd
8421 // op: Vd
8438 // op: Vd
8456 // op: Vd
8473 // op: Vd
[all …]
DARMGenMCPseudoLowering.inc284 // Operand: Vd
299 // Operand: Vd
DARMGenDAGISel.inc1196 /* 2541*/ OPC_RecordChild1, // #1 = $Vd
1225 …v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vd), (and:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, (xor:{ *:[v2i32] }…
1226 … // Dst: (VBSLd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1233 …v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vd), (and:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, (xor:{ *:[v1i64] }…
1234 … // Dst: (VBSLd:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vd, DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
1247 …v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vd), (and:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, (xor:{ *:[v4i32] }…
1248 … // Dst: (VBSLq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
1255 …v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vd), (and:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, (xor:{ *:[v2i64] }…
1256 … // Dst: (VBSLq:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vd, QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
1280 …Vd), (and:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, (xor:{ *:[v2i32] } (bitconvert:{ *:[v2i32] } (ARMvm…
[all …]
/third_party/mbedtls/tests/data_files/
Drsa_pkcs8_pbe_sha1_2048_3des.pem21 95gO9W6lwc+CAA7iZL4+yVzfZa652Yg2eck8EOgZ2N9r+Vd/7rPsv6ysGpU/7p/z
Drsa_pkcs8_pbe_sha1_4096_rc4_128.pem10 jl+gGBvAX5RRKz3+Vj7hb8y4n7npYJYXk+CanrsTblsBhOMaFhgup+Vd+UhHGQku
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td3745 def : InstAlias<"mvn{ $Vd.8b, $Vn.8b|.8b $Vd, $Vn}",
3746 (NOTv8i8 V64:$Vd, V64:$Vn)>;
3747 def : InstAlias<"mvn{ $Vd.16b, $Vn.16b|.16b $Vd, $Vn}",
3748 (NOTv16i8 V128:$Vd, V128:$Vn)>;
4993 (v16i8 V128:$Vd), VectorIndexB:$idx, (v16i8 V128:$Vs),
4996 V128:$Vd, VectorIndexB:$idx, V128:$Vs, VectorIndexB:$idx2)
4999 (v8i16 V128:$Vd), VectorIndexH:$idx, (v8i16 V128:$Vs),
5002 V128:$Vd, VectorIndexH:$idx, V128:$Vs, VectorIndexH:$idx2)
5005 (v4i32 V128:$Vd), VectorIndexS:$idx, (v4i32 V128:$Vs),
5008 V128:$Vd, VectorIndexS:$idx, V128:$Vs, VectorIndexS:$idx2)
[all …]
DAArch64InstrFormats.td5936 def : InstAlias<asm # "\t$Vd.4h, $Vn.4h, #0",
5937 (!cast<Instruction>(NAME # v4i16rz) V64:$Vd, V64:$Vn), 0>;
5938 def : InstAlias<asm # "\t$Vd.8h, $Vn.8h, #0",
5939 (!cast<Instruction>(NAME # v8i16rz) V128:$Vd, V128:$Vn), 0>;
5941 def : InstAlias<asm # "\t$Vd.2s, $Vn.2s, #0",
5942 (!cast<Instruction>(NAME # v2i32rz) V64:$Vd, V64:$Vn), 0>;
5943 def : InstAlias<asm # "\t$Vd.4s, $Vn.4s, #0",
5944 (!cast<Instruction>(NAME # v4i32rz) V128:$Vd, V128:$Vn), 0>;
5945 def : InstAlias<asm # "\t$Vd.2d, $Vn.2d, #0",
5946 (!cast<Instruction>(NAME # v2i64rz) V128:$Vd, V128:$Vn), 0>;
[all …]
DAArch64SchedPredicates.td411 [// MOVI Vd, #0
416 // MOVI Vd, #0, LSL #0
DAArch64SchedCyclone.td322 // FMOVv2f64ns Vd.2d, #0.0
331 // ORR.16b Vd,Vn,Vn
632 // Vd is read 5 cycles after issuing the vector load.
DSVEInstrFormats.td4112 : I<(outs dstRegClass:$Vd), (ins PPR3bAny:$Pg, zprty:$Zn),
4113 asm, "\t$Vd, $Pg, $Zn",
4117 bits<5> Vd;
4126 let Inst{4-0} = Vd;
5275 : I<(outs dstRegtype:$Vd), (ins PPR3bAny:$Pg, zprty:$Zn),
5276 asm, "\t$Vd, $Pg, $Zn",
5280 bits<5> Vd;
5289 let Inst{4-0} = Vd;
6465 : I<(outs regtype:$Vd), (ins PPR3bAny:$Pg, zprty:$Zn),
6466 asm, "\t$Vd, $Pg, $Zn",
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp1572 unsigned Vd = fieldFromInstruction(Val, 8, 5); in DecodeSPRRegListOperand() local
1576 if (regs == 0 || (Vd + regs) > 32) { in DecodeSPRRegListOperand()
1577 regs = Vd + regs > 32 ? 32 - Vd : regs; in DecodeSPRRegListOperand()
1582 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) in DecodeSPRRegListOperand()
1585 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) in DecodeSPRRegListOperand()
1596 unsigned Vd = fieldFromInstruction(Val, 8, 5); in DecodeDPRRegListOperand() local
1600 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { in DecodeDPRRegListOperand()
1601 regs = Vd + regs > 32 ? 32 - Vd : regs; in DecodeDPRRegListOperand()
1607 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) in DecodeDPRRegListOperand()
1610 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) in DecodeDPRRegListOperand()
[all …]
/third_party/boost/libs/wave/test/testwave/testfiles/
Dt_5_035.hpp888 #define Vd macro
/third_party/libxml2/macos/
Dlibxml2.mcp.xml.sit.hqx51 q-!22J4GALA2Gf-r8NJpMV10V9AVG"3Ji(mbAf!4hB*[U"Z!k`i#JHp(Vd+!)[6i
260 eDqB!k2qVPc-b%D$PPCBkjU&2G*-#Z6L#E6qKI`l5ZCr&"6Vd+FBiNNFdLi&h5G+
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonInstrInfo.cpp1167 Register Vd = MI.getOperand(0).getReg(); in expandPostRAPseudo() local
1168 BuildMI(MBB, MI, DL, get(Hexagon::V6_vsubw_dv), Vd) in expandPostRAPseudo()
1169 .addReg(Vd, RegState::Undef) in expandPostRAPseudo()
1170 .addReg(Vd, RegState::Undef); in expandPostRAPseudo()
DHexagonPseudo.td468 def PS_vdd0: InstHexagon<(outs HvxWR:$Vd), (ins), "", [], "",
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenMCCodeEmitter.inc6600 // op: Vd
12327 // op: Vd
12348 // op: Vd
12367 // op: Vd
12389 // op: Vd
12423 // op: Vd
12443 // op: Vd
15218 // op: Vd
DAArch64GenGlobalISel.inc36090 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
36108 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
37292 …Vd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx, V128:{ *:[v16i8] }:$Vs, (imm:{ *:[i64] })<…
37295 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
37325 …Vd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx, V128:{ *:[v8i16] }:$Vs, (imm:{ *:[i64] })<…
37328 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
37358 …Vd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, V128:{ *:[v4i32] }:$Vs, (imm:{ *:[i64] })<…
37361 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
37391 …Vd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx, V128:{ *:[v2i64] }:$Vs, (imm:{ *:[i64] })<…
37394 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
DAArch64GenAsmWriter.inc20145 // (NOTv16i8 V128:$Vd, V128:$Vn) - 2353
20148 // (NOTv8i8 V64:$Vd, V64:$Vn) - 2355
/third_party/skia/third_party/externals/libjpeg-turbo/testimages/
Dtestorig.ppm4 …18A.>K1Pb<bxIk�Lu�Qt�Ps�Ms�Pq�Rp�Rr�Sr�Sr�Sp�Om�Mm�Kp�Ls�Ot�Qv�Uz�Y{�^z�_q�Vd�JZ�D]�JW~GRyBe\Me\Me…
/third_party/libjpeg/
Dtestimg.ppm5 …38A0>K1Pa=ayGk�Lu�Pt�Nr�Mq�Pq�Ro�Rr�Sr�Sr�Qp�Om�Km�Ip�Lr�Ot�Qv�Sx�Y{�^z�_q�Vd�JY�?]�NVGQzBe\Me\Me…
/third_party/flutter/skia/third_party/externals/libjpeg-turbo/testimages/
Dtestorig.ppm4 …18A.>K1Pb<bxIk�Lu�Qt�Ps�Ms�Pq�Rp�Rr�Sr�Sr�Sp�Om�Mm�Kp�Ls�Ot�Qv�Uz�Y{�^z�_q�Vd�JZ�D]�JW~GRyBe\Me\Me…

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